IEEE Design & Test

Papers
(The TQCC of IEEE Design & Test is 2. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-04-01 to 2025-04-01.)
ArticleCitations
Linear Algorithmic Checksums for Deep Neural Network Error Detection: Fundamentals & Recent Advancements45
Report on the 2024 Embedded Systems Week (ESWEEK)40
Top Picks in Hardware and Embedded Security 202238
Table of Contents37
IEEE Foundation36
IEEE Membership34
Compact and High-Performing Five-Stage Pipeline RISC-V Microprocessor Designed for IoT Applications27
IEEE Membership26
Front Cover25
SCA Strikes Back: Reverse-Engineering Neural Network Architectures Using Side Channels23
Front Cover23
Table of Contents19
Machine Learning and Algorithms: Let Us Team Up for EDA15
On the Mitigation of Read Disturbances in Neuromorphic Inference Hardware15
Autonomous Systems Design: Charting a New Discipline15
Machine Learning for CAD/EDA: The Road Ahead15
IEEE Design & Test Publication Information15
Guest Editors’ Introduction: Stochastic Computing for Neuromorphic Applications15
BHT-NoC: Blaming Hardware Trojans in NoC Routers14
HPC-Based Malware Detectors Actually Work: Transition to Practice After a Decade of Research14
Report on the 2021 Embedded Systems Week (ESWEEK)13
On the Implementation of Fixed-Point Exponential Function for Machine Learning and Signal- Processing Accelerators13
RosettaStone: Connecting the Past, Present, and Future of Physical Design Research12
On Backside Probing Techniques and Their Emerging Security Threats12
STLs for GPUs: Using High-Level Language Approaches12
Special Issue on Testability and Dependability of Artificial Intelligence Hardware11
Open-Source Multilevel Converter Power IC Design and Test11
40th IEEE VLSI Test Symposium 202211
An Energy-Aware Nanoscale Design of Reversible Atomic Silicon Based on Miller Algorithm11
A Survey of High-Level Synthesis-Based Hardware (IP) Watermarking Approaches11
Product Health Insights Using Telemetry11
A NoC-Based Spatial DNN Inference Accelerator With Memory-Friendly Dataflow11
A Reinforcement Learning Framework With Region-Awareness and Shared Path Experience for Efficient Routing in Networks-on-Chip10
Special Issue on Postquantum Cryptography for Internet of Things10
Losing My Memory9
Fast Analysis Using Finite Queuing Model for Multilayer NoCs9
Side Channel and Fault Analyses on Memristor-Based Logic In-Memory9
PiN: Processing in Network-on-Chip9
Robust and Secure Systems8
Breaking Silos to Guarantee Control Stability with Communication over Ethernet TSN8
Background Receiver IQ Imbalance Correction for In-Field Testing8
Exact Stochastic Computing Multiplication in Memristive Memory8
Attack of the AI Papers8
Reconfigurable Pipelined Control Systems8
Self-Healing of Redundant FLASH ADCs7
Fair and Comprehensive Benchmarking of Machine Learning Processing Chips7
Adaptive Integer Linear Programming Model for Optimal Qubit Permutation7
TTTC News7
Computing-In-Memory Using Ferroelectrics: From Single- to Multi-Input Logic7
Topology-Aided Multicorner Timing Predictor for Wide Voltage Design7
Low-Power High-Throughput Architecture for AV1 Arithmetic Decoder6
IEEE Design&Test Publication Information6
TechRxiv: Share Your Preprint Research with the World!6
Deep Reinforcement Learning for Optimization at Early Design Stages6
Front Cover6
IEEE Women in Engineering6
Update Your IEEE Profile6
ISLPED 2021: The 25th Anniversary!6
Enabling Design Methodologies and Future Trends for Edge AI: Specialization and Codesign6
Front Cover6
IEEE Foundation5
Binary Forward-Only Algorithms5
Furthering Moore’s Law Integration Benefits in the Chiplet Era5
Table of Contents5
IC SEM Reverse Engineering Tutorial using Artificial Intelligence5
Front Cover5
TechRxiv: Share Your Preprint Research With the World!5
IEEE Foundation5
IEEE Design & Test Publication Information5
IEEE Design & Test Publication Information5
Toward Standardized Vulnerability Assessment of Advanced Packaging Against Probing Attacks5
Join IEEE5
SPOCK: Reverse Packet Traversal for Deadlock Recovery5
IEEE Design&Test publication information4
Design of Single-Bit Fault-Tolerant Reversible Circuits4
Front Cover4
Front Cover4
IEEE Design&Test EIC Call for Nominations4
[Front cover]4
IEEE Design&Test publication information4
Shape Engineering for Custom Nanomagnetic Logic Circuits in NMLSim 2.04
Being Learned4
Front Cover4
A Mixture of Experts Approach for Low-Cost DNN Customization4
Proceedings of the IEEE4
The AXIOM Project: IoT on Heterogeneous Embedded Platforms4
Ladder Scaling Fracmemristor: A Second Emerging Circuit Structure of Fractional-Order Memristor4
Flexible and Portable Management of Secure Scan Implementations Exploiting P1687.1 Extensions4
IEEE Foundation4
Toward Agile Hardware Designs With Chisel: A Network Use Case4
Guest Editors’ Introduction: Machine Intelligence at the Edge4
Detecting and Scoring Equipment Faults in Real Time During Semiconductor Test Processes4
Front Cover3
Front Cover3
IEEE Membership3
Turbo-FHE: Accelerating Fully Homomorphic Encryption with FPGA and HBM Integration3
IEEE.tv3
Front Cover3
Table of Contents3
May CEDA Currents3
Table of Contents3
Front Cover3
Get in the Conversation!3
IEEE Design & Test Publication Information3
Open-Source Electronic Design Automation (EDA) Tools2
Improvement of Functional Safety of the Level-Crossing Barrier Machine by a Noninvasive Angle-Detection Method2
Testing Embedded Toggle Generation Through On-Chip IR-Drop Measurements2
Creating a Foundation for Next-Generation Autonomous Systems2
DRAM PUFs in Commodity Devices2
The 2021 Asia and South Pacific Design Automation Conference (ASPDAC)2
Spectre Returns! Speculation Attacks Using the Return Stack Buffer2
End-to-End Automated Exploit Generation for Processor Security Validation2
Recap of the 39th Edition of the International Conference on Computer-Aided Design (ICCAD 2020)2
Report on the 2023 Embedded Systems Week (ESWEEK)2
A BIST Approach to Approximate Co-Testing of Embedded Data Converters2
ISLPED 2023: International Symposium on Low-Power Electronics and Design2
The 41st IEEE VLSI Test Symposium2
A Conceptual Framework for Stochastic Neuromorphic Computing2
Multiplication Circuit Architecture for Error- Tolerant CNN-Based Keywords Speech Recognition2
A Survey of Neuromorphic Computing-in-Memory: Architectures, Simulators, and Security2
Estimating Code Vulnerability to Timing Errors Via Microarchitecture-Aware Machine Learning2
Mitigating Speculative Execution Attacks via Context-Sensitive Fencing2
Guest Editors’ Introduction: Special Issue on Top Picks in Hardware and Embedded Security2
An Open-Source EDA Flow for Asynchronous Logic2
Recap of the 61st ACM/IEEE Design Automation Conference (DAC61): The “Chips to Systems Conference”2
Safety Ethics for Design and Test of Automated Driving Features2
Special Issue on Ethics in Computing2
Secure FFT IP Using C-Way Partitioning-Based Obfuscation and Fingerprint2
Exploring Resilience of LPDRAM Against RowHammer2
Bandpass NGD Time- Domain Experimental Test of Double-Li Microstrip Circuit2
Special Issue on Design and Test of Multidie Packages2
Design for Test With Unreliable Memories by Restoring the Beauty of Randomness2
Design and Test of Innovative Three-Couplers-Based Bandpass Negative Group Delay Active Circuit2
25 Years (and a Bit More) of The Last Byte2
Automated Probe-Mark Analysis for Advanced Probe Technology Characterization2
Training Binarized Neural Networks Using Ternary Multipliers2
Open-Source Silicon—Unleashing Innovation and Collaboration2
The 28th IEEE European Test Symposium2
Report on First and Second ACM/IEEE Workshop on Machine Learning for CAD (MLCAD)2
Tipping the Balance: Imbalanced Classes in Deep-Learning Side-Channel Analysis2
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