IEEE Design & Test

Papers
(The median citation count of IEEE Design & Test is 0. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-04-01 to 2024-04-01.)
ArticleCitations
Robust Machine Learning Systems: Challenges,Current Trends, Perspectives, and the Road Ahead80
A Survey on Energy Management for Mobile and IoT Devices47
Neural Network Inference on Mobile SoCs46
A Survey of Silicon Photonics for Energy-Efficient Manycore Computing38
Dynamic Energy and Thermal Management of Multi-core Mobile Platforms: A Survey33
Are CNNs Reliable Enough for Critical Applications? An Exploratory Study31
ALIGN: A System for Automating Analog Layout29
Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs25
A Survey of Neuromorphic Computing-in-Memory: Architectures, Simulators, and Security25
MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII24
GLU3.0: Fast GPU-based Parallel Sparse LU Factorization for Circuit Simulation23
Enabling Design Methodologies and Future Trends for Edge AI: Specialization and Codesign22
An Inside Job: Remote Power Analysis Attacks on FPGAs22
From Less Batteries to Battery-Less Alert Systems with Wide Power Adaptation down to nWs—Toward a Smarter, Greener World20
Analog-to-Digital Converter Design Exploration for Compute-in-Memory Accelerators19
A Survey on Machine Learning Accelerators and Evolutionary Hardware Platforms18
Survey on Education for Cyber-Physical Systems16
Fair and Comprehensive Benchmarking of Machine Learning Processing Chips16
Secure Interposer-Based Heterogeneous Integration15
Spectre Returns! Speculation Attacks Using the Return Stack Buffer13
Real Silicon Using Open-Source EDA12
Discovering CAN Specification Using On-Board Diagnostics12
Automatic Detection of Respiratory Symptoms Using a Low-Power Multi-Input CNN Processor11
SIT: Stochastic Input Transformation to Defend Against Adversarial Attacks on Deep Neural Networks11
EM Side Channels in Hardware Security: Attacks and Defenses11
Merged Logic and Memory Fabrics for Accelerating Machine Learning Workloads10
Cyber-Physical Systems Security Education Through Hands-on Lab Exercises10
Exact Stochastic Computing Multiplication in Memristive Memory10
Verification Approaches for Learning-Enabled Autonomous Cyber–Physical Systems10
Semantic Adversarial Deep Learning10
An Energy-Aware Nanoscale Design of Reversible Atomic Silicon Based on Miller Algorithm10
Backdoor Suppression in Neural Networks using Input Fuzzing and Majority Voting10
Enabling Timing Error Resilience for Low-Power Systolic-Array Based Deep Learning Accelerators10
An Open-Source EDA Flow for Asynchronous Logic10
Impact of Memory Voltage Scaling on Accuracy and Resilience of Deep Learning Based Edge Devices9
Breaking Silos to Guarantee Control Stability with Communication over Ethernet TSN9
EM/Power Side-Channel Attack: White-Box Modeling and Signature Attenuation Countermeasures9
Three-Input NPN Class Gate Library for Atomic Silicon Quantum Dots9
SSCNets: Robustifying DNNs using Secure Selective Convolutional Filters9
Machine Learning for CAD/EDA: The Road Ahead9
EdgeAl: A Vision for Deep Learning in the IoT Era9
The Role of Competence Networks in the Era of Cyber-Physical Systems — Promoting Knowledge Sharing and Knowledge Exchange9
OpenTimer v2: A Parallel Incremental Timing Analysis Engine9
Training Large-scale Artificial Neural Networks on Simulated Resistive Crossbar Arrays9
FPGA-Chain: Enabling Holistic Protection of FPGA Supply Chain With Blockchain Technology9
Testability and Dependability of AI Hardware: Survey, Trends, Challenges, and Perspectives9
Hardware Obfuscation and Logic Locking: A Tutorial Introduction8
On Backside Probing Techniques and Their Emerging Security Threats8
A Cautionary Tale About Detecting Malware Using Hardware Performance Counters and Machine Learning8
Introducing IoT Subjects to an Existing Curriculum8
Self-Aware Machine Learning for Multimodal Workload Monitoring during Manual Labor on Edge Wearable Sensors8
FaCT-LSTM: Fast and Compact Ternary Architecture for LSTM Recurrent Neural Networks7
Ladder Scaling Fracmemristor: A Second Emerging Circuit Structure of Fractional-Order Memristor7
Cross-Layer Design of Automotive Systems7
A Data-Based Detection Method Against False Data Injection Attacks7
Fault: Open-Source EDA’s Missing DFT Toolchain7
Hardware Virtualization and Task Allocation for Plug-and-Play Automotive Systems7
Intelligent Chargers Will Make Mobile Devices Live Longer6
EDLAB: A Benchmark for Edge Deep Learning Accelerators6
On the Mitigation of Read Disturbances in Neuromorphic Inference Hardware6
In-Stream Correlation-Based Division and Bit-Inserting Square Root in Stochastic Computing6
Time-to-Digital Converter Compiler for On-Chip Instrumentation6
Advances in Design and Test of Monolithic 3-D ICs6
Remote Electrical-level Security Threats to Multi-Tenant FPGAs6
Project-Based CPS Education: A Case Study of an Autonomous Driving Student Project6
SCA Strikes Back: Reverse-Engineering Neural Network Architectures Using Side Channels6
Defeating Cache Timing Channels with Hardware Prefetchers5
Computing-In-Memory Using Ferroelectrics: From Single- to Multi-Input Logic5
Framework for Load Power Consumption in HANs Using Machine Learning and IoT Assistance5
A Hardware Accelerator for Language-Guided Reinforcement Learning5
Split-Chip Design to Prevent IP Reverse Engineering5
The AXIOM Project: IoT on Heterogeneous Embedded Platforms5
Machine Learning and Algorithms: Let Us Team Up for EDA5
A Novel Method for Scalable VLSI Implementation of Hyperbolic Tangent Function5
Design and Test of Crab-Shaped Negative Group Delay Circuit5
Fault-Tolerant Neural Network Accelerators With Selective TMR5
Estimating Code Vulnerability to Timing Errors Via Microarchitecture-Aware Machine Learning5
Design Challenges of Intrachiplet and Interchiplet Interconnection5
Eavesdropping Attack Detection Using Machine Learning in Network-on-Chip Architectures5
Improving DNN Hardware Accuracy by In-Memory Computing Noise Injection5
Enabling Security of Heterogeneous Integration: From Supply Chain to In-Field Operations4
EDA and Quantum Computing: a symbiotic relationship?4
Multisensing System for Parkinson’s Disease Stage Assessment Based on FPGA-Embedded Serial SVM Classifier4
Design of Single-Bit Fault-Tolerant Reversible Circuits4
Automotive Virtual In-sensor Analytics for Securing Vehicular Communication4
Security Vulnerabilities and Countermeasures in MPSoCs4
Using STLs for Effective In-Field Test of GPUs4
The Emerging Majority: Technology and Design for Superconducting Electronics4
Hardware Penetration Testing Knocks Your SoCs Off4
Event-Triggered Sensing for High-Quality and Low-Power Cardiovascular Monitoring Systems4
Deadlock-Freedom in Computational Neuroscience Simulators4
Know Your Channel First, then Calibrate Your mmWave Phased Array4
Embracing Stochasticity to Enable Neuromorphic Computing at the Edge3
Hunting Security Bugs in SoC Designs: Lessons Learned3
Remote Fault Attacks in Multitenant Cloud FPGAs3
Bandpass NGD Time- Domain Experimental Test of Double-Li Microstrip Circuit3
A Conceptual Framework for Stochastic Neuromorphic Computing3
Exact Benchmark Circuits for Logic Synthesis3
A Programmable Open Architecture Testbed for CPS Education3
High-Performance Deterministic Stochastic Computing Using Residue Number System3
Electronic, Wireless, and Photonic Network-on-Chip Security: Challenges and Countermeasures3
PyH2: Using PyMTL3 to Create Productive and Open-Source Hardware Testing Methodologies3
Broadcast-TDMA: A Cost-Effective Fault-Tolerance Method for TSV Lifetime Reliability Enhancement3
Guest Editorial: Robust Resource-Constrained Systems for Machine Learning3
Design and Test of Innovative Three-Couplers-Based Bandpass Negative Group Delay Active Circuit3
Furthering Moore’s Law Integration Benefits in the Chiplet Era3
Topology-Aided Multicorner Timing Predictor for Wide Voltage Design3
Deep Reinforcement Learning for Optimization at Early Design Stages3
Executing Data Integration Effectively and Efficiently Near the Memory3
Machine Learning in Advanced IC Design: A Methodological Survey3
Recycling Test Methods to Improve Test Capacity and Increase Chip Shipments3
SoC Security Evaluation: Reflections on Methodology and Tooling3
Integrating Interobject Scenarios with Intraobject Statecharts for Developing Reactive Systems3
Runtime Protection of Real-time Critical Control Applications against Known Threats3
Coordinated Self-Tuning Thermal Management Controller for Mobile Devices3
BHT-NoC: Blaming Hardware Trojans in NoC Routers3
Autonomous Systems Design: Charting a New Discipline3
Shape Engineering for Custom Nanomagnetic Logic Circuits in NMLSim 2.03
An Area- and Power-Efficient Stochastic Number Generator for Bayesian Sensor Fusion Circuits3
A Novel Graph-Coloring-Based Solution for Low-Power Scan Shift3
A Many-Ported and Shared Memory Architecture for High-Performance ADAS SoCs2
Lifelong Exploratory Navigation: An Architecture for Safer Mobile Robots2
An Attachable Battery–Supercapacitor Hybrid for Large Pulsed Load2
Autonomous Systems, Trust, and Guarantees2
Hardware Accelerators for Digital Signature Algorithms Dilithium and FALCON2
On the Impact of Uncertainties in Silicon-Photonic Neural Networks2
Training Binarized Neural Networks Using Ternary Multipliers2
On the Implementation of Fixed-Point Exponential Function for Machine Learning and Signal- Processing Accelerators2
Self-Healing of Redundant FLASH ADCs2
Vulnerability of Hardware Neural Networks to Dynamic Operation Point Variations2
Real-Time Requirements for ADAS Platforms Featuring Shared Memory Hierarchies2
Cloud-Ready Acceleration of Formal Method Techniques for Cyber–Physical Systems2
A Systematic Design Methodology of Formally Proven Side-Channel-Resistant Cryptographic Hardware2
Reverse-Engineering CNN Models Using Side-Channel Attacks2
High-Throughput Hardware for 3D-HEVC Depth-Map Intra Prediction2
Future Engineering Curricula: Balancing Domain Competence with CPS Readiness2
Creating a Foundation for Next-Generation Autonomous Systems2
Guest Editors’ Introduction: Stochastic Computing for Neuromorphic Applications2
Detecting Pediatric Foot Deformities Using Plantar Pressure Measurements: A Semisupervised Approach2
Power-Quality Configurable Hardware Design for AV1 Directional Intraframe Prediction2
Hardware-Based Real-Time Workload Forensics2
Datapath Extension of NPUs to Support Nonconvolutional Layers Efficiently2
Design of ₌׀₌ Shape Stub-Based Negative Group Delay Circuit2
API-Based Hardware Fault Simulation for DNN Accelerators2
Testing of Prebond Through Silicon Vias2
Real-time Hardware Implementation of ARM CoreSight Trace Decoder2
Automated Probe-Mark Analysis for Advanced Probe Technology Characterization2
RosettaStone: Connecting the Past, Present, and Future of Physical Design Research2
Flexible and Scalable BLAKE/BLAKE2 Coprocessor for Blockchain-Based IoT Applications2
Adaptive Neural Network Architectures for Power Aware Inference1
Securing CRYSTALS-Kyber in FPGA Using Duplication and Clock Randomization1
JARVA: Joint Application-Aware Oblivious Routing and Static Virtual Channel Allocation1
Affordable and Comprehensive Testing of 3-D Stacked Die Devices1
A Study on Confidence: An Unsupervised Multiagent Machine Learning Experiment1
Randomized Testing of RISC-V CPUs Using Direct Instruction Injection1
Silicon-Proven Timing Signoff Methodology Using Hazard-Free Robust Path Delay Tests1
Mitigating Speculative Execution Attacks via Context-Sensitive Fencing1
Enabling High-Level Design Strategies for High-Throughput and Low-Power NB-LDPC Decoders1
Active and Passive Physical Attacks on Neural Network Accelerators1
A Deep Transfer Learning Design Rule Checker With Synthetic Training1
Flexible and Portable Management of Secure Scan Implementations Exploiting P1687.1 Extensions1
Holding Conferences Online due to COVID-19: The DATE Experience1
Low-Power High-Throughput Architecture for AV1 Arithmetic Decoder1
Impact of Orientation on the Bias of SRAM-Based PUFs1
Guest Editors' Introduction: Education for Cyber-Physical Systems1
SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs1
Shaping Resilient AI Hardware Through DNN Computational Feature Exploitation1
Guest Editors’ Introduction: SBCCI 20191
Long-Wire Leakage: The Threat of Crosstalk1
FlooNoC: A Multi-Tb/s Wide NoC for Heterogeneous AXI4 Traffic1
SynFull-RTL: Evaluation Methodology for RTL NoC Designs1
Strange Loops in Design and Technology: 59th DAC Keynote Speech1
Texas A&M Hackin’ Aggies’ Security Verification Strategies for the 2019 Hack@DAC Competition1
A Global Self-Repair Method for TSV Arrays With Adaptive FNS-CAC Codec1
Optimal Energy Efficiency and Throughput on Partially Reversible Pipelined QCA Circuits1
End-to-End Automated Exploit Generation for Processor Security Validation1
Low-Cost Structural Monitoring of Analog Circuits for Secure and Reliable Operation1
A Reinforcement Learning Framework With Region-Awareness and Shared Path Experience for Efficient Routing in Networks-on-Chip1
Power-Saving 8K Real-Time AV1 Arithmetic Encoder Architecture1
HPC-Based Malware Detectors Actually Work: Transition to Practice After a Decade of Research1
Ethics in Sustainability1
Toward Agile Hardware Designs With Chisel: A Network Use Case1
Efficient Privacy-Aware Federated Learning by Elimination of Downstream Redundancy1
Dependable STT-MRAM With Emerging Approximation and Speculation Paradigms1
Majority-Logic-Based Self-Checking Adder in Quantum-Dot Cellular Automata1
SeMAP—A Method to Secure the Communication in NoC-Based Many-Cores1
VioNet: A Hierarchical Detailed Routing Wire-Short Violation Predictor Based on a Convolutional Neural Network1
Graph-Based Circuit Simulator for Switched Capacitor Circuits1
Traversal Packets: Opportunistic Bypass Packets for Deadlock Recovery1
Provably Secure Sequential Obfuscation for IC Metering and Piracy Avoidance1
Parallelizing GPGPU-Sim for Faster Simulation with High Fidelity1
A Mixture of Experts Approach for Low-Cost DNN Customization1
Building an Open-Source DNA Assembler Device1
Hardware-Based Fast Hybrid Morphological Reconstruction1
Applying IEEE Test Standards to Multidie Designs1
STLs for GPUs: Using High-Level Language Approaches1
A DVFS Design and Simulation Framework Using Machine Learning Models1
Determining Mechanical Stress Testing Parameters for FHE Designs with Low Computational Overhead1
A 703.4-GOPs/W Binary SegNet Processor With Computing-Near-Memory Architecture for Road Detection1
From the EIC: Education for Cyber-Physical Systems1
Ethical Design of Computers: From Semiconductors to IoT and Artificial Intelligence1
RB-OLITS: A Worst Case Reorder Buffer Size Reduction Approach for 3-D-NoC1
Adaptive Integer Linear Programming Model for Optimal Qubit Permutation0
Fast Analysis Using Finite Queuing Model for Multilayer NoCs0
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Side Channel and Fault Analyses on Memristor-Based Logic In-Memory0
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