IEEE Design & Test

Article	Citations
ISLPED 2021: The 25th Anniversary!	64
IEEE Foundation	59
Top Picks in Hardware and Embedded Security 2022	52
Flexible and Portable Management of Secure Scan Implementations Exploiting P1687.1 Extensions	40
Celebrating 20 Years of EDA: Milestones, Challenges, and Future Directions	35
Special Issue on the 2023 Symposium on Integrated Circuits and Systems Design	30
On Backside Probing Techniques and Their Emerging Security Threats	27
BHT-NoC: Blaming Hardware Trojans in NoC Routers	21
An Energy-Aware Nanoscale Design of Reversible Atomic Silicon Based on Miller Algorithm	21
SPOCK: Reverse Packet Traversal for Deadlock Recovery	21
Improvement of Functional Safety of the Level-Crossing Barrier Machine by a Noninvasive Angle-Detection Method	19
Report on the 28th Asia and South Pacific Design Automation Conference	18
Statistical Methods for Detecting Recycled Electronics: From ICs to PCBs and Beyond	18
Tipping the Balance: Imbalanced Classes in Deep-Learning Side-Channel Analysis	18
IEEE Connects You to a Universe of Information!	18
On the Impact of Uncertainties in Silicon-Photonic Neural Networks	17
Front Cover	17
An Open-Source 12-bit 10-kS/s Incremental ADC in 130-nm CMOS	17
ISCA: Intelligent Sense-Compute Adaptive Co-Optimization of Multimodal Machine Learning Kernels for Resilient mHealth Services on Wearables	16
IC Phone Home!	15
The 2022 International Conference on Computer-Aided Design (ICCAD)	15
edAttack: Hardware Trojan Attack on On-Chip Packet Compression	14
Soft and Hard Error-Correction Techniques in STT-MRAM	13
Special Issue on Wearable IoT Devices for Reliable Mobile Health Applications	13
FlooNoC: A Multi-Tb/s Wide NoC for Heterogeneous AXI4 Traffic	12

IEEE Design & Test Publication Information	10
IEEE Design&Test Publication Information	10
Table of Contents	10
Blank Page	10
Get in the Conversation!	9
The Memory Shuffle	9
Hardware/Software Coexploration for Hyperdimensional Computing on Network-on-Chip Architecture	9
Eavesdropping Attack Detection Using Machine Learning in Network-on-Chip Architectures	9
Datapath Extension of NPUs to Support Nonconvolutional Layers Efficiently	9
TTTC News	8
IEEE Design & Test Publication Information	8
Fault-Tolerant Neuromorphic Computing With Memristors Using Functional ATPG for Efficient Recalibration	8
Table of Contents	8
Special Issue on the 2021 Workshop on Top Picks in Hardware and Embedded Security	8
On the Relation Between Reliability and Entropy in Physical Unclonable Functions	7
Analog-to-Digital Converter Design Exploration for Compute-in-Memory Accelerators	7
CLEAR Cross-Layer Resilience: A Retrospective	7
BiomedBench: A Benchmark Suite of TinyML Biomedical Applications for Low-Power Wearables	7
SOC-GPIO-Based Dynamic Power Noise Control for Video Sensor Applications	7
A Survey on Machine Learning Accelerators and Evolutionary Hardware Platforms	7
Verification Approaches for Learning-Enabled Autonomous Cyber–Physical Systems	7
Remembering Arvind	7
Voltage–Resistance-Adaptive MPPT Circuit for Energy Harvesting	6
Dynamically Reconfigurable Network Protocol for Shape-Changeable Computer System	6
FPGA-Chain: Enabling Holistic Protection of FPGA Supply Chain With Blockchain Technology	6
Traversal Packets: Opportunistic Bypass Packets for Deadlock Recovery	6
Special Issue on TinyML	6
CaSA: End-to-End Quantitative Security Analysis of Randomly Mapped Caches	6
Accuracy-Configurable 2-D Gaussian Filter Architecture for Energy-Efficient Image Processing	6
IEEE Design & Test Publication Information	6
Special Issue on Approximate Computing: Challenges, Methodologies, Algorithms, and Architectures for Dependable and Secure Systems	6
Power-Quality Configurable Hardware Design for AV1 Directional Intraframe Prediction	6
IEEE Membership	5
Robust and Secure Systems	5
Binary Forward-Only Algorithms	5
A Brief 20-Year History and Future Perspectives on Sizing and Layout Synthesis of Analog/RF ICs	5
20 Years of IEEE CEDA and More of EDA	5
Table of Contents	5
Computing-In-Memory Using Ferroelectrics: From Single- to Multi-Input Logic	5
IEEE Design & Test Publication Information	5
Get in the Conversation!	5
Attack of the AI Papers	5
Front Cover	5
Physical Design for Heterogeneous Integration: Challenges and Opportunities	5
Design for Test With Unreliable Memories by Restoring the Beauty of Randomness	4
Circuits to Systems: Codesigning Efficient AI Hardware	4
Recap of the 61st ACM/IEEE Design Automation Conference (DAC61): The “Chips to Systems Conference”	4
CAFEEN: A Cooperative Approach for Energy-Efficient NoCs With Multiagent Reinforcement Learning	4
A Global Self-Repair Method for TSV Arrays With Adaptive FNS-CAC Codec	4
Recap of the 62nd ACM/IEEE Design Automation Conference (DAC62): The “Chips to Systems Conference”	4

The 28th IEEE European Test Symposium	4
Guest Editors’ Introduction: SBCCI 2020	4
Front Cover	4
Functional Verification of a RISC-V Vector Accelerator	4
Table of Contents	4
Special Issue on Design and Test of Multidie Packages	4
Estimating Code Vulnerability to Timing Errors Via Microarchitecture-Aware Machine Learning	4
ISLPED 2023: International Symposium on Low-Power Electronics and Design	4
IEEE Membership	4
IEEE Connects You to a Universe of Information!	4
Novel Technique for Manufacturing, System-Level, and In-System Testing of Large SoC Using Functional Protocol-Based High-Speed I/O	4
Table of Contents	3
Table of Contents	3
Edge AI—An Industry View	3
Using STLs for Effective In-Field Test of GPUs	3
Strange Loops in Design and Technology: 59th DAC Keynote Speech	3
SAFER: Safety Assurances for Emergent Behavior	3
Testing for Electromigration in Sub-5-nm FinFET Memories	3
Front Cover	3
IEEE Design & Test Publication Information	3
Table of Contents	3
A BIST Approach to Approximate Co-Testing of Embedded Data Converters	3
IEEE Design & Test Publication Information	3
Heuristic-Based Algorithms for Low-Complexity AV1 Intraprediction	3
Learning Your Lock: Exploiting Structural Vulnerabilities in Logic Locking	3
Seamless Thermal Optimization of Parallel Workloads	3
Special Issue on the 2023 International Symposium on Networks-on-Chip (NOCS 2023)	3
Table of Contents	3
The Future of Design for Test and Silicon Lifecycle Management	3
Special Issue on Top Picks in Test and Reliability	3
EAVREF: An Evolutionary Algorithm Based Tool for Low-Power CMOS Voltage Reference Designs	3
Long-Wire Leakage: The Threat of Crosstalk	3
SeMAP—A Method to Secure the Communication in NoC-Based Many-Cores	3
Site-to-Site Variation in Analog Multisite Testing: A Survey on Its Detection and Correction	2
Special Issue on the First IEEE Top Picks in VLSI Test and Reliability Workshop	2
TTTC News	2
IEEE App	2
IEEE Design & Test Publication Information	2
Real-Time Requirements for ADAS Platforms Featuring Shared Memory Hierarchies	2
Special Issue on NOCS 2022	2
Shaping Resilient AI Hardware Through DNN Computational Feature Exploitation	2
SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs	2
Virtualizing USB Kernel Mode Debug (KMD) Class to Guest OS for Native OS-Like Debug Experience	2
Building an Open-Source DNA Assembler Device	2
IEEE Membership	2
Special Issue on Near-Memory and In-Memory Processing	2
Analysis and Mitigation of DRAM Faults in Sparse-DNN Accelerators	2
Front Cover	2
Special Issue on Wearable IoT Devices for Reliable Mobile Health Applications	2
Postquantum Cryptography for Internet of Things	2
GlucoseHD: Predicting Glucose Levels Using Hyperdimensional Computing	2
Recap of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED’24)	2
Majority-Logic-Based Self-Checking Adder in Quantum-Dot Cellular Automata	2
This Stuff Is Great—Am I Right?	2
Is There an Answer?	2
Machine Learning in Advanced IC Design: A Methodological Survey	2
VioNet: A Hierarchical Detailed Routing Wire-Short Violation Predictor Based on a Convolutional Neural Network	2
An EMG Denoising Method Based on Flexible Wearable Sensors	2
A Case for PIM Support in General-Purpose Compilers	2
Guest Editors’ Introduction: SBCCI 2023	2
SBCCI 2022	2
Silicon Lifecycle Management (SLM): Requirements, Trends, and Opportunities	2
Rethinking SoC Verification for Secure Cross-Layer Interactions	2
Ethical Design of Computers: From Semiconductors to IoT and Artificial Intelligence	2
Leveraging RISC-V for HW/SW Codesign of Flexible and Efficient TinyML SoCs	2
3D Ferroelectric NAND In-Storage Processing Architecture for Mass Spectrometry	2
Special Issue on Benchmarking Machine Learning Systems and Applications	1
Autonomous Systems, Trust, and Guarantees	1
Impact of Partial TMR on RISC-V Processor Reliability	1
Machine Learning for CAD/EDA	1
Deadlock-Freedom in Computational Neuroscience Simulators	1
Product Health Insights Using Telemetry	1
The VCR Effect in Active-RC Continuous-Time Sigma-Delta Modulators	1
Table of Contents	1
Report on the 2021 Embedded Systems Week (ESWEEK)	1
IEEE Design & Test Publication Information	1
IEEE Design & Test Publication Information	1
The 41st IEEE VLSI Test Symposium	1
Quantum-Safe Internet of Things	1
IEEE Design & Test Publication Information	1

Guest Editors’ Introduction: Special Issue on Autonomous Systems Design	1
Analytical Model for Performance Evaluation of Token-Passing-Based WiNoCs	1
A Growing and Thriving Electronic Design, Automation, and Test Community: A DATE 2025 Perspective	1
Table of Contents	1
Spectre Returns! Speculation Attacks Using the Return Stack Buffer	1
Silent Data Corruption by 10× Test Escapes Threatens Reliable Computing	1
IEEE App	1
40th IEEE VLSI Test Symposium 2022	1
Fair and Comprehensive Benchmarking of Machine Learning Processing Chips	1
Report on the 2024 Embedded Systems Week (ESWEEK)	1
Fully Microstrip Three-Port Circuit Bandpass NGD Design and Test	1
ISLPED 2022: An Experience of a Hybrid Conference in the Time of COVID-19	1
Full Key Extraction of SNOW-V Using ML-Assisted Power SCA	1
Crypto-DSEDA: A Domain-Specific EDA Flow for CiM-Based Cryptographic Accelerators	1
IEEE Membership	1
Get in the Conversation!	1
Bandpass NGD Time- Domain Experimental Test of Double-Li Microstrip Circuit	1
Furthering Moore’s Law Integration Benefits in the Chiplet Era	1
Special Issue on 20 Years of IEEE CEDA	1
Exploring Asymmetric Autoencoder Architectures for Computationally-Efficient Neural Image Compression	1
Reverse-Engineering CNN Models Using Side-Channel Attacks	1
Background Receiver IQ Imbalance Correction for In-Field Testing	1
Front Cover	1
A Coding Efficiency-Aware Hardware Design for VVC Affine Motion Estimation Reconstructor	1
25 Years (and a Bit More) of The Last Byte	1
Table of Contents	1
IEEE Connects You to a Universe of Information!	1
ELEMENT: Energy-Efficient Multi-NoP Architecture for IMC-Based 2.5-D Accelerator for DNN Training	0
IEEE Design & Test Publication Information	0
Graph-Based Circuit Simulator for Switched Capacitor Circuits	0
Our Gated Community	0
Special Issue on 2021 Top Picks in Hardware and Embedded Security	0
Fuzzing for Automated SoC Security Verification: Challenges and Solution	0
Hard-Sign: A Hardware Watermarking Scheme Using Dated Handwritten Signature	0
IEEE Membership	0
Low-Power High-Throughput Architecture for AV1 Arithmetic Decoder	0
LATTE: Library Attack for Evaluating Hardware IP Protections Against Reverse Engineering	0
TechRxiv: Share Your Preprint Research With the World!	0
A 703.4-GOPs/W Binary SegNet Processor With Computing-Near-Memory Architecture for Road Detection	0
Open-Source Multilevel Converter Power IC Design and Test	0
Interview With Janet Olson	0
Migortho: A Design Automation Flow for QCA Circuits	0
IEEE Foundation	0
Testing for Multiple Faults in Deep Neural Networks	0
IEEE Design & Test Publication Information	0
IEEE Design & Test Publication Information	0
Interview With Yao-Wen Chang	0
Indirect Test Pattern Generation for Mixed-Signal Circuits Using Machine Learning	0
EM Side Channels in Hardware Security: Attacks and Defenses	0
Threat Detection in NoC-based Manycores using Lightweight Machine Learning Models	0
Table of Contents	0
Front Cover	0
Workload-Aware Periodic Interconnect BIST	0
Postpandemic Conferences: The DATE 2023 Experience	0
Self-Sustainable Wearable and Internet of Things (IoT) Devices for Health Monitoring: Opportunities and Challenges	0
HPC-Based Malware Detectors Actually Work: Transition to Practice After a Decade of Research	0
Front Cover	0
A Hardware Accelerator for Language-Guided Reinforcement Learning	0
Design Challenges of Intrachiplet and Interchiplet Interconnection	0
Tree-Based Unidirectional Neural Networks for Low-Power Computer Vision	0
A NoC-Based Spatial DNN Inference Accelerator With Memory-Friendly Dataflow	0
Erratum to “Ethical Design of Computers: From Semiconductors to IoT and Artificial Intelligence”	0
PiN: Processing in Network-on-Chip	0
STAR: A Mixed Analog Stochastic In-DRAM Convolutional Neural Network Accelerator	0
FALCON: An FPGA Emulation Platform for Domain-Specific SoCs (DSSoCs)	0
Recap of the 29th Edition of the Asia and South Pacific Design Automation Conference (ASPDAC 2024)	0
Addressing the Cross-Temperature Issue in 3D NAND Flash Memories: Characterization and Mitigation for Solid State Drives	0
API-Based Hardware Fault Simulation for DNN Accelerators	0
Table of Contents	0
Affordable and Comprehensive Testing of 3-D Stacked Die Devices	0
Memory Usage Estimation for Dataflow-Model-Based Software Development Methodology	0
Toward Attention-Based TinyML: A Heterogeneous Accelerated Architecture and Automated Deployment Flow	0
On the Implementation of Fixed-Point Exponential Function for Machine Learning and Signal- Processing Accelerators	0
Testability and Dependability of AI Hardware: Survey, Trends, Challenges, and Perspectives	0
Using Approximate Circuits Against Hardware Trojans	0
Front Cover	0
Remote Power Side- Channel Attacks on FPGAs	0
Lynn Conway: Two Remembrances	0
Secure Interposer-Based Heterogeneous Integration	0
Efficient Privacy-Aware Federated Learning by Elimination of Downstream Redundancy	0
Front Cover	0
Time-Bomb HLS Trojan for Performance Degradation Payload	0
IEEE Membership	0
Dependable STT-MRAM With Emerging Approximation and Speculation Paradigms	0
Machine Learning for CAD/EDA: The Road Ahead	0
SIT: Stochastic Input Transformation to Defend Against Adversarial Attacks on Deep Neural Networks	0
Linear Algorithmic Checksums for Deep-Neural-Network Error Detection: Fundamentals and Recent Advancements	0
IEEE Design & Test Publication Information	0
TechRxiv: Share Your Preprint Research With the World!	0
Front Cover	0
Efficient Aspect Verification and Debugging of High-Performance Microprocessor Designs	0
Front Cover	0
IEEE Design & Test Publication Information	0
ViT-Reg: Regression-Focused Hardware-Aware Fine-Tuning for ViT on TinyML Platforms	0
Table of Contents	0