IEEE Design & Test

Article	Citations
Robust Machine Learning Systems: Challenges,Current Trends, Perspectives, and the Road Ahead	78
A Survey on Energy Management for Mobile and IoT Devices	47
Neural Network Inference on Mobile SoCs	45
A Survey of Silicon Photonics for Energy-Efficient Manycore Computing	38
Dynamic Energy and Thermal Management of Multi-core Mobile Platforms: A Survey	31
Are CNNs Reliable Enough for Critical Applications? An Exploratory Study	31
ALIGN: A System for Automating Analog Layout	25
Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs	25
MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII	23
Enabling Design Methodologies and Future Trends for Edge AI: Specialization and Codesign	22
GLU3.0: Fast GPU-based Parallel Sparse LU Factorization for Circuit Simulation	22
A Survey of Neuromorphic Computing-in-Memory: Architectures, Simulators, and Security	21
An Inside Job: Remote Power Analysis Attacks on FPGAs	20
From Less Batteries to Battery-Less Alert Systems with Wide Power Adaptation down to nWs—Toward a Smarter, Greener World	19
A Survey on Machine Learning Accelerators and Evolutionary Hardware Platforms	17
Analog-to-Digital Converter Design Exploration for Compute-in-Memory Accelerators	17
Survey on Education for Cyber-Physical Systems	16
Fair and Comprehensive Benchmarking of Machine Learning Processing Chips	16
Secure Interposer-Based Heterogeneous Integration	14
Discovering CAN Specification Using On-Board Diagnostics	12
Real Silicon Using Open-Source EDA	12
SIT: Stochastic Input Transformation to Defend Against Adversarial Attacks on Deep Neural Networks	11
EM Side Channels in Hardware Security: Attacks and Defenses	11
Automatic Detection of Respiratory Symptoms Using a Low-Power Multi-Input CNN Processor	11
Merged Logic and Memory Fabrics for Accelerating Machine Learning Workloads	10

Cyber-Physical Systems Security Education Through Hands-on Lab Exercises	10
An Energy-Aware Nanoscale Design of Reversible Atomic Silicon Based on Miller Algorithm	10
Verification Approaches for Learning-Enabled Autonomous Cyber–Physical Systems	10
Semantic Adversarial Deep Learning	10
Backdoor Suppression in Neural Networks using Input Fuzzing and Majority Voting	10
Enabling Timing Error Resilience for Low-Power Systolic-Array Based Deep Learning Accelerators	10
An Open-Source EDA Flow for Asynchronous Logic	10
EM/Power Side-Channel Attack: White-Box Modeling and Signature Attenuation Countermeasures	9
Impact of Memory Voltage Scaling on Accuracy and Resilience of Deep Learning Based Edge Devices	9
Exact Stochastic Computing Multiplication in Memristive Memory	9
The Role of Competence Networks in the Era of Cyber-Physical Systems — Promoting Knowledge Sharing and Knowledge Exchange	9
SSCNets: Robustifying DNNs using Secure Selective Convolutional Filters	9
EdgeAl: A Vision for Deep Learning in the IoT Era	9
OpenTimer v2: A Parallel Incremental Timing Analysis Engine	9
Training Large-scale Artificial Neural Networks on Simulated Resistive Crossbar Arrays	9
Hardware Obfuscation and Logic Locking: A Tutorial Introduction	8
Self-Aware Machine Learning for Multimodal Workload Monitoring during Manual Labor on Edge Wearable Sensors	8
A Cautionary Tale About Detecting Malware Using Hardware Performance Counters and Machine Learning	8
Testability and Dependability of AI Hardware: Survey, Trends, Challenges, and Perspectives	8
Introducing IoT Subjects to an Existing Curriculum	8
FPGA-Chain: Enabling Holistic Protection of FPGA Supply Chain With Blockchain Technology	8
FaCT-LSTM: Fast and Compact Ternary Architecture for LSTM Recurrent Neural Networks	7
Ladder Scaling Fracmemristor: A Second Emerging Circuit Structure of Fractional-Order Memristor	7
On Backside Probing Techniques and Their Emerging Security Threats	7
Three-Input NPN Class Gate Library for Atomic Silicon Quantum Dots	7
Breaking Silos to Guarantee Control Stability with Communication over Ethernet TSN	7
A Data-Based Detection Method Against False Data Injection Attacks	7
Hardware Virtualization and Task Allocation for Plug-and-Play Automotive Systems	7
Machine Learning for CAD/EDA: The Road Ahead	7
Fault: Open-Source EDA’s Missing DFT Toolchain	6
Remote Electrical-level Security Threats to Multi-Tenant FPGAs	6
Cross-Layer Design of Automotive Systems	6
In-Stream Correlation-Based Division and Bit-Inserting Square Root in Stochastic Computing	6
EDLAB: A Benchmark for Edge Deep Learning Accelerators	6
On the Mitigation of Read Disturbances in Neuromorphic Inference Hardware	6
Project-Based CPS Education: A Case Study of an Autonomous Driving Student Project	6
Time-to-Digital Converter Compiler for On-Chip Instrumentation	6
Advances in Design and Test of Monolithic 3-D ICs	6
Intelligent Chargers Will Make Mobile Devices Live Longer	5
A Hardware Accelerator for Language-Guided Reinforcement Learning	5
Fault-Tolerant Neural Network Accelerators With Selective TMR	5
Estimating Code Vulnerability to Timing Errors Via Microarchitecture-Aware Machine Learning	5
SCA Strikes Back: Reverse-Engineering Neural Network Architectures Using Side Channels	5
Framework for Load Power Consumption in HANs Using Machine Learning and IoT Assistance	5
Design and Test of Crab-Shaped Negative Group Delay Circuit	5
Split-Chip Design to Prevent IP Reverse Engineering	5
The AXIOM Project: IoT on Heterogeneous Embedded Platforms	5
Machine Learning and Algorithms: Let Us Team Up for EDA	5
A Novel Method for Scalable VLSI Implementation of Hyperbolic Tangent Function	5
Eavesdropping Attack Detection Using Machine Learning in Network-on-Chip Architectures	5

Defeating Cache Timing Channels with Hardware Prefetchers	5
Computing-In-Memory Using Ferroelectrics: From Single- to Multi-Input Logic	5
Automotive Virtual In-sensor Analytics for Securing Vehicular Communication	4
EDA and Quantum Computing: a symbiotic relationship?	4
Using STLs for Effective In-Field Test of GPUs	4
Know Your Channel First, then Calibrate Your mmWave Phased Array	4
Security Vulnerabilities and Countermeasures in MPSoCs	4
Improving DNN Hardware Accuracy by In-Memory Computing Noise Injection	4
Design of Single-Bit Fault-Tolerant Reversible Circuits	4
Design Challenges of Intrachiplet and Interchiplet Interconnection	4
The Emerging Majority: Technology and Design for Superconducting Electronics	4
Event-Triggered Sensing for High-Quality and Low-Power Cardiovascular Monitoring Systems	4
Deadlock-Freedom in Computational Neuroscience Simulators	4
Hardware Penetration Testing Knocks Your SoCs Off	4
Multisensing System for Parkinson’s Disease Stage Assessment Based on FPGA-Embedded Serial SVM Classifier	4
Embracing Stochasticity to Enable Neuromorphic Computing at the Edge	3
Integrating Interobject Scenarios with Intraobject Statecharts for Developing Reactive Systems	3
Remote Fault Attacks in Multitenant Cloud FPGAs	3
Bandpass NGD Time- Domain Experimental Test of Double-Li Microstrip Circuit	3
A Conceptual Framework for Stochastic Neuromorphic Computing	3
Topology-Aided Multicorner Timing Predictor for Wide Voltage Design	3
Shape Engineering for Custom Nanomagnetic Logic Circuits in NMLSim 2.0	3
Machine Learning in Advanced IC Design: A Methodological Survey	3
Recycling Test Methods to Improve Test Capacity and Increase Chip Shipments	3
Electronic, Wireless, and Photonic Network-on-Chip Security: Challenges and Countermeasures	3
Broadcast-TDMA: A Cost-Effective Fault-Tolerance Method for TSV Lifetime Reliability Enhancement	3
Runtime Protection of Real-time Critical Control Applications against Known Threats	3
Design and Test of Innovative Three-Couplers-Based Bandpass Negative Group Delay Active Circuit	3
Exact Benchmark Circuits for Logic Synthesis	3
A Programmable Open Architecture Testbed for CPS Education	3
Executing Data Integration Effectively and Efficiently Near the Memory	3
An Area- and Power-Efficient Stochastic Number Generator for Bayesian Sensor Fusion Circuits	3
PyH2: Using PyMTL3 to Create Productive and Open-Source Hardware Testing Methodologies	3
Hunting Security Bugs in SoC Designs: Lessons Learned	3
Guest Editorial: Robust Resource-Constrained Systems for Machine Learning	3
Coordinated Self-Tuning Thermal Management Controller for Mobile Devices	3
BHT-NoC: Blaming Hardware Trojans in NoC Routers	3
Deep Reinforcement Learning for Optimization at Early Design Stages	3
High-Performance Deterministic Stochastic Computing Using Residue Number System	3
A Novel Graph-Coloring-Based Solution for Low-Power Scan Shift	3
SoC Security Evaluation: Reflections on Methodology and Tooling	2
Datapath Extension of NPUs to Support Nonconvolutional Layers Efficiently	2
A Systematic Design Methodology of Formally Proven Side-Channel-Resistant Cryptographic Hardware	2
Reverse-Engineering CNN Models Using Side-Channel Attacks	2
High-Throughput Hardware for 3D-HEVC Depth-Map Intra Prediction	2
Future Engineering Curricula: Balancing Domain Competence with CPS Readiness	2
Creating a Foundation for Next-Generation Autonomous Systems	2
Guest Editors’ Introduction: Stochastic Computing for Neuromorphic Applications	2
Self-Healing of Redundant FLASH ADCs	2
Flexible and Scalable BLAKE/BLAKE2 Coprocessor for Blockchain-Based IoT Applications	2
A Many-Ported and Shared Memory Architecture for High-Performance ADAS SoCs	2
Hardware-Based Real-Time Workload Forensics	2
Enabling Security of Heterogeneous Integration: From Supply Chain to In-Field Operations	2
Design of ₌׀₌ Shape Stub-Based Negative Group Delay Circuit	2
API-Based Hardware Fault Simulation for DNN Accelerators	2
Testing of Prebond Through Silicon Vias	2
Real-time Hardware Implementation of ARM CoreSight Trace Decoder	2
Automated Probe-Mark Analysis for Advanced Probe Technology Characterization	2
Autonomous Systems Design: Charting a New Discipline	2
On the Implementation of Fixed-Point Exponential Function for Machine Learning and Signal- Processing Accelerators	2
Vulnerability of Hardware Neural Networks to Dynamic Operation Point Variations	2
Real-Time Requirements for ADAS Platforms Featuring Shared Memory Hierarchies	2
Lifelong Exploratory Navigation: An Architecture for Safer Mobile Robots	2
An Attachable Battery–Supercapacitor Hybrid for Large Pulsed Load	2
Autonomous Systems, Trust, and Guarantees	2
Hardware Accelerators for Digital Signature Algorithms Dilithium and FALCON	2
On the Impact of Uncertainties in Silicon-Photonic Neural Networks	2
Training Binarized Neural Networks Using Ternary Multipliers	2
Furthering Moore’s Law Integration Benefits in the Chiplet Era	2
RosettaStone: Connecting the Past, Present, and Future of Physical Design Research	2
Power-Quality Configurable Hardware Design for AV1 Directional Intraframe Prediction	2
RB-OLITS: A Worst Case Reorder Buffer Size Reduction Approach for 3-D-NoC	1
Texas A&M Hackin’ Aggies’ Security Verification Strategies for the 2019 Hack@DAC Competition	1
Silicon-Proven Timing Signoff Methodology Using Hazard-Free Robust Path Delay Tests	1
SeMAP—A Method to Secure the Communication in NoC-Based Many-Cores	1
A Deep Transfer Learning Design Rule Checker With Synthetic Training	1
Securing CRYSTALS-Kyber in FPGA Using Duplication and Clock Randomization	1
Holding Conferences Online due to COVID-19: The DATE Experience	1
Strange Loops in Design and Technology: 59th DAC Keynote Speech	1
Ethical Design of Computers: From Semiconductors to IoT and Artificial Intelligence	1

Randomized Testing of RISC-V CPUs Using Direct Instruction Injection	1
End-to-End Automated Exploit Generation for Processor Security Validation	1
A Reinforcement Learning Framework With Region-Awareness and Shared Path Experience for Efficient Routing in Networks-on-Chip	1
HPC-Based Malware Detectors Actually Work: Transition to Practice After a Decade of Research	1
Toward Agile Hardware Designs With Chisel: A Network Use Case	1
Dependable STT-MRAM With Emerging Approximation and Speculation Paradigms	1
JARVA: Joint Application-Aware Oblivious Routing and Static Virtual Channel Allocation	1
Shaping Resilient AI Hardware Through DNN Computational Feature Exploitation	1
Detecting Pediatric Foot Deformities Using Plantar Pressure Measurements: A Semisupervised Approach	1
Optimal Energy Efficiency and Throughput on Partially Reversible Pipelined QCA Circuits	1
FlooNoC: A Multi-Tb/s Wide NoC for Heterogeneous AXI4 Traffic	1
Power-Saving 8K Real-Time AV1 Arithmetic Encoder Architecture	1
Graph-Based Circuit Simulator for Switched Capacitor Circuits	1
Ethics in Sustainability	1
Provably Secure Sequential Obfuscation for IC Metering and Piracy Avoidance	1
Guest Editors’ Introduction: SBCCI 2019	1
A Mixture of Experts Approach for Low-Cost DNN Customization	1
Hardware-Based Fast Hybrid Morphological Reconstruction	1
STLs for GPUs: Using High-Level Language Approaches	1
Determining Mechanical Stress Testing Parameters for FHE Designs with Low Computational Overhead	1
From the EIC: Education for Cyber-Physical Systems	1
A Study on Confidence: An Unsupervised Multiagent Machine Learning Experiment	1
Efficient Privacy-Aware Federated Learning by Elimination of Downstream Redundancy	1
SynFull-RTL: Evaluation Methodology for RTL NoC Designs	1
Parallelizing GPGPU-Sim for Faster Simulation with High Fidelity	1
Adaptive Neural Network Architectures for Power Aware Inference	1
Applying IEEE Test Standards to Multidie Designs	1
Long-Wire Leakage: The Threat of Crosstalk	1
A DVFS Design and Simulation Framework Using Machine Learning Models	1
Affordable and Comprehensive Testing of 3-D Stacked Die Devices	1
A 703.4-GOPs/W Binary SegNet Processor With Computing-Near-Memory Architecture for Road Detection	1
A Global Self-Repair Method for TSV Arrays With Adaptive FNS-CAC Codec	1
Majority-Logic-Based Self-Checking Adder in Quantum-Dot Cellular Automata	1
Mitigating Speculative Execution Attacks via Context-Sensitive Fencing	1
Active and Passive Physical Attacks on Neural Network Accelerators	1
Flexible and Portable Management of Secure Scan Implementations Exploiting P1687.1 Extensions	1
Low-Power High-Throughput Architecture for AV1 Arithmetic Decoder	1
Guest Editors' Introduction: Education for Cyber-Physical Systems	1
Cloud-Ready Acceleration of Formal Method Techniques for Cyber–Physical Systems	1
Traversal Packets: Opportunistic Bypass Packets for Deadlock Recovery	1
2019 DAC Roundtable	0
TTTC Newsletter	0
IEEE Women in Engineering	0
Guest Editors’ Introduction: Special Issue on Top Picks in Hardware and Embedded Security	0
IEEE Foundation	0
Report on the 2021 Embedded Systems Week (ESWEEK)	0
DRAM PUFs in Commodity Devices	0
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Report on the 28th Asia and South Pacific Design Automation Conference	0
Special Issue on Testability and Dependability of Artificial Intelligence Hardware	0
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Reconfigurable Pipelined Control Systems	0
A NoC-Based Spatial DNN Inference Accelerator With Memory-Friendly Dataflow	0
TTTC Newsletter	0
SPOCK: Reverse Packet Traversal for Deadlock Recovery	0
Adaptive Integer Linear Programming Model for Optimal Qubit Permutation	0
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Losing My Memory	0
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The 2021 Asia and South Pacific Design Automation Conference (ASPDAC)	0
TechRxiv: Share Your Preprint Research with the World!	0
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ISLPED 2021: The 25th Anniversary!	0
Detecting and Scoring Equipment Faults in Real Time During Semiconductor Test Processes	0
Side Channel and Fault Analyses on Memristor-Based Logic In-Memory	0
Special Issue on Ethics in Computing	0
40th IEEE VLSI Test Symposium 2022	0
The 41st IEEE VLSI Test Symposium	0
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PiN: Processing in Network-on-Chip	0
IEEE Women in Engineering	0
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ISLPED 2020: An Experience of Virtual Conference during COVID-19 Time	0
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Being Learned	0
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ISLPED 2022: An Experience of a Hybrid Conference in the Time of COVID-19	0
Product Health Insights Using Telemetry	0
Scan Integrity Tests for EDT Compression	0
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Fast Analysis Using Finite Queuing Model for Multilayer NoCs	0
The 2020 Embedded Systems Week (ESWEEK): A Virtual Event During a Pandemic	0
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