IEEE Design & Test

Article	Citations
A Survey of Neuromorphic Computing-in-Memory: Architectures, Simulators, and Security	39
ALIGN: A System for Automating Analog Layout	32
MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII	31
Analog-to-Digital Converter Design Exploration for Compute-in-Memory Accelerators	29
Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs	28
An Inside Job: Remote Power Analysis Attacks on FPGAs	28
Testability and Dependability of AI Hardware: Survey, Trends, Challenges, and Perspectives	25
A Survey on Machine Learning Accelerators and Evolutionary Hardware Platforms	24
Enabling Design Methodologies and Future Trends for Edge AI: Specialization and Codesign	23
Secure Interposer-Based Heterogeneous Integration	21
From Less Batteries to Battery-Less Alert Systems with Wide Power Adaptation down to nWs—Toward a Smarter, Greener World	21
Spectre Returns! Speculation Attacks Using the Return Stack Buffer	19
Fair and Comprehensive Benchmarking of Machine Learning Processing Chips	18
Survey on Education for Cyber-Physical Systems	17
Three-Input NPN Class Gate Library for Atomic Silicon Quantum Dots	15
Real Silicon Using Open-Source EDA	14
Automatic Detection of Respiratory Symptoms Using a Low-Power Multi-Input CNN Processor	14
EM Side Channels in Hardware Security: Attacks and Defenses	13
Discovering CAN Specification Using On-Board Diagnostics	13
FPGA-Chain: Enabling Holistic Protection of FPGA Supply Chain With Blockchain Technology	13
SIT: Stochastic Input Transformation to Defend Against Adversarial Attacks on Deep Neural Networks	13
A Cautionary Tale About Detecting Malware Using Hardware Performance Counters and Machine Learning	12
Verification Approaches for Learning-Enabled Autonomous Cyber–Physical Systems	11
An Energy-Aware Nanoscale Design of Reversible Atomic Silicon Based on Miller Algorithm	11
An Open-Source EDA Flow for Asynchronous Logic	11

Fault: Open-Source EDA’s Missing DFT Toolchain	11
Machine Learning for CAD/EDA: The Road Ahead	11
EdgeAl: A Vision for Deep Learning in the IoT Era	10
OpenTimer v2: A Parallel Incremental Timing Analysis Engine	10
Merged Logic and Memory Fabrics for Accelerating Machine Learning Workloads	10
Exact Stochastic Computing Multiplication in Memristive Memory	10
Cyber-Physical Systems Security Education Through Hands-on Lab Exercises	10
EM/Power Side-Channel Attack: White-Box Modeling and Signature Attenuation Countermeasures	9
The Role of Competence Networks in the Era of Cyber-Physical Systems — Promoting Knowledge Sharing and Knowledge Exchange	9
Introducing IoT Subjects to an Existing Curriculum	9
Breaking Silos to Guarantee Control Stability with Communication over Ethernet TSN	9
Design Challenges of Intrachiplet and Interchiplet Interconnection	8
Ladder Scaling Fracmemristor: A Second Emerging Circuit Structure of Fractional-Order Memristor	8
FaCT-LSTM: Fast and Compact Ternary Architecture for LSTM Recurrent Neural Networks	8
On Backside Probing Techniques and Their Emerging Security Threats	8
Machine Learning in Advanced IC Design: A Methodological Survey	8
Fault-Tolerant Neural Network Accelerators With Selective TMR	8
Enabling Security of Heterogeneous Integration: From Supply Chain to In-Field Operations	7
Improving DNN Hardware Accuracy by In-Memory Computing Noise Injection	7
Furthering Moore’s Law Integration Benefits in the Chiplet Era	7
In-Stream Correlation-Based Division and Bit-Inserting Square Root in Stochastic Computing	7
EDLAB: A Benchmark for Edge Deep Learning Accelerators	7
Hardware Virtualization and Task Allocation for Plug-and-Play Automotive Systems	7
Project-Based CPS Education: A Case Study of an Autonomous Driving Student Project	7
Cross-Layer Design of Automotive Systems	7
Computing-In-Memory Using Ferroelectrics: From Single- to Multi-Input Logic	7
Eavesdropping Attack Detection Using Machine Learning in Network-on-Chip Architectures	6
Hardware Accelerators for Digital Signature Algorithms Dilithium and FALCON	6
Machine Learning and Algorithms: Let Us Team Up for EDA	6
HPC-Based Malware Detectors Actually Work: Transition to Practice After a Decade of Research	6
Efficient SoC Security Monitoring: Quality Attributes and Potential Solutions	6
A Hardware Accelerator for Language-Guided Reinforcement Learning	6
Split-Chip Design to Prevent IP Reverse Engineering	6
On the Mitigation of Read Disturbances in Neuromorphic Inference Hardware	6
A Novel Method for Scalable VLSI Implementation of Hyperbolic Tangent Function	6
Defeating Cache Timing Channels with Hardware Prefetchers	6
The AXIOM Project: IoT on Heterogeneous Embedded Platforms	6
SCA Strikes Back: Reverse-Engineering Neural Network Architectures Using Side Channels	6
EDA and Quantum Computing: a symbiotic relationship?	5
Hardware Penetration Testing Knocks Your SoCs Off	5
Framework for Load Power Consumption in HANs Using Machine Learning and IoT Assistance	5
A Conceptual Framework for Stochastic Neuromorphic Computing	5
Design and Test of Crab-Shaped Negative Group Delay Circuit	5
Estimating Code Vulnerability to Timing Errors Via Microarchitecture-Aware Machine Learning	5
Topology-Aided Multicorner Timing Predictor for Wide Voltage Design	4
A Programmable Open Architecture Testbed for CPS Education	4
The Emerging Majority: Technology and Design for Superconducting Electronics	4
Multisensing System for Parkinson’s Disease Stage Assessment Based on FPGA-Embedded Serial SVM Classifier	4
PyH2: Using PyMTL3 to Create Productive and Open-Source Hardware Testing Methodologies	4
Ethical Design of Computers: From Semiconductors to IoT and Artificial Intelligence	4

Future Engineering Curricula: Balancing Domain Competence with CPS Readiness	4
The Future of Design for Test and Silicon Lifecycle Management	4
Guest Editors’ Introduction: Stochastic Computing for Neuromorphic Applications	4
Autonomous Systems Design: Charting a New Discipline	4
Embracing Stochasticity to Enable Neuromorphic Computing at the Edge	4
Flexible and Scalable BLAKE/BLAKE2 Coprocessor for Blockchain-Based IoT Applications	4
Security Vulnerabilities and Countermeasures in MPSoCs	4
Securing CRYSTALS-Kyber in FPGA Using Duplication and Clock Randomization	4
Creating a Foundation for Next-Generation Autonomous Systems	4
Real-time Hardware Implementation of ARM CoreSight Trace Decoder	4
BHT-NoC: Blaming Hardware Trojans in NoC Routers	4
Design of Single-Bit Fault-Tolerant Reversible Circuits	4
High-Performance Deterministic Stochastic Computing Using Residue Number System	4
Electronic, Wireless, and Photonic Network-on-Chip Security: Challenges and Countermeasures	4
An Area- and Power-Efficient Stochastic Number Generator for Bayesian Sensor Fusion Circuits	4
Broadcast-TDMA: A Cost-Effective Fault-Tolerance Method for TSV Lifetime Reliability Enhancement	4
Remote Fault Attacks in Multitenant Cloud FPGAs	4
Using STLs for Effective In-Field Test of GPUs	4
Deadlock-Freedom in Computational Neuroscience Simulators	4
Hunting Security Bugs in SoC Designs: Lessons Learned	3
Reverse-Engineering CNN Models Using Side-Channel Attacks	3
Bandpass NGD Time- Domain Experimental Test of Double-Li Microstrip Circuit	3
Deep Reinforcement Learning for Optimization at Early Design Stages	3
RosettaStone: Connecting the Past, Present, and Future of Physical Design Research	3
Executing Data Integration Effectively and Efficiently Near the Memory	3
An Attachable Battery–Supercapacitor Hybrid for Large Pulsed Load	3
SeMAP—A Method to Secure the Communication in NoC-Based Many-Cores	3
Design and Test of Innovative Three-Couplers-Based Bandpass Negative Group Delay Active Circuit	3
On the Implementation of Fixed-Point Exponential Function for Machine Learning and Signal- Processing Accelerators	3
SoC Security Evaluation: Reflections on Methodology and Tooling	3
Integrating Interobject Scenarios with Intraobject Statecharts for Developing Reactive Systems	3
Runtime Protection of Real-time Critical Control Applications against Known Threats	3
A NoC-Based Spatial DNN Inference Accelerator With Memory-Friendly Dataflow	3
Shape Engineering for Custom Nanomagnetic Logic Circuits in NMLSim 2.0	3
Recycling Test Methods to Improve Test Capacity and Increase Chip Shipments	3
Detecting Pediatric Foot Deformities Using Plantar Pressure Measurements: A Semisupervised Approach	2
Dynamically Reconfigurable Network Protocol for Shape-Changeable Computer System	2
Low-Cost Structural Monitoring of Analog Circuits for Secure and Reliable Operation	2
Area-Efficient LFSR-Based Stochastic Number Generators With Minimum Correlation	2
A Systematic Design Methodology of Formally Proven Side-Channel-Resistant Cryptographic Hardware	2
Datapath Extension of NPUs to Support Nonconvolutional Layers Efficiently	2
Autonomous Systems, Trust, and Guarantees	2
Tipping the Balance: Imbalanced Classes in Deep-Learning Side-Channel Analysis	2
On the Impact of Uncertainties in Silicon-Photonic Neural Networks	2
PiN: Processing in Network-on-Chip	2
Power-Quality Configurable Hardware Design for AV1 Directional Intraframe Prediction	2
Real-Time Requirements for ADAS Platforms Featuring Shared Memory Hierarchies	2
Fault-Tolerant Neuromorphic Computing With Memristors Using Functional ATPG for Efficient Recalibration	2
Efficient Privacy-Aware Federated Learning by Elimination of Downstream Redundancy	2
Cloud-Ready Acceleration of Formal Method Techniques for Cyber–Physical Systems	2
Long-Wire Leakage: The Threat of Crosstalk	2
End-to-End Automated Exploit Generation for Processor Security Validation	2
A Global Self-Repair Method for TSV Arrays With Adaptive FNS-CAC Codec	2
Training Binarized Neural Networks Using Ternary Multipliers	2
Self-Healing of Redundant FLASH ADCs	2
Texas A&M Hackin’ Aggies’ Security Verification Strategies for the 2019 Hack@DAC Competition	2
A Many-Ported and Shared Memory Architecture for High-Performance ADAS SoCs	2
Lifelong Exploratory Navigation: An Architecture for Safer Mobile Robots	2
Impact of Orientation on the Bias of SRAM-Based PUFs	2
Design of ₌׀₌ Shape Stub-Based Negative Group Delay Circuit	2
API-Based Hardware Fault Simulation for DNN Accelerators	2
Statistical Methods for Detecting Recycled Electronics: From ICs to PCBs and Beyond	2
Safety Ethics for Design and Test of Automated Driving Features	2
Automated Probe-Mark Analysis for Advanced Probe Technology Characterization	2
Dependable STT-MRAM With Emerging Approximation and Speculation Paradigms	1
JARVA: Joint Application-Aware Oblivious Routing and Static Virtual Channel Allocation	1
Similarity-Based Fast Analysis of Data Center Networks	1
A Study on Confidence: An Unsupervised Multiagent Machine Learning Experiment	1
SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs	1
Graph-Based Circuit Simulator for Switched Capacitor Circuits	1
Applying IEEE Test Standards to Multidie Designs	1
Report on the 2022 Embedded Systems Week (ESWEEK)	1
Power-Saving 8K Real-Time AV1 Arithmetic Encoder Architecture	1
A Highly Robust and Low-Power Flip-Flop Cell With Complete Double-Node-Upset Tolerance for Aerospace Applications	1
Mitigating Speculative Execution Attacks via Context-Sensitive Fencing	1
Active and Passive Physical Attacks on Neural Network Accelerators	1
STLs for GPUs: Using High-Level Language Approaches	1
A DVFS Design and Simulation Framework Using Machine Learning Models	1
Toward Agile Hardware Designs With Chisel: A Network Use Case	1
A 703.4-GOPs/W Binary SegNet Processor With Computing-Near-Memory Architecture for Road Detection	1

Guest Editors' Introduction: Education for Cyber-Physical Systems	1
FALCON: An FPGA Emulation Platform for Domain-Specific SoCs (DSSoCs)	1
RB-OLITS: A Worst Case Reorder Buffer Size Reduction Approach for 3-D-NoC	1
SynFull-RTL: Evaluation Methodology for RTL NoC Designs	1
Guest Editors’ Introduction: SBCCI 2019	1
Heuristic-Based Algorithms for Low-Complexity AV1 Intraprediction	1
Special Issue on Testability and Dependability of Artificial Intelligence Hardware	1
Affordable and Comprehensive Testing of 3-D Stacked Die Devices	1
Enabling High-Level Design Strategies for High-Throughput and Low-Power NB-LDPC Decoders	1
Provably Secure Sequential Obfuscation for IC Metering and Piracy Avoidance	1
Seamless Thermal Optimization of Parallel Workloads	1
Improvement of Functional Safety of the Level-Crossing Barrier Machine by a Noninvasive Angle-Detection Method	1
Fast Analysis Using Finite Queuing Model for Multilayer NoCs	1
Flexible and Portable Management of Secure Scan Implementations Exploiting P1687.1 Extensions	1
Workload-Aware Periodic Interconnect BIST	1
A Reinforcement Learning Framework With Region-Awareness and Shared Path Experience for Efficient Routing in Networks-on-Chip	1
Side Channel and Fault Analyses on Memristor-Based Logic In-Memory	1
Guest Editors’ Introduction: Special Issue on 2021 Top Picks in Hardware and Embedded Security	1
VioNet: A Hierarchical Detailed Routing Wire-Short Violation Predictor Based on a Convolutional Neural Network	1
Shaping Resilient AI Hardware Through DNN Computational Feature Exploitation	1
Traversal Packets: Opportunistic Bypass Packets for Deadlock Recovery	1
Majority-Logic-Based Self-Checking Adder in Quantum-Dot Cellular Automata	1
Beyond the CPU: Side–Channel Attacks on GPUs	1
Building an Open-Source DNA Assembler Device	1
Strange Loops in Design and Technology: 59th DAC Keynote Speech	1
A Deep Transfer Learning Design Rule Checker With Synthetic Training	1
FlooNoC: A Multi-Tb/s Wide NoC for Heterogeneous AXI4 Traffic	1
Randomized Testing of RISC-V CPUs Using Direct Instruction Injection	1
A Mixture of Experts Approach for Low-Cost DNN Customization	1
Product Health Insights Using Telemetry	1
Low-Power High-Throughput Architecture for AV1 Arithmetic Decoder	1
Ethics in Sustainability	1
From the EIC: Education for Cyber-Physical Systems	1
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SPOCK: Reverse Packet Traversal for Deadlock Recovery	0
Guest Editors’ Introduction: Competing to Secure SoCs	0
ISLPED 2020: An Experience of Virtual Conference during COVID-19 Time	0
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Report on the 2021 Embedded Systems Week (ESWEEK)	0
ISLPED 2022: An Experience of a Hybrid Conference in the Time of COVID-19	0
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Conference Report From The 57th Design Automation Conference	0
Reconfigurable Pipelined Control Systems	0
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Fully Microstrip Three-Port Circuit Bandpass NGD Design and Test	0
Adaptive Integer Linear Programming Model for Optimal Qubit Permutation	0
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Losing My Memory	0
Special Issue on Postquantum Cryptography for Internet of Things	0
Attack of the AI Papers	0
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TechRxiv: Share Your Preprint Research with the World!	0
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DRAM PUFs in Commodity Devices	0
ISLPED 2021: The 25th Anniversary!	0
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Background Receiver IQ Imbalance Correction for In-Field Testing	0
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IEEE Design&Test EIC Call for Nominations	0
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