IEEE Design & Test

Papers
(The median citation count of IEEE Design & Test is 0. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-08-01 to 2026-08-01.)
ArticleCitations
IEEE Foundation78
Top Picks in Hardware and Embedded Security 202240
Special Issue on the 2023 Symposium on Integrated Circuits and Systems Design32
On Backside Probing Techniques and Their Emerging Security Threats31
Celebrating 20 Years of EDA: Milestones, Challenges, and Future Directions29
SPOCK: Reverse Packet Traversal for Deadlock Recovery26
Special Issue on Emerging Challenges With 3-D NAND Flash Storage23
BHT-NoC: Blaming Hardware Trojans in NoC Routers22
An Energy-Aware Nanoscale Design of Reversible Atomic Silicon Based on Miller Algorithm22
Improvement of Functional Safety of the Level-Crossing Barrier Machine by a Noninvasive Angle-Detection Method21
Tipping the Balance: Imbalanced Classes in Deep-Learning Side-Channel Analysis19
Report on the 28th Asia and South Pacific Design Automation Conference18
IEEE Connects You to a Universe of Information!15
Statistical Methods for Detecting Recycled Electronics: From ICs to PCBs and Beyond15
Front Cover14
Celebrating Three Decades of IEEE/ACM International Symposium on Low Power Electronics and Design13
On the Impact of Uncertainties in Silicon-Photonic Neural Networks12
An Open-Source 12-bit 10-kS/s Incremental ADC in 130-nm CMOS12
ISCA: Intelligent Sense-Compute Adaptive Co-Optimization of Multimodal Machine Learning Kernels for Resilient mHealth Services on Wearables12
The 2022 International Conference on Computer-Aided Design (ICCAD)11
Special Issue on Wearable IoT Devices for Reliable Mobile Health Applications11
IC Phone Home!11
IEEE App11
IEEE Design & Test Publication Information11
The Ultimate Source of Knowledge11
FlooNoC: A Multi-Tb/s Wide NoC for Heterogeneous AXI4 Traffic11
Datapath Extension of NPUs to Support Nonconvolutional Layers Efficiently10
Soft and Hard Error-Correction Techniques in STT-MRAM10
Blank Page10
edAttack: Hardware Trojan Attack on On-Chip Packet Compression10
IEEE Design & Test Publication Information10
Get in the Conversation!9
Hardware/Software Coexploration for Hyperdimensional Computing on Network-on-Chip Architecture9
Eavesdropping Attack Detection Using Machine Learning in Network-on-Chip Architectures9
Special Issue on the 2021 Workshop on Top Picks in Hardware and Embedded Security8
IEEE Foundation8
Remembering Arvind7
SoC-GPIO-Based Dynamic Power Noise Control for Video Sensor Applications7
Table of Contents7
FPGA-Chain: Enabling Holistic Protection of FPGA Supply Chain With Blockchain Technology7
CLEAR Cross-Layer Resilience: A Retrospective7
IEEE Design & Test Publication Information7
IEEE App7
Evaluating 3-D Flash Memory Retention Reliability Under Temperature Elevation7
Fault-Tolerant Neuromorphic Computing With Memristors Using Functional ATPG for Efficient Recalibration6
CaSA: End-to-End Quantitative Security Analysis of Randomly Mapped Caches6
Special Issue on TinyML6
Voltage–Resistance-Adaptive MPPT Circuit for Energy Harvesting6
BiomedBench: A Benchmark Suite of TinyML Biomedical Applications for Low-Power Wearables6
Special Issue on Approximate Computing: Challenges, Methodologies, Algorithms, and Architectures for Dependable and Secure Systems6
Dynamically Reconfigurable Network Protocol for Shape-Changeable Computer System6
Traversal Packets: Opportunistic Bypass Packets for Deadlock Recovery6
On the Relation Between Reliability and Entropy in Physical Unclonable Functions6
IEEE Design & Test Publication Information6
Get in the Conversation!6
Physical Design for Heterogeneous Integration: Challenges and Opportunities5
Power and Performance Scaling Trends in Modern Intel Xeon Server CPUs5
Recap of the 62nd ACM/IEEE Design Automation Conference (DAC62): The “Chips to Systems Conference”5
IEEE Membership5
Robust and Secure Systems5
Binary Forward-Only Algorithms5
Attack of the AI Papers5
Estimating Code Vulnerability to Timing Errors Via Microarchitecture-Aware Machine Learning5
Table of Contents5
Configuration-Driven RTL Port Initialization with LLM-Assisted Inference5
20 Years of IEEE CEDA and More of EDA5
IEEE Design & Test Publication Information5
TechRxiv5
A Brief 20-Year History and Future Perspectives on Sizing and Layout Synthesis of Analog/RF ICs5
Circuits to Systems: Codesigning Efficient AI Hardware5
A Tutorial on Secure and Efficient Firmware Delivery5
Tutorial on Power Side-Channel Attacks on Embedded Systems5
Front Cover5
Special Issue Dedicated to the 2024 Symposium on Integrated Circuits and Systems Design (SBCCI)5
Front Cover4
ISLPED 2023: International Symposium on Low-Power Electronics and Design4
Edge AI—An Industry View4
IEEE Membership4
Novel Technique for Manufacturing, System-Level, and In-System Testing of Large SoC Using Functional Protocol-Based High-Speed I/O4
Table of Contents4
A BIST Approach to Approximate Co-Testing of Embedded Data Converters4
A Global Self-Repair Method for TSV Arrays With Adaptive FNS-CAC Codec4
Special Issue on Design and Test of Multidie Packages4
The 28th IEEE European Test Symposium4
Recap of the 61st ACM/IEEE Design Automation Conference (DAC61): The “Chips to Systems Conference”4
Functional Verification of a RISC-V Vector Accelerator4
IEEE Connects You to a Universe of Information!4
Residual Structural Traces in Logic Locking: Insights From Redundancy Analysis and Beyond3
Using STLs for Effective In-Field Test of GPUs3
Testing for Electromigration in Sub-5-nm FinFET Memories3
Special Issue on the 2023 International Symposium on Networks-on-Chip (NOCS 2023)3
SAFER: Safety Assurances for Emergent Behavior3
Report on the 2025 Embedded Systems Week (ESWEEK)3
Special Issue on Top Picks in Test and Reliability3
Table of Contents3
The Future of Design for Test and Silicon Lifecycle Management3
IEEE Design & Test Publication Information3
Strange Loops in Design and Technology: 59th DAC Keynote Speech3
Special Issue on Emerging Challenges With 3-D NAND Flash Storage3
Front Cover3
EAVREF: An Evolutionary-Algorithm-Based Tool for Low-Power CMOS Voltage Reference Designs3
Long-Wire Leakage: The Threat of Crosstalk3
IEEE Design & Test Publication Information3
Table of Contents3
CAFEEN: A Cooperative Approach for Energy-Efficient NoCs With Multiagent Reinforcement Learning3
Seamless Thermal Optimization of Parallel Workloads3
Heuristic-Based Algorithms for Low-Complexity AV1 Intraprediction3
IEEE Membership3
Learning Your Lock: Exploiting Structural Vulnerabilities in Logic Locking3
SeMAP—A Method to Secure the Communication in NoC-Based Many-Cores3
Table of Contents3
GlucoseHD: Predicting Glucose Levels Using Hyperdimensional Computing2
Recap of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED’24)2
SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs2
Safe from Prying Eyes2
IEEE Membership2
Analysis and Mitigation of DRAM Faults in Sparse-DNN Accelerators2
Front Cover2
Postquantum Cryptography for Internet of Things2
IEEE App2
Special Issue on NOCS 20222
Virtualizing USB Kernel Mode Debug (KMD) Class to Guest OS for Native OS-Like Debug Experience2
Rethinking SoC Verification for Secure Cross-Layer Interactions2
Majority-Logic-Based Self-Checking Adder in Quantum-Dot Cellular Automata2
This Stuff Is Great—Am I Right?2
Building an Open-Source DNA Assembler Device2
An EMG Denoising Method Based on Flexible Wearable Sensors2
3-D Ferroelectric NAND In-Storage Processing Architecture for Mass Spectrometry2
Special Issue on Wearable IoT Devices for Reliable Mobile Health Applications2
IEEE Foundation2
Silicon Lifecycle Management (SLM): Requirements, Trends, and Opportunities2
Leveraging RISC-V for HW/SW Codesign of Flexible and Efficient TinyML SoCs2
SBCCI 20222
Ethical Design of Computers: From Semiconductors to IoT and Artificial Intelligence2
Shaping Resilient AI Hardware Through DNN Computational Feature Exploitation2
VioNet: A Hierarchical Detailed Routing Wire-Short Violation Predictor Based on a Convolutional Neural Network2
IEEE Design & Test Publication Information2
Front Cover2
Guest Editors’ Introduction: SBCCI 20232
Is There an Answer?2
IEEE App1
IEEE App1
IEEE Membership1
Table of Contents1
Get in the Conversation!1
IEEE Design & Test Publication Information1
ASP-DAC 2026: Strengthening Asia’s Expanding Role in Design Automation Research1
Deadlock-Freedom in Computational Neuroscience Simulators1
IEEE App1
ISLPED 2022: An Experience of a Hybrid Conference in the Time of COVID-191
Background Receiver IQ Imbalance Correction for In-Field Testing1
A Growing and Thriving Electronic Design, Automation, and Test Community: A DATE 2025 Perspective1
Impact of Partial TMR on RISC-V Processor Reliability1
Report on the 2024 Embedded Systems Week (ESWEEK)1
ICCAD 2025: First Time Outside the United States and a Record-Breaking Edition1
Machine Learning in Advanced IC Design: A Methodological Survey1
Special Issue on the First IEEE Top Picks in VLSI Test and Reliability Workshop1
Silent Data Corruption by 10× Test Escapes Threatens Reliable Computing1
IEEE Membership1
Reverse-Engineering CNN Models Using Side-Channel Attacks1
The VCR Effect in Active-RC Continuous-Time Sigma–Delta Modulators1
Table of Contents1
Spectre Returns! Speculation Attacks Using the Return Stack Buffer1
Exploring Asymmetric Autoencoder Architectures for Computationally Efficient Neural Image Compression1
Fully Microstrip Three-Port Circuit Bandpass NGD Design and Test1
A Coding Efficiency-Aware Hardware Design for VVC Affine Motion Estimation Reconstructor1
Table of Contents1
Product Health Insights Using Telemetry1
IEEE Foundation1
IEEE Membership1
Site-to-Site Variation in Analog Multisite Testing: A Survey on Its Detection and Correction1
On the Origin of AI Species1
Furthering Moore’s Law Integration Benefits in the Chiplet Era1
IEEE Connects You to a Universe of Information!1
Analytical Model for Performance Evaluation of Token-Passing-Based WiNoCs1
Special Issue on 20 Years of IEEE CEDA1
Special Issue on the 2024 IEEE Top Picks in VLSI Test and Reliability Workshop1
The 41st IEEE VLSI Test Symposium1
IEEE Design & Test Publication Information1
Machine Learning for CAD/EDA1
40th IEEE VLSI Test Symposium 20221
IEEE Design & Test Publication Information1
Testing of Chiplet-Based Packages Based on Advanced Heterogeneous Integration1
IEEE Membership0
FALCON: An FPGA Emulation Platform for Domain-Specific SoCs (DSSoCs)0
PiN: Processing in Network-on-Chip0
Dependable STT-MRAM With Emerging Approximation and Speculation Paradigms0
Open-Source Multilevel Converter Power IC Design and Test0
ViT-Reg: Regression-Focused Hardware-Aware Fine-Tuning for ViT on TinyML Platforms0
Addressing the Cross-Temperature Issue in 3-D NAND Flash Memories: Characterization and Mitigation for Solid-State Drives0
Interview With Janet Olson0
IEEE Design & Test Publication Information0
Recap of the 29th Edition of the Asia and South Pacific Design Automation Conference (ASPDAC 2024)0
Graph-Based Circuit Simulator for Switched Capacitor Circuits0
Indirect Test Pattern Generation for Mixed-Signal Circuits Using Machine Learning0
STAR: A Mixed Analog Stochastic In-DRAM Convolutional Neural Network Accelerator0
Toward Attention-Based TinyML: A Heterogeneous Accelerated Architecture and Automated Deployment Flow0
Threat Detection in NoC-Based Manycores Using Lightweight Machine-Learning Models0
Table of Contents0
IEEE Design & Test Publication Information0
Front Cover0
SBCCI 20240
HLS Register Allocation Attack for Compromising Hardware IP Designs using HLS-aided Trojan0
Self-Sustainable Wearable and Internet of Things (IoT) Devices for Health Monitoring: Opportunities and Challenges0
Lynn Conway: Two Remembrances0
Low-Power High-Throughput Architecture for AV1 Arithmetic Decoder0
TechRxiv: Share Your Preprint Research With the World!0
Survey of Challenges in Implementation-Security Metrics for Side-Channel and Fault-Injection Attacks0
TechRxiv: Share Your Preprint Research With the World!0
Postpandemic Conferences: The DATE 2023 Experience0
Machine Learning for CAD/EDA: The Road Ahead0
Get in the Conversation!0
A NoC-Based Spatial DNN Inference Accelerator With Memory-Friendly Dataflow0
IEEE Design & Test Publication Information0
Table of Contents0
Front Cover0
Interview With Yao-Wen Chang0
Memory Usage Estimation for Dataflow-Model-Based Software Development Methodology0
Testability and Dependability of AI Hardware: Survey, Trends, Challenges, and Perspectives0
IEEE Design & Test Publication Information0
Front Cover0
Testing for Multiple Faults in Deep Neural Networks0
Remote Power Side- Channel Attacks on FPGAs0
Special Issue on 2021 Top Picks in Hardware and Embedded Security0
Using Approximate Circuits Against Hardware Trojans0
Approximate Computing in Memristive Processing-In-Array (PIA)0
Secure Interposer-Based Heterogeneous Integration0
Tree-Based Unidirectional Neural Networks for Low-Power Computer Vision0
IEEE Membership0
Workload-Aware Periodic Interconnect BIST0
Time-Bomb HLS Trojan for Performance Degradation Payload0
On the Implementation of Fixed-Point Exponential Function for Machine Learning and Signal- Processing Accelerators0
Can Model-Level Fault Tolerance Be Enough for DNN Hardware Accelerators? A Study0
HPC-Based Malware Detectors Actually Work: Transition to Practice After a Decade of Research0
Small Is Good0
Get in the Conversation!0
IEEE Foundation0
Table of Contents0
Efficient Aspect Verification and Debugging of High-Performance Microprocessor Designs0
API-Based Hardware Fault Simulation for DNN Accelerators0
ELEMENT: Energy-Efficient Multi-NoP Architecture for IMC-Based 2.5-D Accelerator for DNN Training0
Affordable and Comprehensive Testing of 3-D Stacked Die Devices0
Front Cover0
Fuzzing for Automated SoC Security Verification: Challenges and Solution0
LATTE: Library Attack for Evaluating Hardware IP Protections Against Reverse Engineering0
Hard-Sign: A Hardware Watermarking Scheme Using Dated Handwritten Signature0
Front Cover0
Design Challenges of Intrachiplet and Interchiplet Interconnection0
Our Gated Community0
Front Cover0
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