IEEE Design & Test

Papers
(The median citation count of IEEE Design & Test is 0. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-01-01 to 2026-01-01.)
ArticleCitations
ISLPED 2021: The 25th Anniversary!64
IEEE Foundation59
Top Picks in Hardware and Embedded Security 202252
Flexible and Portable Management of Secure Scan Implementations Exploiting P1687.1 Extensions40
Celebrating 20 Years of EDA: Milestones, Challenges, and Future Directions35
Special Issue on the 2023 Symposium on Integrated Circuits and Systems Design30
On Backside Probing Techniques and Their Emerging Security Threats27
SPOCK: Reverse Packet Traversal for Deadlock Recovery21
BHT-NoC: Blaming Hardware Trojans in NoC Routers21
An Energy-Aware Nanoscale Design of Reversible Atomic Silicon Based on Miller Algorithm21
Improvement of Functional Safety of the Level-Crossing Barrier Machine by a Noninvasive Angle-Detection Method19
IEEE Connects You to a Universe of Information!18
Report on the 28th Asia and South Pacific Design Automation Conference18
Statistical Methods for Detecting Recycled Electronics: From ICs to PCBs and Beyond18
Tipping the Balance: Imbalanced Classes in Deep-Learning Side-Channel Analysis18
An Open-Source 12-bit 10-kS/s Incremental ADC in 130-nm CMOS17
On the Impact of Uncertainties in Silicon-Photonic Neural Networks17
Front Cover17
ISCA: Intelligent Sense-Compute Adaptive Co-Optimization of Multimodal Machine Learning Kernels for Resilient mHealth Services on Wearables16
IC Phone Home!15
The 2022 International Conference on Computer-Aided Design (ICCAD)15
edAttack: Hardware Trojan Attack on On-Chip Packet Compression14
Soft and Hard Error-Correction Techniques in STT-MRAM13
Special Issue on Wearable IoT Devices for Reliable Mobile Health Applications13
FlooNoC: A Multi-Tb/s Wide NoC for Heterogeneous AXI4 Traffic12
Blank Page10
IEEE Design & Test Publication Information10
IEEE Design&Test Publication Information10
Table of Contents10
Eavesdropping Attack Detection Using Machine Learning in Network-on-Chip Architectures9
Datapath Extension of NPUs to Support Nonconvolutional Layers Efficiently9
Get in the Conversation!9
The Memory Shuffle9
Hardware/Software Coexploration for Hyperdimensional Computing on Network-on-Chip Architecture9
Special Issue on the 2021 Workshop on Top Picks in Hardware and Embedded Security8
TTTC News8
IEEE Design & Test Publication Information8
Fault-Tolerant Neuromorphic Computing With Memristors Using Functional ATPG for Efficient Recalibration8
Table of Contents8
A Survey on Machine Learning Accelerators and Evolutionary Hardware Platforms7
Verification Approaches for Learning-Enabled Autonomous Cyber–Physical Systems7
Remembering Arvind7
On the Relation Between Reliability and Entropy in Physical Unclonable Functions7
Analog-to-Digital Converter Design Exploration for Compute-in-Memory Accelerators7
CLEAR Cross-Layer Resilience: A Retrospective7
BiomedBench: A Benchmark Suite of TinyML Biomedical Applications for Low-Power Wearables7
SOC-GPIO-Based Dynamic Power Noise Control for Video Sensor Applications7
IEEE Design & Test Publication Information6
Special Issue on Approximate Computing: Challenges, Methodologies, Algorithms, and Architectures for Dependable and Secure Systems6
Power-Quality Configurable Hardware Design for AV1 Directional Intraframe Prediction6
Voltage–Resistance-Adaptive MPPT Circuit for Energy Harvesting6
Dynamically Reconfigurable Network Protocol for Shape-Changeable Computer System6
FPGA-Chain: Enabling Holistic Protection of FPGA Supply Chain With Blockchain Technology6
Traversal Packets: Opportunistic Bypass Packets for Deadlock Recovery6
Special Issue on TinyML6
CaSA: End-to-End Quantitative Security Analysis of Randomly Mapped Caches6
Accuracy-Configurable 2-D Gaussian Filter Architecture for Energy-Efficient Image Processing6
Get in the Conversation!5
Attack of the AI Papers5
Front Cover5
Physical Design for Heterogeneous Integration: Challenges and Opportunities5
IEEE Membership5
Robust and Secure Systems5
Binary Forward-Only Algorithms5
A Brief 20-Year History and Future Perspectives on Sizing and Layout Synthesis of Analog/RF ICs5
20 Years of IEEE CEDA and More of EDA5
Table of Contents5
Computing-In-Memory Using Ferroelectrics: From Single- to Multi-Input Logic5
IEEE Design & Test Publication Information5
Estimating Code Vulnerability to Timing Errors Via Microarchitecture-Aware Machine Learning4
ISLPED 2023: International Symposium on Low-Power Electronics and Design4
IEEE Membership4
IEEE Connects You to a Universe of Information!4
Novel Technique for Manufacturing, System-Level, and In-System Testing of Large SoC Using Functional Protocol-Based High-Speed I/O4
Design for Test With Unreliable Memories by Restoring the Beauty of Randomness4
Circuits to Systems: Codesigning Efficient AI Hardware4
Recap of the 61st ACM/IEEE Design Automation Conference (DAC61): The “Chips to Systems Conference”4
CAFEEN: A Cooperative Approach for Energy-Efficient NoCs With Multiagent Reinforcement Learning4
A Global Self-Repair Method for TSV Arrays With Adaptive FNS-CAC Codec4
Recap of the 62nd ACM/IEEE Design Automation Conference (DAC62): The “Chips to Systems Conference”4
The 28th IEEE European Test Symposium4
Guest Editors’ Introduction: SBCCI 20204
Front Cover4
Functional Verification of a RISC-V Vector Accelerator4
Table of Contents4
Special Issue on Design and Test of Multidie Packages4
Seamless Thermal Optimization of Parallel Workloads3
Special Issue on the 2023 International Symposium on Networks-on-Chip (NOCS 2023)3
Table of Contents3
The Future of Design for Test and Silicon Lifecycle Management3
Special Issue on Top Picks in Test and Reliability3
EAVREF: An Evolutionary Algorithm Based Tool for Low-Power CMOS Voltage Reference Designs3
Long-Wire Leakage: The Threat of Crosstalk3
SeMAP—A Method to Secure the Communication in NoC-Based Many-Cores3
Table of Contents3
Table of Contents3
Edge AI—An Industry View3
SAFER: Safety Assurances for Emergent Behavior3
Using STLs for Effective In-Field Test of GPUs3
Strange Loops in Design and Technology: 59th DAC Keynote Speech3
Testing for Electromigration in Sub-5-nm FinFET Memories3
Front Cover3
IEEE Design & Test Publication Information3
Table of Contents3
A BIST Approach to Approximate Co-Testing of Embedded Data Converters3
Learning Your Lock: Exploiting Structural Vulnerabilities in Logic Locking3
IEEE Design & Test Publication Information3
Heuristic-Based Algorithms for Low-Complexity AV1 Intraprediction3
Is There an Answer?2
Machine Learning in Advanced IC Design: A Methodological Survey2
VioNet: A Hierarchical Detailed Routing Wire-Short Violation Predictor Based on a Convolutional Neural Network2
An EMG Denoising Method Based on Flexible Wearable Sensors2
A Case for PIM Support in General-Purpose Compilers2
Guest Editors’ Introduction: SBCCI 20232
SBCCI 20222
Silicon Lifecycle Management (SLM): Requirements, Trends, and Opportunities2
Rethinking SoC Verification for Secure Cross-Layer Interactions2
Ethical Design of Computers: From Semiconductors to IoT and Artificial Intelligence2
Leveraging RISC-V for HW/SW Codesign of Flexible and Efficient TinyML SoCs2
3D Ferroelectric NAND In-Storage Processing Architecture for Mass Spectrometry2
Site-to-Site Variation in Analog Multisite Testing: A Survey on Its Detection and Correction2
Special Issue on the First IEEE Top Picks in VLSI Test and Reliability Workshop2
TTTC News2
IEEE App2
Real-Time Requirements for ADAS Platforms Featuring Shared Memory Hierarchies2
IEEE Design & Test Publication Information2
Special Issue on NOCS 20222
Shaping Resilient AI Hardware Through DNN Computational Feature Exploitation2
SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs2
Virtualizing USB Kernel Mode Debug (KMD) Class to Guest OS for Native OS-Like Debug Experience2
Building an Open-Source DNA Assembler Device2
IEEE Membership2
Special Issue on Near-Memory and In-Memory Processing2
Analysis and Mitigation of DRAM Faults in Sparse-DNN Accelerators2
Front Cover2
Special Issue on Wearable IoT Devices for Reliable Mobile Health Applications2
Postquantum Cryptography for Internet of Things2
GlucoseHD: Predicting Glucose Levels Using Hyperdimensional Computing2
Recap of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED’24)2
Majority-Logic-Based Self-Checking Adder in Quantum-Dot Cellular Automata2
This Stuff Is Great—Am I Right?2
Full Key Extraction of SNOW-V Using ML-Assisted Power SCA1
Crypto-DSEDA: A Domain-Specific EDA Flow for CiM-Based Cryptographic Accelerators1
IEEE Membership1
Bandpass NGD Time- Domain Experimental Test of Double-Li Microstrip Circuit1
Special Issue on 20 Years of IEEE CEDA1
Exploring Asymmetric Autoencoder Architectures for Computationally-Efficient Neural Image Compression1
Reverse-Engineering CNN Models Using Side-Channel Attacks1
Background Receiver IQ Imbalance Correction for In-Field Testing1
Front Cover1
A Coding Efficiency-Aware Hardware Design for VVC Affine Motion Estimation Reconstructor1
Get in the Conversation!1
25 Years (and a Bit More) of The Last Byte1
Furthering Moore’s Law Integration Benefits in the Chiplet Era1
Table of Contents1
IEEE Connects You to a Universe of Information!1
Special Issue on Benchmarking Machine Learning Systems and Applications1
Autonomous Systems, Trust, and Guarantees1
Deadlock-Freedom in Computational Neuroscience Simulators1
Product Health Insights Using Telemetry1
The VCR Effect in Active-RC Continuous-Time Sigma-Delta Modulators1
Table of Contents1
Report on the 2021 Embedded Systems Week (ESWEEK)1
IEEE Design & Test Publication Information1
Impact of Partial TMR on RISC-V Processor Reliability1
IEEE Design & Test Publication Information1
Machine Learning for CAD/EDA1
The 41st IEEE VLSI Test Symposium1
Quantum-Safe Internet of Things1
IEEE Design & Test Publication Information1
Guest Editors’ Introduction: Special Issue on Autonomous Systems Design1
Analytical Model for Performance Evaluation of Token-Passing-Based WiNoCs1
Spectre Returns! Speculation Attacks Using the Return Stack Buffer1
Silent Data Corruption by 10× Test Escapes Threatens Reliable Computing1
IEEE App1
40th IEEE VLSI Test Symposium 20221
Fair and Comprehensive Benchmarking of Machine Learning Processing Chips1
Report on the 2024 Embedded Systems Week (ESWEEK)1
A Growing and Thriving Electronic Design, Automation, and Test Community: A DATE 2025 Perspective1
Fully Microstrip Three-Port Circuit Bandpass NGD Design and Test1
Table of Contents1
ISLPED 2022: An Experience of a Hybrid Conference in the Time of COVID-191
A Hardware Accelerator for Language-Guided Reinforcement Learning0
Design Challenges of Intrachiplet and Interchiplet Interconnection0
Tree-Based Unidirectional Neural Networks for Low-Power Computer Vision0
A NoC-Based Spatial DNN Inference Accelerator With Memory-Friendly Dataflow0
Erratum to “Ethical Design of Computers: From Semiconductors to IoT and Artificial Intelligence”0
PiN: Processing in Network-on-Chip0
STAR: A Mixed Analog Stochastic In-DRAM Convolutional Neural Network Accelerator0
FALCON: An FPGA Emulation Platform for Domain-Specific SoCs (DSSoCs)0
Recap of the 29th Edition of the Asia and South Pacific Design Automation Conference (ASPDAC 2024)0
Addressing the Cross-Temperature Issue in 3D NAND Flash Memories: Characterization and Mitigation for Solid State Drives0
API-Based Hardware Fault Simulation for DNN Accelerators0
Table of Contents0
Affordable and Comprehensive Testing of 3-D Stacked Die Devices0
Memory Usage Estimation for Dataflow-Model-Based Software Development Methodology0
Testability and Dependability of AI Hardware: Survey, Trends, Challenges, and Perspectives0
Toward Attention-Based TinyML: A Heterogeneous Accelerated Architecture and Automated Deployment Flow0
On the Implementation of Fixed-Point Exponential Function for Machine Learning and Signal- Processing Accelerators0
Remote Power Side- Channel Attacks on FPGAs0
Using Approximate Circuits Against Hardware Trojans0
Front Cover0
Lynn Conway: Two Remembrances0
Secure Interposer-Based Heterogeneous Integration0
Efficient Privacy-Aware Federated Learning by Elimination of Downstream Redundancy0
Front Cover0
Time-Bomb HLS Trojan for Performance Degradation Payload0
IEEE Membership0
Dependable STT-MRAM With Emerging Approximation and Speculation Paradigms0
Machine Learning for CAD/EDA: The Road Ahead0
SIT: Stochastic Input Transformation to Defend Against Adversarial Attacks on Deep Neural Networks0
Linear Algorithmic Checksums for Deep-Neural-Network Error Detection: Fundamentals and Recent Advancements0
IEEE Design & Test Publication Information0
TechRxiv: Share Your Preprint Research With the World!0
Front Cover0
Efficient Aspect Verification and Debugging of High-Performance Microprocessor Designs0
Front Cover0
IEEE Design & Test Publication Information0
ViT-Reg: Regression-Focused Hardware-Aware Fine-Tuning for ViT on TinyML Platforms0
Table of Contents0
Graph-Based Circuit Simulator for Switched Capacitor Circuits0
ELEMENT: Energy-Efficient Multi-NoP Architecture for IMC-Based 2.5-D Accelerator for DNN Training0
IEEE Design & Test Publication Information0
Our Gated Community0
Special Issue on 2021 Top Picks in Hardware and Embedded Security0
Fuzzing for Automated SoC Security Verification: Challenges and Solution0
Hard-Sign: A Hardware Watermarking Scheme Using Dated Handwritten Signature0
IEEE Membership0
Low-Power High-Throughput Architecture for AV1 Arithmetic Decoder0
LATTE: Library Attack for Evaluating Hardware IP Protections Against Reverse Engineering0
TechRxiv: Share Your Preprint Research With the World!0
A 703.4-GOPs/W Binary SegNet Processor With Computing-Near-Memory Architecture for Road Detection0
Open-Source Multilevel Converter Power IC Design and Test0
Interview With Janet Olson0
Migortho: A Design Automation Flow for QCA Circuits0
IEEE Foundation0
Testing for Multiple Faults in Deep Neural Networks0
IEEE Design & Test Publication Information0
IEEE Design & Test Publication Information0
Interview With Yao-Wen Chang0
Indirect Test Pattern Generation for Mixed-Signal Circuits Using Machine Learning0
Threat Detection in NoC-based Manycores using Lightweight Machine Learning Models0
EM Side Channels in Hardware Security: Attacks and Defenses0
Workload-Aware Periodic Interconnect BIST0
Table of Contents0
Front Cover0
Postpandemic Conferences: The DATE 2023 Experience0
Self-Sustainable Wearable and Internet of Things (IoT) Devices for Health Monitoring: Opportunities and Challenges0
HPC-Based Malware Detectors Actually Work: Transition to Practice After a Decade of Research0
Front Cover0
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