IEEE Embedded Systems Letters

Papers
(The median citation count of IEEE Embedded Systems Letters is 1. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-07-01 to 2024-07-01.)
ArticleCitations
Deep Learning Inference Parallelization on Heterogeneous Processors With TensorRT44
A Safe, Secure, and Predictable Software Architecture for Deep Learning in Safety-Critical Systems26
Low-Power Compressor-Based Approximate Multipliers With Error Correcting Module25
CHISEL: Compression-Aware High-Accuracy Embedded Indoor Localization With Deep Learning24
Configurable Logic Blocks and Memory Blocks for Beyond-CMOS FPGA-Based Embedded Systems21
A General Embedded Underwater Acoustic Communication System Based on Advance STM3219
Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators19
Challenges and Limitations of IEEE 802.1CB-201718
Smart Implementation of Industrial Internet of Things Using Embedded Mechatronic System17
Enabling Resource-Aware Mapping of Spiking Neural Networks via Spatial Decomposition17
Deep Learning for Eye Blink Detection Implemented at the Edge16
Reconfigurable Field Effect Transistors Design Solutions for Delay-Invariant Logic Gates16
High-Performance 1-Bit Full Adder With Excellent Driving Capability for Multistage Structures16
Dynamic Partial Reconfiguration Profitability for Real-Time Systems15
Toward Mobile Malware Detection Through Convolutional Neural Networks13
DeBAM: Decoder-Based Approximate Multiplier for Low Power Applications13
High-Level Synthesis of Number-Theoretic Transform: A Case Study for Future Cryptosystems12
Comp-TCAM: An Adaptable Composite Ternary Content-Addressable Memory on FPGAs12
Ring-DVFS: Reliability-Aware Reinforcement Learning-Based DVFS for Real-Time Embedded Systems11
Fast Montgomery Modular Multiplier Using FPGAs11
Combining Thermal Maps With Inception Neural Networks for Hardware Trojan Detection11
Embedded Identification of Surface Based on Multirate Sensor Fusion With Deep Neural Network11
Bactran: A Hardware Batch Normalization Implementation for CNN Training Engine10
Novel SOH Estimation of Lithium-Ion Batteries for Real-Time Embedded Applications10
Design Space Exploration of FPGA-Based System With Multiple DNN Accelerators9
Analytical Performance Modeling of NoCs under Priority Arbitration and Bursty Traffic9
Novel Hardware Trojan Attack on Activation Parameters of FPGA-Based DNN Accelerators9
A Remote Control System for Emergency Ventilators During SARS-CoV-28
Fast and High-Accuracy Approximate MAC Unit Design for CNN Computing8
ARTS: A Framework for AI-Rooted IoT System Design Automation8
DAS: Dynamic Adaptive Scheduling for Energy-Efficient Heterogeneous SoCs8
Implications of Various Preemption Configurations in TSN Networks7
Improving Memory Utilization in Convolutional Neural Network Accelerators7
High Efficient GDI-CNTFET-Based Approximate Full Adder for Next Generation of Computer Architectures7
An Energy-Efficient Routing Method in WSNs Based on Compressive Sensing: From the Perspective of Social Welfare7
Design of a Low-Cost System for the Measurement of Variables Associated With Air Quality7
Secure Register Allocation for Trusted Code Generation6
Needle in a Haystack: Detecting Subtle Malicious Edits to Additive Manufacturing G-Code Files6
Enhancing Matrix Multiplication With a Monolithic 3-D-Based Scratchpad Memory6
Robust and Accurate Fine-Grain Power Models for Embedded Systems With No On-Chip PMU6
WATERMARCH: IP Protection Through Authenticated Obfuscation in FPGA Bitstreams6
Brain-Inspired Hyperdimensional Computing: How Thermal-Friendly for Edge Computing?6
Area-Optimized Constant-Time Hardware Implementation for Polynomial Multiplication6
Hardware Deployable Edge-AI Solution for Prescreening of Oral Tongue Lesions Using TinyML on Embedded Devices5
A Novel Mapping of ECG and PPG to Ensure the Safety of Health Monitoring Applications5
mTREE: A Customized Multicast-Enabled Tree-Based Network on Chip for AI Chips5
HASTE: Software Security Analysis for Timing Attacks on Clear Hardware Assumption5
Meeting Power Constraints While Mitigating Contention on Clustered Multiprocessor System5
Fast LDPC GPU Decoder for Cloud RAN5
High Speed Partial Pattern Classification System Using a CAM-Based LBP Histogram on FPGA5
Guaranteeing That Multilevel Prioritized DNN Models on an Embedded GPU Have Inference Performance Proportional to Respective Priorities5
Aging-Aware Parallel Execution5
A Fully Configurable SoC-Based IR-UWB Platform for Data Acquisition and Algorithm Testing5
Real-Time Optical Localization and Tracking of UAV Using Ellipse Detection5
Gbit/s Throughput Under 6.3-W Lossless Hyperspectral Image Compression on Parallel Embedded Devices5
Efficient Nonprofiled Side-Channel Attack Using Multi-Output Classification Neural Network5
A Q-Learning-Based Fault-Tolerant and Congestion-Aware Adaptive Routing Algorithm for Networks-on-Chip5
Synthesis of Parallel Synchronous Software4
Quant-PIM: An Energy-Efficient Processing-in-Memory Accelerator for Layerwise Quantized Neural Networks4
High-Speed Serial–Parallel Multiplier in Quantum-Dot Cellular Automata4
DB4HLS: A Database of High-Level Synthesis Design Space Explorations4
High-Speed Architecture for Successive Cancellation Decoder With Split-g Node Block4
Three-Stage Power Supply System Model for a Wearable IoT Device for COVID-19 Patients4
Device-Free Human Motion Detection Using Single Link WiFi Channel Measurements for Building Energy Management4
Toward RISC-V CSR Compliance Testing4
FPGA Design of Elliptic Curve Cryptosystem (ECC) for Isomorphic Transformation and EC ElGamal Encryption4
Design and Implementation of an Embedded Cardiorespiratory Monitoring System for Wheelchair Users4
CASH-RF: A Compiler-Assisted Hierarchical Register File in GPUs4
Accelerated Updating Mechanisms for FPGA-Based Ternary Content-Addressable Memory4
A Novel Approach to Design Multiplexer Using Magnetic Quantum-Dot Cellular Automata4
SMT-Based Contention-Free Task Mapping and Scheduling on SMART NoC4
C++20 Coroutines on Microcontrollers—What We Learned4
Communication-Efficient Federated Learning With Gradual Layer Freezing4
SecPump: A Connected Open-Source Infusion Pump for Security Research Purposes4
A Quad-Redundant PLC Architecture for Cyber-Resilient Industrial Control Systems4
Embedded Systems Education: Experiences With Application-Driven Pedagogy3
Trivial Bypassing in GPGPUs3
Location Monitoring System for Sailboats by GPS Using GSM/GPRS Technology3
Diagnostic Accuracy of Smartphone-Connected Electrophysiological Biosensors for Prediction of Blood Glucose Level in a Type-2 Diabetic Patient Using Machine Learning: A Pilot Study3
An Energy Consumption Benchmark for a Low-Power RISC-V Core Aimed at Implantable Medical Devices3
A Hardware-Efficient and Reconfigurable UFMC Transmitter Architecture With its FPGA Prototype3
Design and Implementation of an Embedded Edge-Processing Water Quality Monitoring System for Underground Waters3
Determination of Fiber Content in 3-D Printed Composite Parts Using Image Analysis3
Improved Schedulability Test for Non-Preemptive Fixed-Priority Scheduling on Multiprocessors3
Wearable Device to Monitor Sheep Behavior3
Enabling 3-D Object Detection With a Low-Resolution LiDAR3
Optimizing Learned Bloom Filters: How Much Should Be Learned?3
Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style3
Renée: New Life for Old Phones3
Grey Wolf Optimization Algorithm for Embedded Adaptive Filtering Applications3
A New Approximate Sum of Absolute Differences Unit for Bioimages Processing3
Application Phase Behavior-Guided Thermal Management of Embedded Platforms3
Gradual Channel Estimation Method for TLC NAND Flash Memory3
Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs2
An Efficient Hardware Accelerator for Block Sparse Convolutional Neural Networks on FPGA2
FPGA Implementation of Modified SNOW 3G Stream Ciphers Using Fast and Resource Efficient Substitution Box2
Global Voltage Scaling Across Multiple Cores for Real-Time Workloads2
Are You Sitting With Good Posture? Tracking the Position of the Legs via 2-D LiDAR2
Toward an Optimal Countermeasure for Cache Side-Channel Attacks2
Hardware–Software Co-Optimization of Long-Latency Stochastic Computing2
Design of Leading Zero Counters on FPGAs2
A Hybrid Prototyping Framework in a Virtual Platform Centered Design and Verification Flow2
Flexible Active–Passive and Push–Pull Protocols2
SANGRIA: Stacked Autoencoder Neural Networks With Gradient Boosting for Indoor Localization2
Edge-First Resource Management for Video-Based Applications: A Face Detection Use Case2
Payload-XL: A Platform for the In-Orbit Validation of the BRAVE FPGA2
Efficient Leading Zero Count (LZC) Implementations for Xilinx FPGAs2
Dadu-SV: Accelerate Stereo Vision Processing on NPU2
No-Multiplication Deterministic Hyperdimensional Encoding for Resource-Constrained Devices2
Task Sequencing in Frame-Based CPS2
Improved Low Time-Complexity Schedulability Test for Nonpreemptive EDF on a Multiprocessor2
Implementation of a Convolutional Neural Network Into an Embedded Device for Polyps Detection2
Methodology for CNN Implementation in FPGA-Based Embedded Systems2
WoMA: An Input-Based Learning Model to Predict Dynamic Workload of Embedded Applications2
An XSLT-Based Proposal to Ease Embedded Critical Systems Tools Implementation, Verification, Validation, Testing, and Certification Efforts2
Evolutionary Recurrent Neural Architecture Search2
Predicting Failures in Embedded Systems Using Long Short-Term Inference2
Energy-Efficient Approximate Multiplier Design With Lesser Error Rate Using the Probability-Based Approximate 4:2 Compressor2
CAAM: Compressor-Based Adaptive Approximate Multiplier for Neural Network Applications2
Vector-Based Dedicated Processor Architecture for Efficient Tracking in VSLAM Systems1
EnHDC: Ensemble Learning for Brain-Inspired Hyperdimensional Computing1
A Traceability Localization Method of Acoustic Attack Source for MEMS Gyroscope1
An End-to-End Workflow to Efficiently Compress and Deploy DNN Classifiers On SoC/FPGA1
Data Communication for Low Resources IoT Devices: RS485 Over Electrical Wires1
Regularized Differentiable Architecture Search1
Evaluating the Effects of Reducing Voltage Margins for Energy-Efficient Operation of MPSoCs1
Design and Implementation of a Universal Shift Convolutional Neural Network Accelerator1
Practical and Efficient PUF-Based Protocol for Authentication and Key Agreement in IoT1
Monitoring Software Execution Flow Through Power Consumption and Dynamic Time Warping1
LabOSat-01: A Payload for In-Orbit Device Characterization1
DMMC: A Polar Code Construction Method for Improving Performance in TLC NAND Flash1
Switch-Based High Cardinality Node Detection1
High-Speed Energy-Efficient Fixed-Point Signed Multipliers for FPGA-Based DSP Applications1
Novel Substitution Box Architectural Synthesis for Lightweight Block Ciphers1
Lightweight Robotic Grasping Model Based on Template Matching and Depth Image1
Enhanced Multicore Performance Using Novel Thread-Aware Cache Coherence and Prefetch-Control Mechanism1
Verifying Cross-Layer Interactions Through Formal Model-Based Assertion Generation1
Convolutional Neural Network-Based Signal Classification in Real Time1
Co-Designing Clusters of Lightweight Manycores and Asymmetric Operating System Kernels1
Call String Sensitivity for Hardware-Based Hybrid WCET Analysis1
Design and Implementation of Digital Down Converter for WiFi Network1
Hardware-in-the-Loop Simulation of an On-Board Energy-Driven Scheduling Algorithm for CubeSats1
Efficient Exact Response Time Analysis for Fixed Priority Scheduling in Lowest Priority First-Based Feasibility Tests1
Hybrid Logic Computing of Binary and Stochastic1
Efficient HLS Implementation of Fast Linear Discriminant Analysis Classifier1
Pipelining of a Mobile SoC and an External NPU for Accelerating CNN Inference1
Compilation of Parallel Data Access for Vector Processor in Radio Base Stations1
Sec-NoC: A Lightweight Secure Communication System for On-Chip Interconnects1
High-Flexibility Designs of Quantized Runtime Reconfigurable Multi-Precision Multipliers1
Machine Learning for Sensor Transducer Conversion Routines1
LabOSat-02: Hardware and Firmware Development of an On-Board Computer for Small Satellites1
AbstractSDRs: Bring Down the Two-Language Barrier With Julia Language for Efficient SDR Prototyping1
Mitigating Interactive Performance Degradation From Mobile Device Thermal Throttling1
An Efficient Self-Healing Architecture for Improving the RAS Characteristics of RISC-V Server and Its Quantitative Evaluation Method1
FPGA-Based Accelerator for AI-Toolbox Reinforcement Learning Library1
Efficient Programmable Random Variate Generation Accelerator From Sensor Noise1
Embedded Restricted Boltzmann Machine Approach for Adjustments of Repetitive Physical Activities Using IMU Data1
Automatic Generation of Heterogeneous SoC Architectures With Secure Communications1
SMT-Based Verification of Safety-Critical Embedded Control Software1
Virtio Front-End Network Driver for RTEMS Operating System1
Shared Pattern History Tables in Multicomponent Branch Predictors With a Dealiasing Cache1
DSCAM: Latency-Guaranteed and High-Capacity Content-Addressable Memory on FPGAs1
Cometes: Cross-Device Mapping for Energy and Time-Aware Deployment on Edge Infrastructures1
Automatic Generation of Reconfiguration Blueprints for IMA Systems Using Reinforcement Learning1
DynaFuse: Dynamic Fusion for Resource Efficient Multimodal Machine Learning Inference1
Low-Power Synchronization for Multi-IMU WSNs1
Accelerating the Verification of Forward Error Correction Decoders by PCIe FPGA Cards1
Efficient Transform Algorithms for Parallel Ultra-Low-Power IoT End Nodes1
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