IEEE Embedded Systems Letters

Papers
(The median citation count of IEEE Embedded Systems Letters is 0. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-11-01 to 2024-11-01.)
ArticleCitations
Deep Learning Inference Parallelization on Heterogeneous Processors With TensorRT51
Low-Power Compressor-Based Approximate Multipliers With Error Correcting Module30
CHISEL: Compression-Aware High-Accuracy Embedded Indoor Localization With Deep Learning25
Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators22
A General Embedded Underwater Acoustic Communication System Based on Advance STM3221
Configurable Logic Blocks and Memory Blocks for Beyond-CMOS FPGA-Based Embedded Systems21
Challenges and Limitations of IEEE 802.1CB-201719
Reconfigurable Field Effect Transistors Design Solutions for Delay-Invariant Logic Gates17
Smart Implementation of Industrial Internet of Things Using Embedded Mechatronic System17
Deep Learning for Eye Blink Detection Implemented at the Edge17
Enabling Resource-Aware Mapping of Spiking Neural Networks via Spatial Decomposition17
High-Performance 1-Bit Full Adder With Excellent Driving Capability for Multistage Structures17
DeBAM: Decoder-Based Approximate Multiplier for Low Power Applications16
Dynamic Partial Reconfiguration Profitability for Real-Time Systems15
Ring-DVFS: Reliability-Aware Reinforcement Learning-Based DVFS for Real-Time Embedded Systems13
Toward Mobile Malware Detection Through Convolutional Neural Networks13
Embedded Identification of Surface Based on Multirate Sensor Fusion With Deep Neural Network12
High-Level Synthesis of Number-Theoretic Transform: A Case Study for Future Cryptosystems12
Fast Montgomery Modular Multiplier Using FPGAs12
Novel SOH Estimation of Lithium-Ion Batteries for Real-Time Embedded Applications12
Comp-TCAM: An Adaptable Composite Ternary Content-Addressable Memory on FPGAs12
Fast and High-Accuracy Approximate MAC Unit Design for CNN Computing11
Combining Thermal Maps With Inception Neural Networks for Hardware Trojan Detection11
Bactran: A Hardware Batch Normalization Implementation for CNN Training Engine11
Novel Hardware Trojan Attack on Activation Parameters of FPGA-Based DNN Accelerators10
Analytical Performance Modeling of NoCs under Priority Arbitration and Bursty Traffic10
Design Space Exploration of FPGA-Based System With Multiple DNN Accelerators10
DAS: Dynamic Adaptive Scheduling for Energy-Efficient Heterogeneous SoCs9
Needle in a Haystack: Detecting Subtle Malicious Edits to Additive Manufacturing G-Code Files9
Implications of Various Preemption Configurations in TSN Networks9
A Remote Control System for Emergency Ventilators During SARS-CoV-28
ARTS: A Framework for AI-Rooted IoT System Design Automation8
Design of a Low-Cost System for the Measurement of Variables Associated With Air Quality8
Improving Memory Utilization in Convolutional Neural Network Accelerators7
High Efficient GDI-CNTFET-Based Approximate Full Adder for Next Generation of Computer Architectures7
An Energy-Efficient Routing Method in WSNs Based on Compressive Sensing: From the Perspective of Social Welfare7
WATERMARCH: IP Protection Through Authenticated Obfuscation in FPGA Bitstreams6
HASTE: Software Security Analysis for Timing Attacks on Clear Hardware Assumption6
Secure Register Allocation for Trusted Code Generation6
Brain-Inspired Hyperdimensional Computing: How Thermal-Friendly for Edge Computing?6
Enhancing Matrix Multiplication With a Monolithic 3-D-Based Scratchpad Memory6
Robust and Accurate Fine-Grain Power Models for Embedded Systems With No On-Chip PMU6
Area-Optimized Constant-Time Hardware Implementation for Polynomial Multiplication6
Design and Implementation of an Embedded Cardiorespiratory Monitoring System for Wheelchair Users5
A Fully Configurable SoC-Based IR-UWB Platform for Data Acquisition and Algorithm Testing5
A Novel Mapping of ECG and PPG to Ensure the Safety of Health Monitoring Applications5
A Novel Approach to Design Multiplexer Using Magnetic Quantum-Dot Cellular Automata5
Quant-PIM: An Energy-Efficient Processing-in-Memory Accelerator for Layerwise Quantized Neural Networks5
Efficient Nonprofiled Side-Channel Attack Using Multi-Output Classification Neural Network5
Design and Implementation of an Embedded Edge-Processing Water Quality Monitoring System for Underground Waters5
FPGA Design of Elliptic Curve Cryptosystem (ECC) for Isomorphic Transformation and EC ElGamal Encryption5
Device-Free Human Motion Detection Using Single Link WiFi Channel Measurements for Building Energy Management5
Guaranteeing That Multilevel Prioritized DNN Models on an Embedded GPU Have Inference Performance Proportional to Respective Priorities5
Aging-Aware Parallel Execution5
Fast LDPC GPU Decoder for Cloud RAN5
Hardware Deployable Edge-AI Solution for Prescreening of Oral Tongue Lesions Using TinyML on Embedded Devices5
Real-Time Optical Localization and Tracking of UAV Using Ellipse Detection5
Gbit/s Throughput Under 6.3-W Lossless Hyperspectral Image Compression on Parallel Embedded Devices5
mTREE: A Customized Multicast-Enabled Tree-Based Network on Chip for AI Chips5
A Q-Learning-Based Fault-Tolerant and Congestion-Aware Adaptive Routing Algorithm for Networks-on-Chip5
A Quad-Redundant PLC Architecture for Cyber-Resilient Industrial Control Systems4
No-Multiplication Deterministic Hyperdimensional Encoding for Resource-Constrained Devices4
Optimizing Learned Bloom Filters: How Much Should Be Learned?4
DB4HLS: A Database of High-Level Synthesis Design Space Explorations4
Embedded Systems Education: Experiences With Application-Driven Pedagogy4
SecPump: A Connected Open-Source Infusion Pump for Security Research Purposes4
Three-Stage Power Supply System Model for a Wearable IoT Device for COVID-19 Patients4
Synthesis of Parallel Synchronous Software4
SMT-Based Contention-Free Task Mapping and Scheduling on SMART NoC4
A Hardware-Efficient and Reconfigurable UFMC Transmitter Architecture With its FPGA Prototype4
C++20 Coroutines on Microcontrollers—What We Learned4
High-Speed Architecture for Successive Cancellation Decoder With Split-g Node Block4
Accelerated Updating Mechanisms for FPGA-Based Ternary Content-Addressable Memory4
A New Approximate Sum of Absolute Differences Unit for Bioimages Processing4
Toward RISC-V CSR Compliance Testing4
High-Speed Serial–Parallel Multiplier in Quantum-Dot Cellular Automata4
Communication-Efficient Federated Learning With Gradual Layer Freezing4
CASH-RF: A Compiler-Assisted Hierarchical Register File in GPUs4
An Energy Consumption Benchmark for a Low-Power RISC-V Core Aimed at Implantable Medical Devices4
Gradual Channel Estimation Method for TLC NAND Flash Memory3
Vector-Based Dedicated Processor Architecture for Efficient Tracking in VSLAM Systems3
Efficient Leading Zero Count (LZC) Implementations for Xilinx FPGAs3
SANGRIA: Stacked Autoencoder Neural Networks With Gradient Boosting for Indoor Localization3
Dadu-SV: Accelerate Stereo Vision Processing on NPU3
Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style3
Wearable Device to Monitor Sheep Behavior3
Data Communication for Low Resources IoT Devices: RS485 Over Electrical Wires3
Improved Schedulability Test for Non-Preemptive Fixed-Priority Scheduling on Multiprocessors3
Hybrid Logic Computing of Binary and Stochastic3
High-Speed Energy-Efficient Fixed-Point Signed Multipliers for FPGA-Based DSP Applications3
Toward an Optimal Countermeasure for Cache Side-Channel Attacks3
Trivial Bypassing in GPGPUs3
Middleton’s Class A Noise Parameter Estimator3
Location Monitoring System for Sailboats by GPS Using GSM/GPRS Technology3
Mitigating Interactive Performance Degradation From Mobile Device Thermal Throttling3
Diagnostic Accuracy of Smartphone-Connected Electrophysiological Biosensors for Prediction of Blood Glucose Level in a Type-2 Diabetic Patient Using Machine Learning: A Pilot Study3
Are You Sitting With Good Posture? Tracking the Position of the Legs via 2-D LiDAR3
Enabling 3-D Object Detection With a Low-Resolution LiDAR3
An Efficient Hardware Accelerator for Block Sparse Convolutional Neural Networks on FPGA3
High-Flexibility Designs of Quantized Runtime Reconfigurable Multi-Precision Multipliers3
Renée: New Life for Old Phones3
CAAM: Compressor-Based Adaptive Approximate Multiplier for Neural Network Applications3
Determination of Fiber Content in 3-D Printed Composite Parts Using Image Analysis3
Application Phase Behavior-Guided Thermal Management of Embedded Platforms3
Grey Wolf Optimization Algorithm for Embedded Adaptive Filtering Applications3
LabOSat-01: A Payload for In-Orbit Device Characterization2
Energy-Efficient Approximate Multiplier Design With Lesser Error Rate Using the Probability-Based Approximate 4:2 Compressor2
Evaluating NTT/INTT Implementation Styles for Post-Quantum Cryptography2
Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs2
Accelerating the Verification of Forward Error Correction Decoders by PCIe FPGA Cards2
FPGA Implementation of Modified SNOW 3G Stream Ciphers Using Fast and Resource Efficient Substitution Box2
Cometes: Cross-Device Mapping for Energy and Time-Aware Deployment on Edge Infrastructures2
Hardware-in-the-Loop Simulation of an On-Board Energy-Driven Scheduling Algorithm for CubeSats2
An XSLT-Based Proposal to Ease Embedded Critical Systems Tools Implementation, Verification, Validation, Testing, and Certification Efforts2
Predicting Failures in Embedded Systems Using Long Short-Term Inference2
Task Sequencing in Frame-Based CPS2
Design of Leading Zero Counters on FPGAs2
Flexible Active–Passive and Push–Pull Protocols2
Improved Low Time-Complexity Schedulability Test for Nonpreemptive EDF on a Multiprocessor2
Pipelining of a Mobile SoC and an External NPU for Accelerating CNN Inference2
An Efficient Self-Healing Architecture for Improving the RAS Characteristics of RISC-V Server and Its Quantitative Evaluation Method2
Edge-First Resource Management for Video-Based Applications: A Face Detection Use Case2
Global Voltage Scaling Across Multiple Cores for Real-Time Workloads2
Evolutionary Recurrent Neural Architecture Search2
Hardware–Software Co-Optimization of Long-Latency Stochastic Computing2
LabOSat-02: Hardware and Firmware Development of an On-Board Computer for Small Satellites2
A Hybrid Prototyping Framework in a Virtual Platform Centered Design and Verification Flow2
Implementation of a Convolutional Neural Network Into an Embedded Device for Polyps Detection2
Lightweight Robotic Grasping Model Based on Template Matching and Depth Image2
Methodology for CNN Implementation in FPGA-Based Embedded Systems2
AbstractSDRs: Bring Down the Two-Language Barrier With Julia Language for Efficient SDR Prototyping2
Design and Implementation of Digital Down Converter for WiFi Network2
Payload-XL: A Platform for the In-Orbit Validation of the BRAVE FPGA2
Compilation of Parallel Data Access for Vector Processor in Radio Base Stations2
Automatic Generation of Reconfiguration Blueprints for IMA Systems Using Reinforcement Learning1
Monitoring Software Execution Flow Through Power Consumption and Dynamic Time Warping1
Novel Substitution Box Architectural Synthesis for Lightweight Block Ciphers1
Optimized Local Path Planner Implementation for GPU-Accelerated Embedded Systems1
EnHDC: Ensemble Learning for Brain-Inspired Hyperdimensional Computing1
DMMC: A Polar Code Construction Method for Improving Performance in TLC NAND Flash1
Co-Designing Clusters of Lightweight Manycores and Asymmetric Operating System Kernels1
An End-to-End Workflow to Efficiently Compress and Deploy DNN Classifiers on SoC/FPGA1
Efficient Programmable Random Variate Generation Accelerator From Sensor Noise1
Automatic Generation of Heterogeneous SoC Architectures With Secure Communications1
Power Simulation of a CubeSat: Influence of Orbit, Attitude, and Thermal Control1
An Efficient Edge–Cloud Partitioning of Random Forests for Distributed Sensor Networks1
Vector Accelerator Unit for Caravel1
DSCAM: Latency-Guaranteed and High-Capacity Content-Addressable Memory on FPGAs1
Switch-Based High Cardinality Node Detection1
Design and Implementation of a Universal Shift Convolutional Neural Network Accelerator1
New Paradigm for Contactless Vital Sign Sensing Using UWB Radar and Hybrid Optical Wireless Communications1
Low-Power Synchronization for Multi-IMU WSNs1
DynaFuse: Dynamic Fusion for Resource Efficient Multimodal Machine Learning Inference1
Efficient Transform Algorithms for Parallel Ultra-Low-Power IoT End Nodes1
Sec-NoC: A Lightweight Secure Communication System for On-Chip Interconnects1
FEARLESS: A Federated Reinforcement Learning Orchestrator for Serverless Edge Swarms1
FPGA-Based Accelerator for AI-Toolbox Reinforcement Learning Library1
Embedded Restricted Boltzmann Machine Approach for Adjustments of Repetitive Physical Activities Using IMU Data1
An Approximate Parallel Annealing Ising Machine for Solving Traveling Salesman Problems1
LoRa, Sigfox, and NB-IoT: An Empirical Comparison for IoT LPWAN Technologies in the Agribusiness1
Evaluating the Effects of Reducing Voltage Margins for Energy-Efficient Operation of MPSoCs1
An SoC Design for Future Mobile DNA Detection1
Multigateway Designation for Real-Time TSCH Networks Using Spectral Clustering and Centrality1
Hardware-Level Secure Coding1
Efficient HLS Implementation of Fast Linear Discriminant Analysis Classifier1
SMT-Based Verification of Safety-Critical Embedded Control Software1
Enhanced Multicore Performance Using Novel Thread-Aware Cache Coherence and Prefetch-Control Mechanism1
Machine Learning for Sensor Transducer Conversion Routines1
Convolutional Neural Network-Based Signal Classification in Real Time1
A Traceability Localization Method of Acoustic Attack Source for MEMS Gyroscope1
Design of a Stub-Loaded Coupled Line Diplexer for IoT-Based Applications1
Call String Sensitivity for Hardware-Based Hybrid WCET Analysis1
Regularized Differentiable Architecture Search1
Swift-CNN: Leveraging PCM Memory’s Fast Write Mode to Accelerate CNNs1
Wireless Tag Sensor Network for Apnea Detection and Posture Recognition Using LSTM1
Efficient Exact Response Time Analysis for Fixed Priority Scheduling in Lowest Priority First-Based Feasibility Tests1
Practical and Efficient PUF-Based Protocol for Authentication and Key Agreement in IoT1
Schedulability of Blocking Threads0
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IEEE Embedded Systems Letters Publication Information0
IEEE Embedded Systems Letters Publication Information0
Reduce Refresh Operations on 3-D TLC nand Flash System via Wordline (WL) Interference0
A Graph Attention Network Approach to Partitioned Scheduling in Real-Time Systems0
LoFFT: Low-Voltage FFT Using Lightweight Fault Detection for Energy Efficiency0
SCALLER: Standard Cell Assembled and Local Layout Effect-Based Ring Oscillators0
FedTinyWolf -A Memory Efficient Federated Embedded Learning Mechanism0
Development of a Motion Controller for the Electric Wheelchair of Quadriplegic Patients Using Head Movements Recognition0
Hardware-Aware Bayesian Neural Architecture Search of Quantized CNNs0
Revisiting Black-Hat HLS: A Lightweight Countermeasure to HLS-Aided Trojan Attack0
Pythia: An Edge First Agent for State Prediction in High-Dimensional Environments0
NvMISC: Toward an FPGA-Based Emulation Platform for RISC-V and Nonvolatile Memories0
Design of Tri-Band Bandpass Filter Using Modified X-Shaped Structure for IoT-Based Wireless Applications0
Impulsive Noise Estimator With Minimization Methods (INEMM) on Software0
IEEE Embedded Systems Letters Publication Information0
VANet: A Solution for Ventricular Arrhythmias Detection of IEGM on Embedded Devices0
FPGA Implementation of the Proposed DCNN Model for Detection of Tuberculosis and Pneumonia Using CXR Images0
A Multiplier-Free Discrete Cosine Transform Architecture Using Approximate Full Adder and Subtractor0
IEEE Embedded Systems Letters Publication Information0
CasCon: Cascaded Thermal and Electrical Current Throttling for Mobile Devices0
Exploring Dynamic Duty Cycling for Energy Efficiency in Coherent DSP ASIC0
IEEE Embedded Systems Letters Publication Information0
GNN-MiCS: Graph Neural-Network-Based Bounding Time in Embedded Mixed-Criticality Systems0
Acceleration of an Optimized Kvazaar All Intra Prediction on Embedded Systems Based on the Directional Texture Complexity0
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SoC-Based Implementation of 1D Convolutional Neural Network for 3-Channel ECG Arrhythmia Classification via HLS4ML0
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Usage-Driven Personalization of Power Management Logic0
Hardware and Firmware Design and Implementation of Twin 8-Bit and 32-Bit Microcontroller Boards for Research and Educational Applications0
IEEE Embedded Systems Letters Publication Information0
TinyML-Based Intrusion Detection System for In-Vehicle Network Using Convolutional Neural Network on Embedded Devices0
Time-Sensitive Networking in Low Latency Cyber-Physical Systems0
Hardware Trojan Detection Method Against Balanced Controllability Trigger Design0
An Endogenous Security Study of Telematics Box in Intelligent Connected Vehicles0
Triple-A: Early Operand Collector Allocation for Maximizing GPU Register Bank Utilization0
Detecting Vulnerability in Hardware Description Languages: Opcode Language Processing0
Respiratory Rate Estimation on Embedded System0
Codesign for Generation of Large Random Sequences on Zynq FPGA0
Low Consumption Monitoring and Estimation of the State of Charge System for a Hybrid Electric Vehicle0
TAFT: Thermal-Aware Hybrid Fault-Tolerant Technique for Multicore Embedded Systems0
PROMISE: A Programmable Hardware Monitor for Secure Execution in Zero Trust Networks0
IEEE Embedded Systems Letters Publication Information0
A Co-Optimization of Software and Hardware for PCIe-Based Small Packet DMA Transfer0
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DATA: Throughput and Deadline-Aware Genetic Approach for Task Scheduling in Fog Networks0
Optimal Tasks and Heater Scheduling Applied to the Management of CubeSats Battery Lifespan0
Comparing XML and JSON Characteristics as Formats for Data Serialisation Within Ultra-Low Power Embedded Systems0
M-HLS: Malevolent High-Level Synthesis for Watermarked Hardware IPs0
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Navigating Time and Energy Trade-Offs in Reactive Heterogeneous Systems0
Point Multiplication Accelerator for Arbitrary Montgomery Curves0
A Generic Executable Model for Fast Yet Accurate Contention Simulation in Multiprocessor Systems0
IEEE Embedded Systems Letters publication information0
Configurable Multi-Port Memory Architecture for High-Speed Data Communication0
Design of an Embedded System for Integrated Underwater Communication and Detection0
On-Device Personalization for Human Activity Recognition on STM320
Implementation in FPGA of Alternative Modulation Strategy for Energy Balancing Purposes0
Using Static Analysis for Enhancing HLS Security0
LOTUS: A Scalable Framework to Lock Multi-Module Designs With One-Time Key and Self-Destructive Approaches0
Controlling a House’s Air-Conditioning Using Nonlinear Model Predictive Control0
Experimental Investigation of Side-Channel Attacks on Neuromorphic Spiking Neural Networks0
76.5-Gbps Viterbi Decoder for Convolutional Codes on GPU0
Differentiable Slimming for Memory-Efficient Transformers0
TinyMo: Graph-Level Memory Optimizer for Tiny Machine Learning0
IEEE Embedded Systems Letters Publication Information0
FloripaSat-2: An Open-Source Platform for CubeSats0
Virtually Contiguous Memory Allocation in Embedded Systems: A Performance Analysis0
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Enhancing Perceptual Experience of Video Quality in Drone Communications by Using VPN Bonding0
IDRA: An In-Storage Data Reorganization Accelerator for Multidimensional Databases0
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