ACM Transactions on Reconfigurable Technology and Systems

Papers
(The TQCC of ACM Transactions on Reconfigurable Technology and Systems is 4. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-07-01 to 2024-07-01.)
ArticleCitations
FPGAD efender61
The Future of FPGA Acceleration in Datacenters and the Cloud57
FPGA HLS Today: Successes, Challenges, and Opportunities50
A Software/Hardware Co-Design of Crystals-Dilithium Signature Scheme25
FOS20
Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future Prospects18
MEG16
Low-precision Floating-point Arithmetic for High-performance FPGA-based CNN Acceleration16
Mitigating Voltage Attacks in Multi-Tenant FPGAs14
Accelerating FPGA Routing Through Algorithmic Enhancements and Connection-aware Parallelization13
SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs12
Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL Components11
FlexCNN: An End-to-end Framework for Composing CNN Accelerators on FPGA11
LW-GCN: A Lightweight FPGA-based Graph Convolutional Network Accelerator10
Elastic-DF: Scaling Performance of DNN Inference in FPGA Clouds through Automatic Partitioning10
An Optimized GIB Routing Architecture with Bent Wires for FPGA10
Reconfigurable Framework for Environmentally Adaptive Resilience in Hybrid Space Systems10
Voltage Sensor Implementations for Remote Power Attacks on FPGAs9
Deploying Multi-tenant FPGAs within Linux-based Cloud Infrastructure8
NASCENT2: Generic Near-Storage Sort Accelerator for Data Analytics on SmartSSD8
Cross-VM Covert- and Side-Channel Attacks in Cloud FPGAs8
RWRoute: An Open-source Timing-driven Router for Commercial FPGAs7
AIgean : An Open Framework for Deploying Machine Learning on Heterogeneous Clusters7
The Strong Scaling Advantage of FPGAs in HPC for N-body Simulations7
BlastFunction: A Full-stack Framework Bringing FPGA Hardware Acceleration to Cloud-native Applications7
Design of Distributed Reconfigurable Robotics Systems with ReconROS7
Near-memory Computing on FPGAs with 3D-stacked Memories: Applications, Architectures, and Optimizations7
ThunderGP: Resource-Efficient Graph Processing Framework on FPGAs with HLS6
AutoScaleDSE: A Scalable Design Space Exploration Engine for High-Level Synthesis6
FPGA-based Deep Learning Inference Accelerators: Where Are We Standing?6
Accelerating Weather Prediction Using Near-Memory Reconfigurable Fabric6
High-performance and Configurable SW/HW Co-design of Post-quantum Signature CRYSTALS-Dilithium6
xDNN: Inference for Deep Convolutional Neural Networks6
Tensor Slices: FPGA Building Blocks For The Deep Learning Era6
Enhancing the Security of FPGA-SoCs via the Usage of ARM TrustZone and a Hybrid-TPM5
FPGA Implementation of Compact Hardware Accelerators for Ring-Binary-LWE-based Post-quantum Cryptography5
A Deep Learning Framework to Predict Routability for FPGA Circuit Placement5
A Survey on FPGA Cybersecurity Design Strategies5
RapidStream 2.0: Automated Parallel Implementation of Latency–Insensitive FPGA Designs Through Partial Reconfiguration5
CGRA-EAM—Rapid Energy and Area Estimation for Coarse-grained Reconfigurable Architectures5
UNILOGIC5
Jitter-based Adaptive True Random Number Generation Circuits for FPGAs in the Cloud4
An Empirical Approach to Enhance Performance for Scalable CORDIC-Based Deep Neural Networks4
Parallel Unary Computing Based on Function Derivatives4
An OpenGL Compliant Hardware Implementation of a Graphic Processing Unit Using Field Programmable Gate Array–System on Chip Technology4
Process Variability Analysis in Interconnect, Logic, and Arithmetic Blocks of 16-nm FinFET FPGAs4
Approaches for FPGA Design Assurance4
Stratix 10 NX Architecture4
ACE-GCN: A Fast Data-driven FPGA Accelerator for GCN Embedding4
A Scalable Many-core Overlay Architecture on an HBM2-enabled Multi-Die FPGA4
The Impact of Terrestrial Radiation on FPGAs in Data Centers4
A BNN Accelerator Based on Edge-skip-calculation Strategy and Consolidation Compressed Tree4
FPGA Architecture Exploration for DNN Acceleration4
BurstZ+: Eliminating The Communication Bottleneck of Scientific Computing Accelerators via Accelerated Compression4
Specializing FGPU for Persistent Deep Learning4
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