OOIR: Observatory of International Research

Papers

(The TQCC of ACM Transactions on Reconfigurable Technology and Systems is 6. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-01-01 to 2026-01-01.)

Article	Citations
DF-BETA: An FPGA-based Memory Locality Aware Decision Forest Accelerator via Bit-Level Early Termination	136
HopliteML: Evolving Application Customized FPGA NoCs with Adaptable Routers and Regulators	124
MCoreOPU: An FPGA-based Multi-Core Overlay Processor for Transformer-based Models	49
LHAM: Low-Cost and High-Accuracy Approximate Multiplier for FPGA-Based Computing	44
A Systematic Review of Fast, Scalable, and Efficient Hardware Implementations of Elliptic Curve Cryptography for Blockchain	39
FPGA-Based Sparse Matrix Multiplication Accelerators: From State-of-the-Art to Future Opportunities	35
Tensor Slices: FPGA Building Blocks For The Deep Learning Era	31
High-Throughput TRNG Design with Novelty Adjustable TDC Based on STR	24
Montgomery Multiplication Scalable Systolic Designs Optimized for DSP48E2	21
BurstZ+: Eliminating The Communication Bottleneck of Scientific Computing Accelerators via Accelerated Compression	20
Eciton: Very Low-power Recurrent Neural Network Accelerator for Real-time Inference at the Edge	19
FDRA: A Framework for a Dynamically Reconfigurable Accelerator Supporting Multi-Level Parallelism	19
A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol and its Application	18
RD-FAXID: Ransomware Detection with FPGA-Accelerated XGBoost	17
A Partitioned CAM Architecture with FPGA Acceleration for Binary Descriptor Matching	16
OpenDRAM: A Modular, High-performance Soft Memory Controller for DDR4 DRAM	15
Accelerating In-memory Database Functionality with FPGAs	15
CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning Acceleration	14
FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs	14
A Speculative Loop Pipeline Framework with Accurate Path Modeling for High-Level Synthesis	14
SPARTA: High-Level Synthesis of Parallel Multi-Threaded Accelerators	14
Efficient SpMM Accelerator for Deep Learning: Sparkle and Its Automated Generator	13
Cross-VM Covert- and Side-Channel Attacks in Cloud FPGAs	13
ThunderGP: Resource-Efficient Graph Processing Framework on FPGAs with HLS	13
Composable Open-Source Toolchain for Synthesizing Hardware Accelerators from OpenCL Command Buffers	12

Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-switched Inter-FPGA Networks	12
Adaptive Selection and Clustering of Partial Reconfiguration Modules for Modern FPGA Design Flow	12
Introduction to the Special Issue on RAW 2024	12
Streaming Overlay Architecture for Lightweight LSTM Computation on FPGA SoCs	11
HLPerf: Demystifying the Performance of HLS-based Graph Neural Networks with Dataflow Architectures	10
Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units	10
HiFA: A High-Performance and Flexible Acceleration Framework for Large-Size Number Theoretic Transform	10
Turn on, Tune in, and Listen up: Maximizing Side-Channel Recovery in Cross-Platform Time-to-Digital Converters	10
Covert-channels in FPGA-enabled SmartSSDs	10
Highly Parallel Multi-FPGA System Compilation from Sequential C/C++ Code in the AWS Cloud	10
Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains	10
SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs	9
High-efficiency Compressor Trees for Latest AMD FPGAs	8
CTScan: A CGRA-based Platform for the Emulation of Power Side-Channel Attacks on Edge CPUs	8
End-to-end codesign of Hessian-aware quantized neural networks for FPGAs	8
VERSATILE: Very Fast Partial Reconfiguration Controller	8
da4ml: Distributed Arithmetic for Real-time Neural Networks on FPGAs	8
Introduction to Special Issue on FPGAs in Data Centers	8
MCT-TRNG: Multi-Channel Tetrahedral TRNG via Metastability Enhanced Entropy with 2.2Gbps Throughput	8
Strega : An HTTP Server for FPGAs	7
OmpSs@FPGA: An Open Source Framework for Programming FPGA Clusters	7
Accelerating Weather Prediction Using Near-Memory Reconfigurable Fabric	7
A Scalable Systolic Accelerator for Estimation of the Spectral Correlation Density Function and Its FPGA Implementation	7
Novel Security Threats in Multi-Tenant FPGAs: Phase Tuning for Voltage Sensors in Remote Power Side-Channel Analysis Attacks on AES	7
`QUEKUF` : An FPGA Union Find Decoder for Quantum Error Correction on the Toric Code	7
Inducing Non-uniform FPGA Aging Using Configuration-based Short Circuits	7
Understanding the Potential of FPGA-based Spatial Acceleration for Large Language Model Inference	7
An FPGA Accelerator for Genome Variant Calling	7
Exploring FPGA Switch-Blocks without Explicitly Listing Connectivity Patterns	7
An Energy-Efficient and Real-Time FPGA-Based Point Cloud Registration Framework with Ultra-Fast and Configurable Multi-Mode Correspondence Search	6
xDNN: Inference for Deep Convolutional Neural Networks	6
DANSEN: Database Acceleration on Native Computational Storage by Exploiting NDP	6
FPGA Implementation of Compact Hardware Accelerators for Ring-Binary-LWE-based Post-quantum Cryptography	6
AHCA: Agile Design Framework for Hashcat Acceleration Based on FPGA	6
DONGLE 2.0: Direct FPGA-Orchestrated NVMe Storage for HLS	6