ACM Transactions on Reconfigurable Technology and Systems

Papers
(The TQCC of ACM Transactions on Reconfigurable Technology and Systems is 3. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-02-01 to 2025-02-01.)
ArticleCitations
CHIRP: C ompact and H igh-Performance FPGA Implementation of Un i fied Hardware Accelerators for 66
Multi-Tenant Cloud FPGA: A Survey on Security, Trust and Privacy65
AxOMaP : Designing FPGA-based A ppro x imate Arithmetic O perators using 26
High-efficiency Compressor Trees for Latest AMD FPGAs20
Approximate Constant-Coefficient Multiplication Using Hybrid Binary-Unary Computing for FPGAs19
Introduction to Special Section on FPGA 202118
An FPGA Accelerator for Genome Variant Calling18
A Unified FPGA Virtualization Framework for General-Purpose Deep Neural Networks in the Cloud17
BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining16
Introduction to Special Issue on FPGAs in Data Centers14
Adaptive Clock Management of HLS-generated Circuits on FPGAs13
Introduction to the Special Section on FPGA 202213
Introduction to the Special Section on FPL 201912
Median Filters on FPGAs for Infinite Data and Large, Rectangular Windows11
HopliteML: Evolving Application Customized FPGA NoCs with Adaptable Routers and Regulators11
Artifact Evaluation for ACM TRETS Papers Submitted from the FPT Journal Track10
Accelerating Weather Prediction Using Near-Memory Reconfigurable Fabric9
Design, Calibration, and Evaluation of Real-time Waveform Matching on an FPGA-based Digitizer at 10 GS/s9
Reprogrammable Non-Linear Circuits Using ReRAM for NN Accelerators9
AutoScaleDSE: A Scalable Design Space Exploration Engine for High-Level Synthesis8
Design and Evaluation of a Tunable PUF Architecture for FPGAs8
FPGA Accelerated Implementation of 3D Mesh Secret Sharing Based on Symmetric Similarity of Model7
High Throughput FPGA-Based Object Detection via Algorithm-Hardware Co-Design7
Understanding the Potential of FPGA-based Spatial Acceleration for Large Language Model Inference7
A Systematic Review of Fast, Scalable, and Efficient Hardware Implementations of Elliptic Curve Cryptography for Blockchain7
TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design7
Exploring FPGA Switch-Blocks without Explicitly Listing Connectivity Patterns7
Tensor Slices: FPGA Building Blocks For The Deep Learning Era7
RapidStream 2.0: Automated Parallel Implementation of Latency–Insensitive FPGA Designs Through Partial Reconfiguration7
Mitigating Voltage Attacks in Multi-Tenant FPGAs6
L-FNNG: Accelerating Large-Scale KNN Graph Construction on CPU-FPGA Heterogeneous Platform6
FPGA HLS Today: Successes, Challenges, and Opportunities6
Toward Software-like Debugging for FPGAs via Checkpointing and Transaction-based Co-Simulation6
Buffer Placement and Sizing for High-Performance Dataflow Circuits5
VCSN: Virtual Circuit-Switching Network for Flexible and Simple-to-Operate Communication in HPC FPGA Cluster5
A Survey on FPGA Cybersecurity Design Strategies5
Canalis: A Throughput-Optimized Framework for Real-Time Stream Processing of Wireless Communication5
FPGA Implementation of Compact Hardware Accelerators for Ring-Binary-LWE-based Post-quantum Cryptography5
A Scalable Systolic Accelerator for Estimation of the Spectral Correlation Density Function and Its FPGA Implementation5
When Massive GPU Parallelism Ain’t Enough: A Novel Hardware Architecture of 2D-LSTM Neural Network5
DF-BETA: An FPGA-based Memory Locality Aware Decision Forest Accelerator via Bit-Level Early Termination5
BurstZ+: Eliminating The Communication Bottleneck of Scientific Computing Accelerators via Accelerated Compression5
Eciton: Very Low-power Recurrent Neural Network Accelerator for Real-time Inference at the Edge5
Design and Implementation of Hardware-Software Architecture Based on Hashes for SPHINCS+5
FPGA-Based Sparse Matrix Multiplication Accelerators: From State-of-the-Art to Future Opportunities5
Topgun: An ECC Accelerator for Private Set Intersection4
Practical Model Checking on FPGAs4
A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol and its Application4
Inducing Non-uniform FPGA Aging Using Configuration-based Short Circuits4
Quick-Div: Rethinking Integer Divider Design for FPGA-based Soft-processors4
HierCGRA: A Novel Framework for Large-scale CGRA with Hierarchical Modeling and Automated Design Space Exploration3
Strega : An HTTP Server for FPGAs3
FPGA-based Deep Learning Inference Accelerators: Where Are We Standing?3
High-efficiency TRNG Design Based on Multi-bit Dual-ring Oscillator3
ScalaBFS2: A High-performance BFS Accelerator on an HBM-enhanced FPGA Chip3
FlexCNN: An End-to-end Framework for Composing CNN Accelerators on FPGA3
Automated Buffer Sizing of Dataflow Applications in a High-level Synthesis Workflow3
Hipernetch: High-Performance FPGA Network Switch3
xDNN: Inference for Deep Convolutional Neural Networks3
A Software/Hardware Co-Design of Crystals-Dilithium Signature Scheme3
DANSEN: Database Acceleration on Native Computational Storage by Exploiting NDP3
FDRA: A Framework for a Dynamically Reconfigurable Accelerator Supporting Multi-Level Parallelism3
Elastic-DF: Scaling Performance of DNN Inference in FPGA Clouds through Automatic Partitioning3
Montgomery Multiplication Scalable Systolic Designs Optimized for DSP48E23
CHIP-KNNv2: AConfigurable andHigh-PerformanceK-NearestNeighbors Accelerator on HBM-based FPGAs3
SQL2FPGA: Automated Acceleration of SQL Query Processing on Modern CPU-FPGA Platforms3
Deploying Multi-tenant FPGAs within Linux-based Cloud Infrastructure3
Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL Components3
Design and Analysis of Configurable Ring Oscillators for True Random Number Generation Based on Coherent Sampling3
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