ACM Transactions on Reconfigurable Technology and Systems

Papers
(The TQCC of ACM Transactions on Reconfigurable Technology and Systems is 4. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-05-01 to 2025-05-01.)
ArticleCitations
Design and Evaluation of a Tunable PUF Architecture for FPGAs96
HopliteML: Evolving Application Customized FPGA NoCs with Adaptable Routers and Regulators90
FPGA-Based Sparse Matrix Multiplication Accelerators: From State-of-the-Art to Future Opportunities30
DF-BETA: An FPGA-based Memory Locality Aware Decision Forest Accelerator via Bit-Level Early Termination29
A Systematic Review of Fast, Scalable, and Efficient Hardware Implementations of Elliptic Curve Cryptography for Blockchain26
Mitigating Voltage Attacks in Multi-Tenant FPGAs23
Tensor Slices: FPGA Building Blocks For The Deep Learning Era22
BurstZ+: Eliminating The Communication Bottleneck of Scientific Computing Accelerators via Accelerated Compression21
RD-FAXID: Ransomware Detection with FPGA-Accelerated XGBoost20
A Software/Hardware Co-Design of Crystals-Dilithium Signature Scheme18
High-throughput TRNG design with novelty adjustable TDC based on STR16
FDRA: A Framework for a Dynamically Reconfigurable Accelerator Supporting Multi-Level Parallelism16
A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol and its Application16
Eciton: Very Low-power Recurrent Neural Network Accelerator for Real-time Inference at the Edge14
Montgomery Multiplication Scalable Systolic Designs Optimized for DSP48E213
FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs13
CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning Acceleration13
SPARTA: High-Level Synthesis of Parallel Multi-Threaded Accelerators13
A Speculative Loop Pipeline Framework with Accurate Path Modeling for High-Level Synthesis12
Accelerating In-memory Database Functionality with FPGAs12
A Partitioned CAM Architecture with FPGA Acceleration for Binary Descriptor Matching12
Streaming Overlay Architecture for Lightweight LSTM Computation on FPGA SoCs11
Efficient SpMM Accelerator for Deep Learning: Sparkle and Its Automated Generator11
Cross-VM Covert- and Side-Channel Attacks in Cloud FPGAs11
Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-switched Inter-FPGA Networks11
ThunderGP: Resource-Efficient Graph Processing Framework on FPGAs with HLS11
Adaptive Selection and Clustering of Partial Reconfiguration Modules for Modern FPGA Design Flow10
Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains10
HLPerf: Demystifying the Performance of HLS-based Graph Neural Networks with Dataflow Architectures9
BISWSRBS: A Winograd-based CNN Accelerator with a Fine-grained Regular Sparsity Pattern and Mixed Precision Quantization9
CTScan: A CGRA-based Platform for the Emulation of Power Side-Channel Attacks on Edge CPUs8
RWRoute: An Open-source Timing-driven Router for Commercial FPGAs8
Cloud Building Block Chip for Creating FPGA and ASIC Clouds8
Highly Parallel Multi-FPGA System Compilation from Sequential C/C++ Code in the AWS Cloud7
Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units7
Covert-channels in FPGA-enabled SmartSSDs7
SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs7
End-to-end codesign of Hessian-aware quantized neural networks for FPGAs7
Introduction to the Special Section on FPL 20197
Turn on, Tune in, and Listen up: Maximizing Side-Channel Recovery in Cross-Platform Time-to-Digital Converters7
Introduction to Special Issue on FPGAs in Data Centers6
Exploring FPGA Switch-Blocks without Explicitly Listing Connectivity Patterns6
An FPGA Accelerator for Genome Variant Calling6
Accelerating Weather Prediction Using Near-Memory Reconfigurable Fabric6
xDNN: Inference for Deep Convolutional Neural Networks5
QUEKUF: an FPGA Union Find Decoder for Quantum Error Correction on the Toric Code5
DONGLE 2.0: Direct FPGA-Orchestrated NVMe Storage for HLS5
High-efficiency Compressor Trees for Latest AMD FPGAs5
Inducing Non-uniform FPGA Aging Using Configuration-based Short Circuits5
Strega : An HTTP Server for FPGAs5
FPGA Implementation of Compact Hardware Accelerators for Ring-Binary-LWE-based Post-quantum Cryptography5
Understanding the Potential of FPGA-based Spatial Acceleration for Large Language Model Inference5
A Scalable Systolic Accelerator for Estimation of the Spectral Correlation Density Function and Its FPGA Implementation5
DANSEN: Database Acceleration on Native Computational Storage by Exploiting NDP5
ACE-GCN: A Fast Data-driven FPGA Accelerator for GCN Embedding5
Introduction to the Special Section on FCCM 20224
A Hardware Design Framework for Computer Vision Models Based on Reconfigurable Devices4
Introduction to Special Issue on FPGAs in Data Centers, Part II4
Data and Computation Reuse in CNNs Using Memristor TCAMs4
A Reconfigurable Architecture for Real-time Event-based Multi-Object Tracking4
Design Space Exploration of Galois and Fibonacci Configuration Based on Espresso Stream Cipher4
CSAIL2019 Crypto-Puzzle Solver Architecture4
FiberFlex: Real-time FPGA-based Intelligent and Distributed Fiber Sensor System for Pedestrian Recognition4
Compressing Neural Networks using Learnable 1D Non-Linear Functions4
LW-GCN: A Lightweight FPGA-based Graph Convolutional Network Accelerator4
Introduction to the Special Section on FPL 20204
Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis4
Codesign of Reactor-Oriented Hardware and Software for Cyber-Physical Systems4
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