ACM Transactions on Reconfigurable Technology and Systems

Papers
(The TQCC of ACM Transactions on Reconfigurable Technology and Systems is 7. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-08-01 to 2026-08-01.)
ArticleCitations
LHAM: Low-Cost and High-Accuracy Approximate Multiplier for FPGA-Based Computing164
HopliteML: Evolving Application Customized FPGA NoCs with Adaptable Routers and Regulators69
Tensor Slices: FPGA Building Blocks For The Deep Learning Era69
A Systematic Review of Fast, Scalable, and Efficient Hardware Implementations of Elliptic Curve Cryptography for Blockchain57
DF-BETA: An FPGA-based Memory Locality Aware Decision Forest Accelerator via Bit-Level Early Termination46
MCoreOPU: An FPGA-based Multi-Core Overlay Processor for Transformer-based Models40
A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol and its Application30
FPGA-Based Sparse Matrix Multiplication Accelerators: From State-of-the-Art to Future Opportunities30
Montgomery Multiplication Scalable Systolic Designs Optimized for DSP48E225
RD-FAXID: Ransomware Detection with FPGA-Accelerated XGBoost24
Eciton: Very Low-power Recurrent Neural Network Accelerator for Real-time Inference at the Edge24
High-Throughput TRNG Design with Novelty Adjustable TDC Based on STR22
FDRA: A Framework for a Dynamically Reconfigurable Accelerator Supporting Multi-Level Parallelism21
An MLIR-Based Compilation Framework for Control Flow Management on Coarse Grained Reconfigurable Arrays21
Accelerating In-memory Database Functionality with FPGAs21
FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs20
SIRA : Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators19
A Partitioned CAM Architecture with FPGA Acceleration for Binary Descriptor Matching19
A Speculative Loop Pipeline Framework with Accurate Path Modeling for High-Level Synthesis19
Introduction to the Special Issue on RAW 202518
SPARTA: High-Level Synthesis of Parallel Multi-Threaded Accelerators18
A Flexible FPGA-based Butterfly Engine for Accelerating Signal Processing and Machine Learning17
OpenDRAM: A Modular, High-performance Soft Memory Controller for DDR4 DRAM17
CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning Acceleration17
AIEAnalyzer: An Analytical Framework for Versal AI Engine Performance Analysis17
Introduction to the Special Issue on RAW 202417
Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-switched Inter-FPGA Networks15
Efficient SpMM Accelerator for Deep Learning: Sparkle and Its Automated Generator14
ThunderGP: Resource-Efficient Graph Processing Framework on FPGAs with HLS14
Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains13
Breaking the Scalability Barrier of Content Addressable Memories: A Probabilistic Alternative for Large-Key Associative Search13
HLPerf: Demystifying the Performance of HLS-based Graph Neural Networks with Dataflow Architectures13
Composable Open Source Toolchain for Synthesizing Hardware Accelerators from OpenCL Command Buffers13
Cross-VM Covert- and Side-Channel Attacks in Cloud FPGAs13
hls4ml: A Flexible, Open Source Platform for Deep Learning Acceleration on Reconfigurable Hardware12
HiFA: A High-Performance and Flexible Acceleration Framework for Large-Size Number Theoretic Transform12
Adaptive Selection and Clustering of Partial Reconfiguration Modules for Modern FPGA Design Flow12
Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units11
Streaming Overlay Architecture for Lightweight LSTM Computation on FPGA SoCs11
MCT-TRNG: Multi-Channel Tetrahedral TRNG via Metastability-Enhanced Entropy with 2.2 Gbps Throughput10
Highly Parallel Multi-FPGA System Compilation from Sequential C/C++ Code in the AWS Cloud10
Covert-channels in FPGA-enabled SmartSSDs10
CTScan: A CGRA-based Platform for the Emulation of Power Side-Channel Attacks on Edge CPUs10
End-to-end codesign of Hessian-aware quantized neural networks for FPGAs9
SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs9
A Survey of FPGA Placement Algorithms: From Monolithic Devices to Multi-Die Architectures9
Novel Security Threats in Multi-Tenant FPGAs: Phase Tuning for Voltage Sensors in Remote Power Side-Channel Analysis Attacks on AES8
High-efficiency Compressor Trees for Latest AMD FPGAs8
Understanding the Potential of FPGA-based Spatial Acceleration for Large Language Model Inference8
Turn on, Tune in, and Listen up: Maximizing Side-Channel Recovery in Cross-Platform Time-to-Digital Converters8
Exploring FPGA Switch-Blocks without Explicitly Listing Connectivity Patterns8
OmpSs@FPGA: An Open Source Framework for Programming FPGA Clusters8
QUEKUF : An FPGA Union Find Decoder for Quantum Error Correction on the Toric Code8
da4ml: Distributed Arithmetic for Real-time Neural Networks on FPGAs8
An FPGA Accelerator for Genome Variant Calling8
VERSATILE: Very Fast Partial Reconfiguration Controller8
Strega : An HTTP Server for FPGAs8
FPGA Implementation of Compact Hardware Accelerators for Ring-Binary-LWE-based Post-quantum Cryptography7
cgra4ml : A Hardware/Software Framework to Implement Neural Networks for Scientific Edge Computing7
An Energy-Efficient and Real-Time FPGA-Based Point Cloud Registration Framework with Ultra-Fast and Configurable Multi-Mode Correspondence Search7
DONGLE 2.0: Direct FPGA-Orchestrated NVMe Storage for HLS7
DANSEN: Database Acceleration on Native Computational Storage by Exploiting NDP7
AHCA: Agile Design Framework for Hashcat Acceleration Based on FPGA7
A Scalable Systolic Accelerator for Estimation of the Spectral Correlation Density Function and Its FPGA Implementation7
Introduction to the Special Section on FCCM 20227
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