OOIR: Observatory of International Research

Papers

(The TQCC of ACM Transactions on Reconfigurable Technology and Systems is 7. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-05-01 to 2026-05-01.)

Article	Citations
DF-BETA: An FPGA-based Memory Locality Aware Decision Forest Accelerator via Bit-Level Early Termination	152
LHAM: Low-Cost and High-Accuracy Approximate Multiplier for FPGA-Based Computing	61
HopliteML: Evolving Application Customized FPGA NoCs with Adaptable Routers and Regulators	60
A Systematic Review of Fast, Scalable, and Efficient Hardware Implementations of Elliptic Curve Cryptography for Blockchain	56
Tensor Slices: FPGA Building Blocks For The Deep Learning Era	41
MCoreOPU: An FPGA-based Multi-Core Overlay Processor for Transformer-based Models	36
FPGA-Based Sparse Matrix Multiplication Accelerators: From State-of-the-Art to Future Opportunities	28
Eciton: Very Low-power Recurrent Neural Network Accelerator for Real-time Inference at the Edge	27
A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol and its Application	21
FDRA: A Framework for a Dynamically Reconfigurable Accelerator Supporting Multi-Level Parallelism	21
RD-FAXID: Ransomware Detection with FPGA-Accelerated XGBoost	21
Montgomery Multiplication Scalable Systolic Designs Optimized for DSP48E2	20
Accelerating In-memory Database Functionality with FPGAs	19
High-Throughput TRNG Design with Novelty Adjustable TDC Based on STR	19
FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs	18
SPARTA: High-Level Synthesis of Parallel Multi-Threaded Accelerators	17
A Speculative Loop Pipeline Framework with Accurate Path Modeling for High-Level Synthesis	17
A Partitioned CAM Architecture with FPGA Acceleration for Binary Descriptor Matching	17
OpenDRAM: A Modular, High-performance Soft Memory Controller for DDR4 DRAM	17
CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning Acceleration	16
SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators	16
Composable Open-Source Toolchain for Synthesizing Hardware Accelerators from OpenCL Command Buffers	16
Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-switched Inter-FPGA Networks	15
Introduction to the Special Issue on RAW 2024	15
Efficient SpMM Accelerator for Deep Learning: Sparkle and Its Automated Generator	14

Cross-VM Covert- and Side-Channel Attacks in Cloud FPGAs	14
Adaptive Selection and Clustering of Partial Reconfiguration Modules for Modern FPGA Design Flow	12
hls4ml: A Flexible, Open-Source Platform for Deep Learning Acceleration on Reconfigurable Hardware	12
Breaking the Scalability Barrier of Content Addressable Memories: A Probabilistic Alternative for Large-Key Associative Search	12
HiFA: A High-Performance and Flexible Acceleration Framework for Large-Size Number Theoretic Transform	12
ThunderGP: Resource-Efficient Graph Processing Framework on FPGAs with HLS	12
Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains	12
Streaming Overlay Architecture for Lightweight LSTM Computation on FPGA SoCs	11
Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units	11
HLPerf: Demystifying the Performance of HLS-based Graph Neural Networks with Dataflow Architectures	11
Highly Parallel Multi-FPGA System Compilation from Sequential C/C++ Code in the AWS Cloud	11
SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs	10
CTScan: A CGRA-based Platform for the Emulation of Power Side-Channel Attacks on Edge CPUs	10
Turn on, Tune in, and Listen up: Maximizing Side-Channel Recovery in Cross-Platform Time-to-Digital Converters	10
MCT-TRNG: Multi-Channel Tetrahedral TRNG via Metastability-Enhanced Entropy with 2.2 Gbps Throughput	9
A Survey of FPGA Placement Algorithms: From Monolithic Devices to Multi-Die Architectures	8
Exploring FPGA Switch-Blocks without Explicitly Listing Connectivity Patterns	8
An FPGA Accelerator for Genome Variant Calling	8
`QUEKUF` : An FPGA Union Find Decoder for Quantum Error Correction on the Toric Code	8
AHCA: Agile Design Framework for Hashcat Acceleration Based on FPGA	8
High-efficiency Compressor Trees for Latest AMD FPGAs	8
da4ml: Distributed Arithmetic for Real-time Neural Networks on FPGAs	8
End-to-end codesign of Hessian-aware quantized neural networks for FPGAs	8
OmpSs@FPGA: An Open Source Framework for Programming FPGA Clusters	8
Accelerating Weather Prediction Using Near-Memory Reconfigurable Fabric	8
Strega : An HTTP Server for FPGAs	8
An Energy-Efficient and Real-Time FPGA-Based Point Cloud Registration Framework with Ultra-Fast and Configurable Multi-Mode Correspondence Search	8
Covert-channels in FPGA-enabled SmartSSDs	8
VERSATILE: Very Fast Partial Reconfiguration Controller	8
Novel Security Threats in Multi-Tenant FPGAs: Phase Tuning for Voltage Sensors in Remote Power Side-Channel Analysis Attacks on AES	8
Understanding the Potential of FPGA-based Spatial Acceleration for Large Language Model Inference	8
FPGA Implementation of Compact Hardware Accelerators for Ring-Binary-LWE-based Post-quantum Cryptography	8
A Scalable Systolic Accelerator for Estimation of the Spectral Correlation Density Function and Its FPGA Implementation	8
DANSEN: Database Acceleration on Native Computational Storage by Exploiting NDP	7
Accelerated Phylogenetics on the AMD Versal Adaptive SoC	7
CGRA4ML : A Hardware/Software Framework to Implement Neural Networks for Scientific Edge Computing	7
DONGLE 2.0: Direct FPGA-Orchestrated NVMe Storage for HLS	7
Inducing Non-uniform FPGA Aging Using Configuration-based Short Circuits	7
Introduction to the Special Section on FCCM 2022	7