ACM Transactions on Reconfigurable Technology and Systems

Papers
(The TQCC of ACM Transactions on Reconfigurable Technology and Systems is 3. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-11-01 to 2024-11-01.)
ArticleCitations
The Future of FPGA Acceleration in Datacenters and the Cloud63
FPGA HLS Today: Successes, Challenges, and Opportunities60
A Software/Hardware Co-Design of Crystals-Dilithium Signature Scheme26
Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future Prospects20
Low-precision Floating-point Arithmetic for High-performance FPGA-based CNN Acceleration19
SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs16
FlexCNN: An End-to-end Framework for Composing CNN Accelerators on FPGA15
Mitigating Voltage Attacks in Multi-Tenant FPGAs14
NASCENT2: Generic Near-Storage Sort Accelerator for Data Analytics on SmartSSD14
LW-GCN: A Lightweight FPGA-based Graph Convolutional Network Accelerator14
An Optimized GIB Routing Architecture with Bent Wires for FPGA13
Elastic-DF: Scaling Performance of DNN Inference in FPGA Clouds through Automatic Partitioning12
Deploying Multi-tenant FPGAs within Linux-based Cloud Infrastructure11
Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL Components11
Voltage Sensor Implementations for Remote Power Attacks on FPGAs11
RWRoute: An Open-source Timing-driven Router for Commercial FPGAs10
Near-memory Computing on FPGAs with 3D-stacked Memories: Applications, Architectures, and Optimizations9
Cross-VM Covert- and Side-Channel Attacks in Cloud FPGAs9
ThunderGP: Resource-Efficient Graph Processing Framework on FPGAs with HLS9
FPGA-based Deep Learning Inference Accelerators: Where Are We Standing?8
The Strong Scaling Advantage of FPGAs in HPC for N-body Simulations8
AIgean : An Open Framework for Deploying Machine Learning on Heterogeneous Clusters7
Accelerating Weather Prediction Using Near-Memory Reconfigurable Fabric7
BlastFunction: A Full-stack Framework Bringing FPGA Hardware Acceleration to Cloud-native Applications7
A Survey on FPGA Cybersecurity Design Strategies7
Tensor Slices: FPGA Building Blocks For The Deep Learning Era7
Design of Distributed Reconfigurable Robotics Systems with ReconROS7
FPGA Implementation of Compact Hardware Accelerators for Ring-Binary-LWE-based Post-quantum Cryptography7
AutoScaleDSE: A Scalable Design Space Exploration Engine for High-Level Synthesis6
CGRA-EAM—Rapid Energy and Area Estimation for Coarse-grained Reconfigurable Architectures6
High-performance and Configurable SW/HW Co-design of Post-quantum Signature CRYSTALS-Dilithium6
A Scalable Many-core Overlay Architecture on an HBM2-enabled Multi-Die FPGA5
Automatic Creation of High-bandwidth Memory Architectures from Domain-specific Languages: The Case of Computational Fluid Dynamics5
Stratix 10 NX Architecture5
xDNN: Inference for Deep Convolutional Neural Networks5
A Deep Learning Framework to Predict Routability for FPGA Circuit Placement5
Enhancing the Security of FPGA-SoCs via the Usage of ARM TrustZone and a Hybrid-TPM5
FPGA Architecture Exploration for DNN Acceleration5
TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design5
Process Variability Analysis in Interconnect, Logic, and Arithmetic Blocks of 16-nm FinFET FPGAs5
Jitter-based Adaptive True Random Number Generation Circuits for FPGAs in the Cloud5
ACE-GCN: A Fast Data-driven FPGA Accelerator for GCN Embedding5
RapidStream 2.0: Automated Parallel Implementation of Latency–Insensitive FPGA Designs Through Partial Reconfiguration5
The Impact of Terrestrial Radiation on FPGAs in Data Centers4
ADAS: A High Computational Utilization D ynamic Reconfigurable Hardware A ccelerator for S4
Approaches for FPGA Design Assurance4
An Empirical Approach to Enhance Performance for Scalable CORDIC-Based Deep Neural Networks4
Specializing FGPU for Persistent Deep Learning4
A BNN Accelerator Based on Edge-skip-calculation Strategy and Consolidation Compressed Tree4
BurstZ+: Eliminating The Communication Bottleneck of Scientific Computing Accelerators via Accelerated Compression4
Algorithm-hardware Co-optimization for Energy-efficient Drone Detection on Resource-constrained FPGA3
A Reconfigurable Architecture for Real-time Event-based Multi-Object Tracking3
Hipernetch: High-Performance FPGA Network Switch3
Approximate Constant-Coefficient Multiplication Using Hybrid Binary-Unary Computing for FPGAs3
SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs3
Exploiting HBM on FPGAs for Data Processing3
CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning Acceleration3
CHIP-KNNv2: AConfigurable andHigh-PerformanceK-NearestNeighbors Accelerator on HBM-based FPGAs3
Design and Analysis of Configurable Ring Oscillators for True Random Number Generation Based on Coherent Sampling3
A Unified FPGA Virtualization Framework for General-Purpose Deep Neural Networks in the Cloud3
ZyPR: End-to-end Build Tool and Runtime Manager for Partial Reconfiguration of FPGA SoCs at the Edge3
Hardware Optimizations of Fruit-80 Stream Cipher: Smaller than Grain3
Demystifying the Soft and Hardened Memory Systems of Modern FPGAs for Software Programmers through Microbenchmarking3
RapidLayout: Fast Hard Block Placement of FPGA-optimized Systolic Arrays Using Evolutionary Algorithm3
High-efficiency TRNG Design Based on Multi-bit Dual-ring Oscillator3
When Massive GPU Parallelism Ain’t Enough: A Novel Hardware Architecture of 2D-LSTM Neural Network3
A Real-Time Deep Learning OFDM Receiver3
Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains3
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