ACM Transactions on Reconfigurable Technology and Systems

Papers
(The median citation count of ACM Transactions on Reconfigurable Technology and Systems is 1. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-05-01 to 2025-05-01.)
ArticleCitations
Design and Evaluation of a Tunable PUF Architecture for FPGAs96
HopliteML: Evolving Application Customized FPGA NoCs with Adaptable Routers and Regulators90
FPGA-Based Sparse Matrix Multiplication Accelerators: From State-of-the-Art to Future Opportunities30
DF-BETA: An FPGA-based Memory Locality Aware Decision Forest Accelerator via Bit-Level Early Termination29
A Systematic Review of Fast, Scalable, and Efficient Hardware Implementations of Elliptic Curve Cryptography for Blockchain26
Mitigating Voltage Attacks in Multi-Tenant FPGAs23
Tensor Slices: FPGA Building Blocks For The Deep Learning Era22
BurstZ+: Eliminating The Communication Bottleneck of Scientific Computing Accelerators via Accelerated Compression21
RD-FAXID: Ransomware Detection with FPGA-Accelerated XGBoost20
A Software/Hardware Co-Design of Crystals-Dilithium Signature Scheme18
FDRA: A Framework for a Dynamically Reconfigurable Accelerator Supporting Multi-Level Parallelism16
A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol and its Application16
High-throughput TRNG design with novelty adjustable TDC based on STR16
Eciton: Very Low-power Recurrent Neural Network Accelerator for Real-time Inference at the Edge14
CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning Acceleration13
SPARTA: High-Level Synthesis of Parallel Multi-Threaded Accelerators13
Montgomery Multiplication Scalable Systolic Designs Optimized for DSP48E213
FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs13
Accelerating In-memory Database Functionality with FPGAs12
A Partitioned CAM Architecture with FPGA Acceleration for Binary Descriptor Matching12
A Speculative Loop Pipeline Framework with Accurate Path Modeling for High-Level Synthesis12
Streaming Overlay Architecture for Lightweight LSTM Computation on FPGA SoCs11
Efficient SpMM Accelerator for Deep Learning: Sparkle and Its Automated Generator11
Cross-VM Covert- and Side-Channel Attacks in Cloud FPGAs11
Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-switched Inter-FPGA Networks11
ThunderGP: Resource-Efficient Graph Processing Framework on FPGAs with HLS11
Adaptive Selection and Clustering of Partial Reconfiguration Modules for Modern FPGA Design Flow10
Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains10
HLPerf: Demystifying the Performance of HLS-based Graph Neural Networks with Dataflow Architectures9
BISWSRBS: A Winograd-based CNN Accelerator with a Fine-grained Regular Sparsity Pattern and Mixed Precision Quantization9
CTScan: A CGRA-based Platform for the Emulation of Power Side-Channel Attacks on Edge CPUs8
RWRoute: An Open-source Timing-driven Router for Commercial FPGAs8
Cloud Building Block Chip for Creating FPGA and ASIC Clouds8
Highly Parallel Multi-FPGA System Compilation from Sequential C/C++ Code in the AWS Cloud7
Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units7
Covert-channels in FPGA-enabled SmartSSDs7
SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs7
End-to-end codesign of Hessian-aware quantized neural networks for FPGAs7
Introduction to the Special Section on FPL 20197
Turn on, Tune in, and Listen up: Maximizing Side-Channel Recovery in Cross-Platform Time-to-Digital Converters7
Exploring FPGA Switch-Blocks without Explicitly Listing Connectivity Patterns6
An FPGA Accelerator for Genome Variant Calling6
Accelerating Weather Prediction Using Near-Memory Reconfigurable Fabric6
Introduction to Special Issue on FPGAs in Data Centers6
High-efficiency Compressor Trees for Latest AMD FPGAs5
Inducing Non-uniform FPGA Aging Using Configuration-based Short Circuits5
Strega : An HTTP Server for FPGAs5
FPGA Implementation of Compact Hardware Accelerators for Ring-Binary-LWE-based Post-quantum Cryptography5
Understanding the Potential of FPGA-based Spatial Acceleration for Large Language Model Inference5
A Scalable Systolic Accelerator for Estimation of the Spectral Correlation Density Function and Its FPGA Implementation5
DANSEN: Database Acceleration on Native Computational Storage by Exploiting NDP5
ACE-GCN: A Fast Data-driven FPGA Accelerator for GCN Embedding5
xDNN: Inference for Deep Convolutional Neural Networks5
QUEKUF: an FPGA Union Find Decoder for Quantum Error Correction on the Toric Code5
DONGLE 2.0: Direct FPGA-Orchestrated NVMe Storage for HLS5
Introduction to the Special Section on FCCM 20224
A Hardware Design Framework for Computer Vision Models Based on Reconfigurable Devices4
Introduction to Special Issue on FPGAs in Data Centers, Part II4
Data and Computation Reuse in CNNs Using Memristor TCAMs4
A Reconfigurable Architecture for Real-time Event-based Multi-Object Tracking4
Design Space Exploration of Galois and Fibonacci Configuration Based on Espresso Stream Cipher4
CSAIL2019 Crypto-Puzzle Solver Architecture4
FiberFlex: Real-time FPGA-based Intelligent and Distributed Fiber Sensor System for Pedestrian Recognition4
Compressing Neural Networks using Learnable 1D Non-Linear Functions4
LW-GCN: A Lightweight FPGA-based Graph Convolutional Network Accelerator4
Introduction to the Special Section on FPL 20204
Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis4
Codesign of Reactor-Oriented Hardware and Software for Cyber-Physical Systems4
VCSN: Virtual Circuit-Switching Network for Flexible and Simple-to-Operate Communication in HPC FPGA Cluster3
L-FNNG: Accelerating Large-Scale KNN Graph Construction on CPU-FPGA Heterogeneous Platform3
A Survey on Architectures, Hardware Acceleration and Challenges for In-Network Computing3
The Impact of Terrestrial Radiation on FPGAs in Data Centers3
Analytical Performance Estimation for Large-Scale Reconfigurable Dataflow Platforms3
Introduction to the Special Issue on FPGA-based Embedded Systems for Industrial and IoT Applications3
High Throughput FPGA-Based Object Detection via Algorithm-Hardware Co-Design3
Hipernetch: High-Performance FPGA Network Switch3
CHIRP: Compact and High-Performance FPGA Implementation of Unified Hardware Accelerators for Ring-Binary-LWE-based PQC3
Multi-Tenant Cloud FPGA: A Survey on Security, Trust, and Privacy3
Across Time and Space: Senju ’s Approach for Scaling Iterative Stencil Loop Accelerators on Single and Multiple FPGAs3
CGRA-EAM—Rapid Energy and Area Estimation for Coarse-grained Reconfigurable Architectures3
Scalable Phylogeny Reconstruction with Disaggregated Near-memory Processing3
NAPOLY: A Non-deterministic Automata Processor OverLaY3
Toward Software-like Debugging for FPGAs via Checkpointing and Transaction-based Co-Simulation3
TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design3
Canalis: A Throughput-Optimized Framework for Real-Time Stream Processing of Wireless Communication3
Voltage Sensor Implementations for Remote Power Attacks on FPGAs3
NeuroHSMD: Neuromorphic Hybrid Spiking Motion Detector3
Introduction to the Special Issue on FPT 20213
Algorithm-hardware Co-optimization for Energy-efficient Drone Detection on Resource-constrained FPGA3
Artifact Evaluation for ACM TRETS Papers Submitted from the FPT Journal Track3
SQL2FPGA: Automated Acceleration of SQL Query Processing on Modern CPU-FPGA Platforms3
Reconfigurable Framework for Resilient Semantic Segmentation for Space Applications2
A Computation of the Ninth Dedekind Number Using FPGA Supercomputing2
Elastic-DF: Scaling Performance of DNN Inference in FPGA Clouds through Automatic Partitioning2
Resource Sharing in Dataflow Circuits2
Fantastic Circuits and Where to Find Them—A Holistic ILP Formulation for Model-Based Hardware Design2
DFlows : A Flow-based Programming Approach for a Polyglot Design-Space Exploration Framework2
Designing Deep Learning Models on FPGA with Multiple Heterogeneous Engines2
BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining2
Near-memory Computing on FPGAs with 3D-stacked Memories: Applications, Architectures, and Optimizations2
Improving Fault Tolerance for FPGA SoCs through Post-Radiation Design Analysis2
Low-precision Floating-point Arithmetic for High-performance FPGA-based CNN Acceleration2
GraphScale: Scalable Processing on FPGAs for HBM and Large Graphs2
The Future of FPGA Acceleration in Datacenters and the Cloud2
Hardware-accelerated Real-time Drift-awareness for Robust Deep Learning on Wireless RF Data2
Introduction to the Special Issue on FPL 20222
Improving Loop Parallelization by a Combination of Static and Dynamic Analyses in HLS2
ADAS: A High Computational Utilization D ynamic Reconfigurable Hardware A ccelerator for S2
The Open-source DeLiBA2 Hardware/Software Framework for Distributed Storage Accelerators2
SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-specific LLVM Passes for Compute-Intensive FPGA Accelerators2
FPGA-based Acceleration of Time Series Similarity Prediction: From Cloud to Edge2
Introduction to Special Section on FPGA 20202
A BNN Accelerator Based on Edge-skip-calculation Strategy and Consolidation Compressed Tree2
Introduction to Special Section on FPGA 20212
An All-digital Compute-in-memory FPGA Architecture for Deep Learning Acceleration1
Design and Implementation of Hardware-Software Architecture Based on Hashes for SPHINCS+1
Practical Model Checking on FPGAs1
RapidStream 2.0: Automated Parallel Implementation of Latency–Insensitive FPGA Designs Through Partial Reconfiguration1
R-Blocks: an Energy-Efficient, Flexible, and Programmable CGRA1
Reprogrammable Non-Linear Circuits Using ReRAM for NN Accelerators1
Jitter-based Adaptive True Random Number Generation Circuits for FPGAs in the Cloud1
Dynamic-ACTS - A Dynamic Graph Analytics Accelerator For HBM-Enabled FPGAs1
Exploiting HBM on FPGAs for Data Processing1
AIgean : An Open Framework for Deploying Machine Learning on Heterogeneous Clusters1
An Optimized GIB Routing Architecture with Bent Wires for FPGA1
HyBNN: Quantifying and Optimizing Hardware Efficiency of Binary Neural Networks1
A Survey on FPGA Cybersecurity Design Strategies1
Leveraging Incremental Machine Learning for Reconfigurable Systems Modeling under Dynamic Workloads1
FPGA Accelerated Implementation of 3D Mesh Secret Sharing Based on Symmetric Similarity of Model1
CHIP-KNNv2: AConfigurable andHigh-PerformanceK-NearestNeighbors Accelerator on HBM-based FPGAs1
High-performance and Configurable SW/HW Co-design of Post-quantum Signature CRYSTALS-Dilithium1
An Efficient FPGA-based Depthwise Separable Convolutional Neural Network Accelerator with Hardware Pruning1
Hardware Optimizations of Fruit-80 Stream Cipher: Smaller than Grain1
PTME: A Regular Expression Matching Engine Based on Speculation and Enumerative Computation on FPGA1
DyRecMul: Fast and Low-Cost Approximate Multiplier for FPGAs using Dynamic Reconfiguration1
Evaluating the Impact of Using Multiple-Metal Layers on the Layout Area of Switch Blocks for Tile-Based FPGAs in FinFET 7nm1
High-efficiency TRNG Design Based on Multi-bit Dual-ring Oscillator1
Design and Analysis of Configurable Ring Oscillators for True Random Number Generation Based on Coherent Sampling1
FPGA-Accelerated Correspondence-free Point Cloud Registration with PointNet Features1
Design, Calibration, and Evaluation of Real-time Waveform Matching on an FPGA-based Digitizer at 10 GS/s1
RapidLayout: Fast Hard Block Placement of FPGA-optimized Systolic Arrays Using Evolutionary Algorithm1
Rock the QASBA : Q uantum Error Correction A cceleration via the S parse 1
PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs1
Approaches for FPGA Design Assurance1
A Survey of Processing Systems for Phylogenetics and Population Genetics1
Constraint-Aware Multi-Technique Approximate High-Level Synthesis for FPGAs1
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