ACM Transactions on Reconfigurable Technology and Systems

Papers
(The median citation count of ACM Transactions on Reconfigurable Technology and Systems is 2. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-06-01 to 2026-06-01.)
ArticleCitations
DF-BETA: An FPGA-based Memory Locality Aware Decision Forest Accelerator via Bit-Level Early Termination152
LHAM: Low-Cost and High-Accuracy Approximate Multiplier for FPGA-Based Computing62
HopliteML: Evolving Application Customized FPGA NoCs with Adaptable Routers and Regulators61
Tensor Slices: FPGA Building Blocks For The Deep Learning Era56
MCoreOPU: An FPGA-based Multi-Core Overlay Processor for Transformer-based Models43
FPGA-Based Sparse Matrix Multiplication Accelerators: From State-of-the-Art to Future Opportunities36
A Systematic Review of Fast, Scalable, and Efficient Hardware Implementations of Elliptic Curve Cryptography for Blockchain28
A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol and its Application28
Montgomery Multiplication Scalable Systolic Designs Optimized for DSP48E223
Eciton: Very Low-power Recurrent Neural Network Accelerator for Real-time Inference at the Edge22
RD-FAXID: Ransomware Detection with FPGA-Accelerated XGBoost22
High-Throughput TRNG Design with Novelty Adjustable TDC Based on STR20
FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs19
Accelerating In-memory Database Functionality with FPGAs19
FDRA: A Framework for a Dynamically Reconfigurable Accelerator Supporting Multi-Level Parallelism19
A Speculative Loop Pipeline Framework with Accurate Path Modeling for High-Level Synthesis18
A Partitioned CAM Architecture with FPGA Acceleration for Binary Descriptor Matching17
OpenDRAM: A Modular, High-performance Soft Memory Controller for DDR4 DRAM17
CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning Acceleration17
SPARTA: High-Level Synthesis of Parallel Multi-Threaded Accelerators17
Introduction to the Special Issue on RAW 202516
SIRA : Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators16
Cross-VM Covert- and Side-Channel Attacks in Cloud FPGAs15
Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-switched Inter-FPGA Networks15
Introduction to the Special Issue on RAW 202415
Efficient SpMM Accelerator for Deep Learning: Sparkle and Its Automated Generator14
ThunderGP: Resource-Efficient Graph Processing Framework on FPGAs with HLS13
HiFA: A High-Performance and Flexible Acceleration Framework for Large-Size Number Theoretic Transform12
Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains12
Composable Open Source Toolchain for Synthesizing Hardware Accelerators from OpenCL Command Buffers12
Adaptive Selection and Clustering of Partial Reconfiguration Modules for Modern FPGA Design Flow12
Breaking the Scalability Barrier of Content Addressable Memories: A Probabilistic Alternative for Large-Key Associative Search12
Streaming Overlay Architecture for Lightweight LSTM Computation on FPGA SoCs12
HLPerf: Demystifying the Performance of HLS-based Graph Neural Networks with Dataflow Architectures11
Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units11
hls4ml: A Flexible, Open Source Platform for Deep Learning Acceleration on Reconfigurable Hardware11
Highly Parallel Multi-FPGA System Compilation from Sequential C/C++ Code in the AWS Cloud10
Turn on, Tune in, and Listen up: Maximizing Side-Channel Recovery in Cross-Platform Time-to-Digital Converters10
CTScan: A CGRA-based Platform for the Emulation of Power Side-Channel Attacks on Edge CPUs9
End-to-end codesign of Hessian-aware quantized neural networks for FPGAs8
Accelerating Weather Prediction Using Near-Memory Reconfigurable Fabric8
da4ml: Distributed Arithmetic for Real-time Neural Networks on FPGAs8
High-efficiency Compressor Trees for Latest AMD FPGAs8
Strega : An HTTP Server for FPGAs8
MCT-TRNG: Multi-Channel Tetrahedral TRNG via Metastability-Enhanced Entropy with 2.2 Gbps Throughput8
SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs8
VERSATILE: Very Fast Partial Reconfiguration Controller8
Novel Security Threats in Multi-Tenant FPGAs: Phase Tuning for Voltage Sensors in Remote Power Side-Channel Analysis Attacks on AES8
Understanding the Potential of FPGA-based Spatial Acceleration for Large Language Model Inference8
AHCA: Agile Design Framework for Hashcat Acceleration Based on FPGA8
Covert-channels in FPGA-enabled SmartSSDs8
A Survey of FPGA Placement Algorithms: From Monolithic Devices to Multi-Die Architectures8
OmpSs@FPGA: An Open Source Framework for Programming FPGA Clusters8
An FPGA Accelerator for Genome Variant Calling8
QUEKUF : An FPGA Union Find Decoder for Quantum Error Correction on the Toric Code8
Exploring FPGA Switch-Blocks without Explicitly Listing Connectivity Patterns8
DONGLE 2.0: Direct FPGA-Orchestrated NVMe Storage for HLS7
Inducing Non-uniform FPGA Aging Using Configuration-based Short Circuits7
FPGA Implementation of Compact Hardware Accelerators for Ring-Binary-LWE-based Post-quantum Cryptography7
A Scalable Systolic Accelerator for Estimation of the Spectral Correlation Density Function and Its FPGA Implementation7
DANSEN: Database Acceleration on Native Computational Storage by Exploiting NDP7
An Energy-Efficient and Real-Time FPGA-Based Point Cloud Registration Framework with Ultra-Fast and Configurable Multi-Mode Correspondence Search7
cgra4ml : A Hardware/Software Framework to Implement Neural Networks for Scientific Edge Computing7
Accelerated Phylogenetics on the AMD Versal Adaptive SoC6
Design Space Exploration of Galois and Fibonacci Configuration Based on Espresso Stream Cipher6
Introduction to the Special Section on FCCM 20226
LW-GCN: A Lightweight FPGA-based Graph Convolutional Network Accelerator6
Compressing Neural Networks using Learnable 1D Non-Linear Functions6
A Hardware Design Framework for Computer Vision Models Based on Reconfigurable Devices6
A 950 MHz SIMT Soft Processor5
Introduction to the Special Section on FPL 20205
Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis5
Algorithm-hardware Co-optimization for Energy-efficient Drone Detection on Resource-constrained FPGA5
A Survey on Architectures, Hardware Acceleration and Challenges for In-Network Computing5
BitBlender: Scalable, High-Throughput Bloom Filter Acceleration on FPGAs with Dynamic Scheduling5
Across Time and Space: Senju ’s Approach for Scaling Iterative Stencil Loop Accelerators on Single and Multiple FPGAs5
FiberFlex: Real-time FPGA-based Intelligent and Distributed Fiber Sensor System for Pedestrian Recognition5
Editorial: A Message from the New Editor-in-Chief5
Introduction to the Special Issue on FPGA-based Embedded Systems for Industrial and IoT Applications5
High-Performance RISC-V CSR Access in FPGAs: Optimized Microarchitecture for Efficient Decoding and Multiplexing5
A Reconfigurable Architecture for Real-time Event-based Multi-Object Tracking5
Data and Computation Reuse in CNNs Using Memristor TCAMs5
CSAIL2019 Crypto-Puzzle Solver Architecture5
Codesign of Reactor-Oriented Hardware and Software for Cyber-Physical Systems5
Zero2M: Optimizing Tenant-Level I/O Management for Future Faster NVMe Storage with FPGA5
High Throughput FPGA-Based Object Detection via Algorithm-Hardware Co-Design4
CHIRP: Compact and High-Performance FPGA Implementation of Unified Hardware Accelerators for Ring-Binary-LWE-based PQC4
NeuroHSMD: Neuromorphic Hybrid Spiking Motion Detector4
Introduction to the Special Issue on FPT 20214
Artifact Evaluation for ACM TRETS Papers Submitted from the FPT Journal Track4
Canalis: A Throughput-Optimized Framework for Real-Time Stream Processing of Wireless Communication4
L-FNNG: Accelerating Large-Scale KNN Graph Construction on CPU-FPGA Heterogeneous Platform4
Exploring the Contribution of Hardware Shuffling in Securing Low-Cost Symmetric Encryption Devices against Power-Based Side-Channel Attacks: Case Study of an AES-128 on FPGA4
CD-LLM: A Heterogeneous Multi-FPGA System for Batched Decoding of 70B+ LLMs Using a Compute-Dedicated Architecture4
DA-VinCi: A Deep-Learning Accelerator Overlay Using In-Memory Computing4
Multi-Tenant Cloud FPGA: A Survey on Security, Trust, and Privacy4
Toward Software-like Debugging for FPGAs via Checkpointing and Transaction-based Co-Simulation4
Voltage Sensor Implementations for Remote Power Attacks on FPGAs4
NAPOLY: A Non-deterministic Automata Processor OverLaY4
A Configurable RISC-V Co-Processor with Instruction-Controlled Stream-Based Accelerators4
OpenFPGA-NoC: Automated Fabric and Bitstream Generation for NoC-based FPGAs4
SQL2FPGA: Automated Acceleration of SQL Query Processing on Modern CPU-FPGA Platforms3
REATA: An Efficient Vision Transformer Accelerator Featuring a Resource-Optimized Attention Design on Versal ACAP3
ADAS: A High Computational Utilization D ynamic Reconfigurable Hardware A ccelerator for S3
Near-memory Computing on FPGAs with 3D-stacked Memories: Applications, Architectures, and Optimizations3
TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design3
DGMF: A Unified Dynamic Mapping Framework for Graph Neural Networks3
The Open-source DeLiBA2 Hardware/Software Framework for Distributed Storage Accelerators3
A Computation of the Ninth Dedekind Number Using FPGA Supercomputing3
Improving Fault Tolerance for FPGA SoCs through Post-Radiation Design Analysis3
VCSN: Virtual Circuit-Switching Network for Flexible and Simple-to-Operate Communication in HPC FPGA Cluster3
Corrigendum: VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration3
SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-specific LLVM Passes for Compute-Intensive FPGA Accelerators3
GraphScale: Scalable Processing on FPGAs for HBM and Large Graphs3
Design, Calibration, and Evaluation of Real-time Waveform Matching on an FPGA-based Digitizer at 10 GS/s2
MAD-HiSpMV: Matrix Adaptive Design with Hybrid Row Distribution for Imbalanced SpMV Acceleration on FPGAs2
High-efficiency TRNG Design Based on Multi-bit Dual-ring Oscillator2
FPGA Accelerated Implementation of 3D Mesh Secret Sharing Based on Symmetric Similarity of Model2
Fantastic Circuits and Where to Find Them—A Holistic ILP Formulation for Model-Based Hardware Design2
Designing Deep Learning Models on FPGA with Multiple Heterogeneous Engines2
DFlows : A Flow-Based Programming Approach for a Polyglot Design-Space Exploration Framework2
BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining2
Leveraging Incremental Machine Learning for Reconfigurable Systems Modeling under Dynamic Workloads2
FPGA-based Acceleration of Time Series Similarity Prediction: From Cloud to Edge2
MetaML-Pro: Cross-Stage Design Flow Automation for Efficient Deep Learning Acceleration2
Hardware-accelerated Real-time Drift-awareness for Robust Deep Learning on Wireless RF Data2
Reprogrammable Non-Linear Circuits Using ReRAM for NN Accelerators2
RapidStream 2.0: Automated Parallel Implementation of Latency–Insensitive FPGA Designs Through Partial Reconfiguration2
FPGA-accelerated Correspondence-free Point Cloud Registration with PointNet Features2
Resource Sharing in Dataflow Circuits2
Introduction to the Special Issue on FPL 20222
Introduction to Special Section on FPGA 20212
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