ACM Transactions on Reconfigurable Technology and Systems

Papers
(The median citation count of ACM Transactions on Reconfigurable Technology and Systems is 1. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-04-01 to 2024-04-01.)
ArticleCitations
VTR 8156
FPGAD efender55
The Future of FPGA Acceleration in Datacenters and the Cloud51
FPGA HLS Today: Successes, Challenges, and Opportunities44
A Software/Hardware Co-Design of Crystals-Dilithium Signature Scheme20
FOS20
FPGA Logic Block Architectures for Efficient Deep Learning Inference19
Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future Prospects17
MEG16
Low-precision Floating-point Arithmetic for High-performance FPGA-based CNN Acceleration15
Mitigating Voltage Attacks in Multi-Tenant FPGAs13
Accelerating FPGA Routing Through Algorithmic Enhancements and Connection-aware Parallelization12
Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL Components10
Elastic-DF: Scaling Performance of DNN Inference in FPGA Clouds through Automatic Partitioning10
SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs9
FlexCNN: An End-to-end Framework for Composing CNN Accelerators on FPGA9
An Optimized GIB Routing Architecture with Bent Wires for FPGA9
Reconfigurable Framework for Environmentally Adaptive Resilience in Hybrid Space Systems9
Deploying Multi-tenant FPGAs within Linux-based Cloud Infrastructure8
NASCENT2: Generic Near-Storage Sort Accelerator for Data Analytics on SmartSSD8
LW-GCN: A Lightweight FPGA-based Graph Convolutional Network Accelerator8
RWRoute: An Open-source Timing-driven Router for Commercial FPGAs7
Optimizing OpenCL-Based CNN Design on FPGA with Comprehensive Design Space Exploration and Collaborative Performance Modeling7
Voltage Sensor Implementations for Remote Power Attacks on FPGAs7
Cross-VM Covert- and Side-Channel Attacks in Cloud FPGAs7
AIgean : An Open Framework for Deploying Machine Learning on Heterogeneous Clusters6
xDNN: Inference for Deep Convolutional Neural Networks6
ThunderGP: Resource-Efficient Graph Processing Framework on FPGAs with HLS6
Accelerating Weather Prediction Using Near-Memory Reconfigurable Fabric6
The Strong Scaling Advantage of FPGAs in HPC for N-body Simulations6
Near-memory Computing on FPGAs with 3D-stacked Memories: Applications, Architectures, and Optimizations6
Tensor Slices: FPGA Building Blocks For The Deep Learning Era6
Design of Distributed Reconfigurable Robotics Systems with ReconROS5
UNILOGIC5
BlastFunction: A Full-stack Framework Bringing FPGA Hardware Acceleration to Cloud-native Applications5
AutoScaleDSE: A Scalable Design Space Exploration Engine for High-Level Synthesis5
A Deep Learning Framework to Predict Routability for FPGA Circuit Placement5
Substream-Centric Maximum Matchings on FPGA5
Process Variability Analysis in Interconnect, Logic, and Arithmetic Blocks of 16-nm FinFET FPGAs4
Enhancing the Security of FPGA-SoCs via the Usage of ARM TrustZone and a Hybrid-TPM4
High-performance and Configurable SW/HW Co-design of Post-quantum Signature CRYSTALS-Dilithium4
A Survey on FPGA Cybersecurity Design Strategies4
CGRA-EAM—Rapid Energy and Area Estimation for Coarse-grained Reconfigurable Architectures4
Model-based Design of Hardware SC Polar Decoders for FPGAs4
Parallel Unary Computing Based on Function Derivatives4
An OpenGL Compliant Hardware Implementation of a Graphic Processing Unit Using Field Programmable Gate Array–System on Chip Technology4
Specializing FGPU for Persistent Deep Learning4
Jitter-based Adaptive True Random Number Generation Circuits for FPGAs in the Cloud4
Stratix 10 NX Architecture4
Partitioning and Scheduling with Module Merging on Dynamic Partial Reconfigurable FPGAs4
SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs3
Automatic Creation of High-bandwidth Memory Architectures from Domain-specific Languages: The Case of Computational Fluid Dynamics3
RapidLayout: Fast Hard Block Placement of FPGA-optimized Systolic Arrays Using Evolutionary Algorithm3
Design and Analysis of Configurable Ring Oscillators for True Random Number Generation Based on Coherent Sampling3
BurstZ+: Eliminating The Communication Bottleneck of Scientific Computing Accelerators via Accelerated Compression3
A Unified FPGA Virtualization Framework for General-Purpose Deep Neural Networks in the Cloud3
Approaches for FPGA Design Assurance3
A BNN Accelerator Based on Edge-skip-calculation Strategy and Consolidation Compressed Tree3
ACE-GCN: A Fast Data-driven FPGA Accelerator for GCN Embedding3
When Massive GPU Parallelism Ain’t Enough: A Novel Hardware Architecture of 2D-LSTM Neural Network3
TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design3
A Scalable Many-core Overlay Architecture on an HBM2-enabled Multi-Die FPGA3
The Impact of Terrestrial Radiation on FPGAs in Data Centers3
FPGA Architecture Exploration for DNN Acceleration3
FPGA Implementation of Compact Hardware Accelerators for Ring-Binary-LWE-based Post-quantum Cryptography3
Hipernetch: High-Performance FPGA Network Switch3
RapidStream 2.0: Automated Parallel Implementation of Latency–Insensitive FPGA Designs Through Partial Reconfiguration3
Exploiting HBM on FPGAs for Data Processing2
ADAS: A High Computational Utilization D ynamic Reconfigurable Hardware A ccelerator for S2
A Reconfigurable Architecture for Real-time Event-based Multi-Object Tracking2
A Scalable Systolic Accelerator for Estimation of the Spectral Correlation Density Function and Its FPGA Implementation2
Inducing Non-uniform FPGA Aging Using Configuration-based Short Circuits2
ZyPR: End-to-end Build Tool and Runtime Manager for Partial Reconfiguration of FPGA SoCs at the Edge2
Cloud Building Block Chip for Creating FPGA and ASIC Clouds2
Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains2
Processing Grid-format Real-world Graphs on DRAM-based FPGA Accelerators with Application-specific Caching Mechanisms2
FPGA Acceleration of Probabilistic Sentential Decision Diagrams with High-level Synthesis2
FPGA-based Deep Learning Inference Accelerators: Where Are We Standing?2
Approximate Constant-Coefficient Multiplication Using Hybrid Binary-Unary Computing for FPGAs2
A Real-Time Deep Learning OFDM Receiver2
Hardware Optimizations of Fruit-80 Stream Cipher: Smaller than Grain2
An Empirical Approach to Enhance Performance for Scalable CORDIC-Based Deep Neural Networks2
CoNFV2
VCSN: Virtual Circuit-Switching Network for Flexible and Simple-to-Operate Communication in HPC FPGA Cluster2
A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol and its Application2
Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units2
Fixed-point FPGA Implementation of the FFT Accumulation Method for Real-time Cyclostationary Analysis1
Hardware Context Switch-based Cryptographic Accelerator for Handling Multiple Streams1
Scalable Phylogeny Reconstruction with Disaggregated Near-memory Processing1
BISWSRBS: A Winograd-based CNN Accelerator with a Fine-grained Regular Sparsity Pattern and Mixed Precision Quantization1
Across Time and Space: Senju ’s Approach for Scaling Iterative Stencil Loop Accelerators on Single and Multiple FPGAs1
Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-switched Inter-FPGA Networks1
Data and Computation Reuse in CNNs Using Memristor TCAMs1
CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning Acceleration1
Hardware Acceleration of High-Performance Computational Flow Dynamics Using High-Bandwidth Memory-Enabled Field-Programmable Gate Arrays1
Buffer Placement and Sizing for High-Performance Dataflow Circuits1
Toward Software-like Debugging for FPGAs via Checkpointing and Transaction-based Co-Simulation1
Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs1
Parallelising Control Flow in Dynamic-scheduling High-level Synthesis1
Resource Sharing in Dataflow Circuits1
fSEAD: A Composable FPGA-based Streaming Ensemble Anomaly Detection Library1
Deterministic Approach for Range-enhanced Reconfigurable Packet Classification Engine1
Reconfigurable Framework for Resilient Semantic Segmentation for Space Applications1
Introduction to Special Issue on FPGAs in Data Centers, Part II1
A Hardware Accelerator for the Semi-Global Matching Stereo Algorithm: An Efficient Implementation for the Stratix V and Zynq UltraScale+ FPGA Technology1
High-efficiency TRNG Design Based on Multi-bit Dual-ring Oscillator1
Large-scale Cellular Automata on FPGAs1
CHIP-KNNv2: A C onfigurable and Hi gh- P erformance K - N1
Tailor : Altering Skip Connections for Resource-Efficient Inference1
Detailed Placement for Dedicated LUT-Level FPGA Interconnect1
FPGA-based Acceleration of Time Series Similarity Prediction: From Cloud to Edge1
Streaming Overlay Architecture for Lightweight LSTM Computation on FPGA SoCs1
Programmable Analog System Benchmarks Leading to Efficient Analog Computation Synthesis1
Demystifying the Soft and Hardened Memory Systems of Modern FPGAs for Software Programmers through Microbenchmarking1
Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis1
Introduction to the Special Section on FCCM 20221
Topgun: An ECC Accelerator for Private Set Intersection1
Introduction to Special Issue on FPGAs in Data Centers1
BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining1
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