OOIR: Observatory of International Research

Papers

(The median citation count of ACM Transactions on Reconfigurable Technology and Systems is 2. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-05-01 to 2026-05-01.)

Article	Citations
DF-BETA: An FPGA-based Memory Locality Aware Decision Forest Accelerator via Bit-Level Early Termination	152
LHAM: Low-Cost and High-Accuracy Approximate Multiplier for FPGA-Based Computing	61
HopliteML: Evolving Application Customized FPGA NoCs with Adaptable Routers and Regulators	60
A Systematic Review of Fast, Scalable, and Efficient Hardware Implementations of Elliptic Curve Cryptography for Blockchain	56
Tensor Slices: FPGA Building Blocks For The Deep Learning Era	41
MCoreOPU: An FPGA-based Multi-Core Overlay Processor for Transformer-based Models	36
FPGA-Based Sparse Matrix Multiplication Accelerators: From State-of-the-Art to Future Opportunities	28
Eciton: Very Low-power Recurrent Neural Network Accelerator for Real-time Inference at the Edge	27
A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol and its Application	21
FDRA: A Framework for a Dynamically Reconfigurable Accelerator Supporting Multi-Level Parallelism	21
RD-FAXID: Ransomware Detection with FPGA-Accelerated XGBoost	21
Montgomery Multiplication Scalable Systolic Designs Optimized for DSP48E2	20
Accelerating In-memory Database Functionality with FPGAs	19
High-Throughput TRNG Design with Novelty Adjustable TDC Based on STR	19
FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs	18
SPARTA: High-Level Synthesis of Parallel Multi-Threaded Accelerators	17
A Speculative Loop Pipeline Framework with Accurate Path Modeling for High-Level Synthesis	17
A Partitioned CAM Architecture with FPGA Acceleration for Binary Descriptor Matching	17
OpenDRAM: A Modular, High-performance Soft Memory Controller for DDR4 DRAM	17
CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning Acceleration	16
SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators	16
Composable Open-Source Toolchain for Synthesizing Hardware Accelerators from OpenCL Command Buffers	16
Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-switched Inter-FPGA Networks	15
Introduction to the Special Issue on RAW 2024	15
Efficient SpMM Accelerator for Deep Learning: Sparkle and Its Automated Generator	14

Cross-VM Covert- and Side-Channel Attacks in Cloud FPGAs	14
Adaptive Selection and Clustering of Partial Reconfiguration Modules for Modern FPGA Design Flow	12
hls4ml: A Flexible, Open-Source Platform for Deep Learning Acceleration on Reconfigurable Hardware	12
Breaking the Scalability Barrier of Content Addressable Memories: A Probabilistic Alternative for Large-Key Associative Search	12
HiFA: A High-Performance and Flexible Acceleration Framework for Large-Size Number Theoretic Transform	12
ThunderGP: Resource-Efficient Graph Processing Framework on FPGAs with HLS	12
Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains	12
Highly Parallel Multi-FPGA System Compilation from Sequential C/C++ Code in the AWS Cloud	11
Streaming Overlay Architecture for Lightweight LSTM Computation on FPGA SoCs	11
Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units	11
HLPerf: Demystifying the Performance of HLS-based Graph Neural Networks with Dataflow Architectures	11
Turn on, Tune in, and Listen up: Maximizing Side-Channel Recovery in Cross-Platform Time-to-Digital Converters	10
SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs	10
CTScan: A CGRA-based Platform for the Emulation of Power Side-Channel Attacks on Edge CPUs	10
MCT-TRNG: Multi-Channel Tetrahedral TRNG via Metastability-Enhanced Entropy with 2.2 Gbps Throughput	9
A Survey of FPGA Placement Algorithms: From Monolithic Devices to Multi-Die Architectures	8
Exploring FPGA Switch-Blocks without Explicitly Listing Connectivity Patterns	8
An FPGA Accelerator for Genome Variant Calling	8
`QUEKUF` : An FPGA Union Find Decoder for Quantum Error Correction on the Toric Code	8
AHCA: Agile Design Framework for Hashcat Acceleration Based on FPGA	8
High-efficiency Compressor Trees for Latest AMD FPGAs	8
da4ml: Distributed Arithmetic for Real-time Neural Networks on FPGAs	8
End-to-end codesign of Hessian-aware quantized neural networks for FPGAs	8
OmpSs@FPGA: An Open Source Framework for Programming FPGA Clusters	8
Accelerating Weather Prediction Using Near-Memory Reconfigurable Fabric	8
Strega : An HTTP Server for FPGAs	8
An Energy-Efficient and Real-Time FPGA-Based Point Cloud Registration Framework with Ultra-Fast and Configurable Multi-Mode Correspondence Search	8
Covert-channels in FPGA-enabled SmartSSDs	8
VERSATILE: Very Fast Partial Reconfiguration Controller	8
Novel Security Threats in Multi-Tenant FPGAs: Phase Tuning for Voltage Sensors in Remote Power Side-Channel Analysis Attacks on AES	8
Understanding the Potential of FPGA-based Spatial Acceleration for Large Language Model Inference	8
FPGA Implementation of Compact Hardware Accelerators for Ring-Binary-LWE-based Post-quantum Cryptography	8
A Scalable Systolic Accelerator for Estimation of the Spectral Correlation Density Function and Its FPGA Implementation	8
DANSEN: Database Acceleration on Native Computational Storage by Exploiting NDP	7
Accelerated Phylogenetics on the AMD Versal Adaptive SoC	7
CGRA4ML : A Hardware/Software Framework to Implement Neural Networks for Scientific Edge Computing	7
DONGLE 2.0: Direct FPGA-Orchestrated NVMe Storage for HLS	7
Inducing Non-uniform FPGA Aging Using Configuration-based Short Circuits	7
Introduction to the Special Section on FCCM 2022	7
A Reconfigurable Architecture for Real-time Event-based Multi-Object Tracking	6
Compressing Neural Networks using Learnable 1D Non-Linear Functions	6
Design Space Exploration of Galois and Fibonacci Configuration Based on Espresso Stream Cipher	6
LW-GCN: A Lightweight FPGA-based Graph Convolutional Network Accelerator	6
A Hardware Design Framework for Computer Vision Models Based on Reconfigurable Devices	6
Zero2M: Optimizing Tenant-Level I/O Management for Future Faster NVMe Storage with FPGA	5
Data and Computation Reuse in CNNs Using Memristor TCAMs	5
FiberFlex: Real-time FPGA-based Intelligent and Distributed Fiber Sensor System for Pedestrian Recognition	5
Editorial: A Message from the New Editor-in-Chief	5
Introduction to the Special Issue on FPGA-based Embedded Systems for Industrial and IoT Applications	5
Across Time and Space: Senju ’s Approach for Scaling Iterative Stencil Loop Accelerators on Single and Multiple FPGAs	5

Introduction to the Special Section on FPL 2020	5
CSAIL2019 Crypto-Puzzle Solver Architecture	5
High-Performance RISC-V CSR Access in FPGAs: Optimized Microarchitecture for Efficient Decoding and Multiplexing	5
NeuroHSMD: Neuromorphic Hybrid Spiking Motion Detector	5
Introduction to Special Issue on FPGAs in Data Centers, Part II	5
Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis	5
Codesign of Reactor-Oriented Hardware and Software for Cyber-Physical Systems	5
Algorithm-hardware Co-optimization for Energy-efficient Drone Detection on Resource-constrained FPGA	5
Exploring the Contribution of Hardware Shuffling in Securing Low-Cost Symmetric Encryption Devices against Power-Based Side-Channel Attacks: Case Study of an AES-128 on FPGA	4
Toward Software-like Debugging for FPGAs via Checkpointing and Transaction-based Co-Simulation	4
DA-VinCi: A Deep-Learning Accelerator Overlay Using In-Memory Computing	4
OpenFPGA-NoC: Automated Fabric and Bitstream Generation for NoC-based FPGAs	4
Artifact Evaluation for ACM TRETS Papers Submitted from the FPT Journal Track	4
Voltage Sensor Implementations for Remote Power Attacks on FPGAs	4
NAPOLY: A Non-deterministic Automata Processor OverLaY	4
L-FNNG: Accelerating Large-Scale KNN Graph Construction on CPU-FPGA Heterogeneous Platform	4
CD-LLM: A Heterogeneous Multi-FPGA System for Batched Decoding of 70B+ LLMs Using a Compute-Dedicated Architecture	4
CHIRP: Compact and High-Performance FPGA Implementation of Unified Hardware Accelerators for Ring-Binary-LWE-based PQC	4
Multi-Tenant Cloud FPGA: A Survey on Security, Trust, and Privacy	4
A Survey on Architectures, Hardware Acceleration and Challenges for In-Network Computing	4
Introduction to the Special Issue on FPT 2021	4
Canalis: A Throughput-Optimized Framework for Real-Time Stream Processing of Wireless Communication	4
High Throughput FPGA-Based Object Detection via Algorithm-Hardware Co-Design	4
SQL2FPGA: Automated Acceleration of SQL Query Processing on Modern CPU-FPGA Platforms	3
REATA: An Efficient Vision Transformer Accelerator Featuring a Resource-Optimized Attention Design on Versal ACAP	3
SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-specific LLVM Passes for Compute-Intensive FPGA Accelerators	3
Near-memory Computing on FPGAs with 3D-stacked Memories: Applications, Architectures, and Optimizations	3
The Open-source DeLiBA2 Hardware/Software Framework for Distributed Storage Accelerators	3
TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design	3
DGMF: A Unified Dynamic Mapping Framework for Graph Neural Networks	3
Improving Fault Tolerance for FPGA SoCs through Post-Radiation Design Analysis	3
ADAS: A High Computational Utilization D ynamic Reconfigurable Hardware A ccelerator for S	3
FPGA-based Acceleration of Time Series Similarity Prediction: From Cloud to Edge	3
VCSN: Virtual Circuit-Switching Network for Flexible and Simple-to-Operate Communication in HPC FPGA Cluster	3
Corrigendum: VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration	3
A Computation of the Ninth Dedekind Number Using FPGA Supercomputing	3
GraphScale: Scalable Processing on FPGAs for HBM and Large Graphs	3
MetaML-Pro: Cross-Stage Design Flow Automation for Efficient Deep Learning Acceleration	3
Introduction to Special Section on FPGA 2021	2
Fantastic Circuits and Where to Find Them—A Holistic ILP Formulation for Model-Based Hardware Design	2
Hardware-accelerated Real-time Drift-awareness for Robust Deep Learning on Wireless RF Data	2
Designing Deep Learning Models on FPGA with Multiple Heterogeneous Engines	2
MAD-HiSpMV: Matrix Adaptive Design with Hybrid Row Distribution for Imbalanced SpMV Acceleration on FPGAs	2
CHIP-KNNv2: AConfigurable andHigh-PerformanceK-NearestNeighbors Accelerator on HBM-based FPGAs	2
Resource Sharing in Dataflow Circuits	2
Introduction to the Special Issue on FPL 2022	2
FPGA Accelerated Implementation of 3D Mesh Secret Sharing Based on Symmetric Similarity of Model	2
BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining	2
Leveraging Incremental Machine Learning for Reconfigurable Systems Modeling under Dynamic Workloads	2
ISRLUT: Integer-Only FHD Image Super-Resolution Based on Neural Lookup Table and Near-Memory Computing	2
A BNN Accelerator Based on Edge-skip-calculation Strategy and Consolidation Compressed Tree	2
`DFlows` : A Flow-Based Programming Approach for a Polyglot Design-Space Exploration Framework	2
Design, Calibration, and Evaluation of Real-time Waveform Matching on an FPGA-based Digitizer at 10 GS/s	2
RapidStream 2.0: Automated Parallel Implementation of Latency–Insensitive FPGA Designs Through Partial Reconfiguration	2
FPGA-accelerated Correspondence-free Point Cloud Registration with PointNet Features	2
Reprogrammable Non-Linear Circuits Using ReRAM for NN Accelerators	2