ACM Transactions on Reconfigurable Technology and Systems

Papers
(The median citation count of ACM Transactions on Reconfigurable Technology and Systems is 1. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-07-01 to 2024-07-01.)
ArticleCitations
FPGAD efender61
The Future of FPGA Acceleration in Datacenters and the Cloud57
FPGA HLS Today: Successes, Challenges, and Opportunities50
A Software/Hardware Co-Design of Crystals-Dilithium Signature Scheme25
FOS20
Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future Prospects18
Low-precision Floating-point Arithmetic for High-performance FPGA-based CNN Acceleration16
MEG16
Mitigating Voltage Attacks in Multi-Tenant FPGAs14
Accelerating FPGA Routing Through Algorithmic Enhancements and Connection-aware Parallelization13
SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs12
FlexCNN: An End-to-end Framework for Composing CNN Accelerators on FPGA11
Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL Components11
Elastic-DF: Scaling Performance of DNN Inference in FPGA Clouds through Automatic Partitioning10
An Optimized GIB Routing Architecture with Bent Wires for FPGA10
Reconfigurable Framework for Environmentally Adaptive Resilience in Hybrid Space Systems10
LW-GCN: A Lightweight FPGA-based Graph Convolutional Network Accelerator10
Voltage Sensor Implementations for Remote Power Attacks on FPGAs9
NASCENT2: Generic Near-Storage Sort Accelerator for Data Analytics on SmartSSD8
Cross-VM Covert- and Side-Channel Attacks in Cloud FPGAs8
Deploying Multi-tenant FPGAs within Linux-based Cloud Infrastructure8
RWRoute: An Open-source Timing-driven Router for Commercial FPGAs7
AIgean : An Open Framework for Deploying Machine Learning on Heterogeneous Clusters7
The Strong Scaling Advantage of FPGAs in HPC for N-body Simulations7
BlastFunction: A Full-stack Framework Bringing FPGA Hardware Acceleration to Cloud-native Applications7
Design of Distributed Reconfigurable Robotics Systems with ReconROS7
Near-memory Computing on FPGAs with 3D-stacked Memories: Applications, Architectures, and Optimizations7
FPGA-based Deep Learning Inference Accelerators: Where Are We Standing?6
Accelerating Weather Prediction Using Near-Memory Reconfigurable Fabric6
High-performance and Configurable SW/HW Co-design of Post-quantum Signature CRYSTALS-Dilithium6
xDNN: Inference for Deep Convolutional Neural Networks6
Tensor Slices: FPGA Building Blocks For The Deep Learning Era6
ThunderGP: Resource-Efficient Graph Processing Framework on FPGAs with HLS6
AutoScaleDSE: A Scalable Design Space Exploration Engine for High-Level Synthesis6
A Deep Learning Framework to Predict Routability for FPGA Circuit Placement5
A Survey on FPGA Cybersecurity Design Strategies5
RapidStream 2.0: Automated Parallel Implementation of Latency–Insensitive FPGA Designs Through Partial Reconfiguration5
CGRA-EAM—Rapid Energy and Area Estimation for Coarse-grained Reconfigurable Architectures5
UNILOGIC5
Enhancing the Security of FPGA-SoCs via the Usage of ARM TrustZone and a Hybrid-TPM5
FPGA Implementation of Compact Hardware Accelerators for Ring-Binary-LWE-based Post-quantum Cryptography5
Process Variability Analysis in Interconnect, Logic, and Arithmetic Blocks of 16-nm FinFET FPGAs4
Approaches for FPGA Design Assurance4
Stratix 10 NX Architecture4
ACE-GCN: A Fast Data-driven FPGA Accelerator for GCN Embedding4
A Scalable Many-core Overlay Architecture on an HBM2-enabled Multi-Die FPGA4
The Impact of Terrestrial Radiation on FPGAs in Data Centers4
A BNN Accelerator Based on Edge-skip-calculation Strategy and Consolidation Compressed Tree4
FPGA Architecture Exploration for DNN Acceleration4
BurstZ+: Eliminating The Communication Bottleneck of Scientific Computing Accelerators via Accelerated Compression4
Specializing FGPU for Persistent Deep Learning4
Jitter-based Adaptive True Random Number Generation Circuits for FPGAs in the Cloud4
An Empirical Approach to Enhance Performance for Scalable CORDIC-Based Deep Neural Networks4
Parallel Unary Computing Based on Function Derivatives4
An OpenGL Compliant Hardware Implementation of a Graphic Processing Unit Using Field Programmable Gate Array–System on Chip Technology4
Design and Analysis of Configurable Ring Oscillators for True Random Number Generation Based on Coherent Sampling3
A Unified FPGA Virtualization Framework for General-Purpose Deep Neural Networks in the Cloud3
SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs3
Hardware Optimizations of Fruit-80 Stream Cipher: Smaller than Grain3
A Reconfigurable Architecture for Real-time Event-based Multi-Object Tracking3
High-efficiency TRNG Design Based on Multi-bit Dual-ring Oscillator3
Hipernetch: High-Performance FPGA Network Switch3
ZyPR: End-to-end Build Tool and Runtime Manager for Partial Reconfiguration of FPGA SoCs at the Edge3
Exploiting HBM on FPGAs for Data Processing3
ADAS: A High Computational Utilization D ynamic Reconfigurable Hardware A ccelerator for S3
Partitioning and Scheduling with Module Merging on Dynamic Partial Reconfigurable FPGAs3
When Massive GPU Parallelism Ain’t Enough: A Novel Hardware Architecture of 2D-LSTM Neural Network3
TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design3
A Real-Time Deep Learning OFDM Receiver3
Automatic Creation of High-bandwidth Memory Architectures from Domain-specific Languages: The Case of Computational Fluid Dynamics3
CoNFV3
RapidLayout: Fast Hard Block Placement of FPGA-optimized Systolic Arrays Using Evolutionary Algorithm3
Cloud Building Block Chip for Creating FPGA and ASIC Clouds2
Stream Aggregation with Compressed Sliding Windows2
Design Space Exploration of Galois and Fibonacci Configuration Based on Espresso Stream Cipher2
A Scalable Systolic Accelerator for Estimation of the Spectral Correlation Density Function and Its FPGA Implementation2
Approximate Constant-Coefficient Multiplication Using Hybrid Binary-Unary Computing for FPGAs2
End-to-end codesign of Hessian-aware quantized neural networks for FPGAs2
An Efficient FPGA-based Depthwise Separable Convolutional Neural Network Accelerator with Hardware Pruning2
Programmable Analog System Benchmarks Leading to Efficient Analog Computation Synthesis2
FPGA Acceleration of Probabilistic Sentential Decision Diagrams with High-level Synthesis2
A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol and its Application2
Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units2
Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains2
Demystifying the Soft and Hardened Memory Systems of Modern FPGAs for Software Programmers through Microbenchmarking2
VCSN: Virtual Circuit-Switching Network for Flexible and Simple-to-Operate Communication in HPC FPGA Cluster2
Inducing Non-uniform FPGA Aging Using Configuration-based Short Circuits2
ScalaBFS2: A High-performance BFS Accelerator on an HBM-enhanced FPGA Chip1
Large-scale Cellular Automata on FPGAs1
CHIP-KNNv2: A C onfigurable and Hi gh- P erformance K - N1
Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs1
Toward Software-like Debugging for FPGAs via Checkpointing and Transaction-based Co-Simulation1
Tailor : Altering Skip Connections for Resource-Efficient Inference1
Scalable Phylogeny Reconstruction with Disaggregated Near-memory Processing1
Resource Sharing in Dataflow Circuits1
Streaming Overlay Architecture for Lightweight LSTM Computation on FPGA SoCs1
Introduction to Special Issue on FPGAs in Data Centers, Part II1
Data and Computation Reuse in CNNs Using Memristor TCAMs1
Hardware Acceleration of High-Performance Computational Flow Dynamics Using High-Bandwidth Memory-Enabled Field-Programmable Gate Arrays1
A Hardware Accelerator for the Semi-Global Matching Stereo Algorithm: An Efficient Implementation for the Stratix V and Zynq UltraScale+ FPGA Technology1
Topgun: An ECC Accelerator for Private Set Intersection1
Understanding the Potential of FPGA-Based Spatial Acceleration for Large Language Model Inference1
Turn on, Tune in, Listen up: Maximizing Side-Channel Recovery in Cross-Platform Time-to-Digital Converters1
Hardware Context Switch-based Cryptographic Accelerator for Handling Multiple Streams1
HLPerf: Demystifying the Performance of HLS-based Graph Neural Networks with Dataflow Architectures1
FPGA-based Acceleration of Time Series Similarity Prediction: From Cloud to Edge1
Algorithm-hardware Co-optimization for Energy-efficient Drone Detection on Resource-constrained FPGA1
Deterministic Approach for Range-enhanced Reconfigurable Packet Classification Engine1
Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-switched Inter-FPGA Networks1
CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning Acceleration1
Design and implementation of hardware-software architecture based on hashes for SPHINCS+1
Buffer Placement and Sizing for High-Performance Dataflow Circuits1
Parallelising Control Flow in Dynamic-scheduling High-level Synthesis1
BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining1
Fixed-point FPGA Implementation of the FFT Accumulation Method for Real-time Cyclostationary Analysis1
Detailed Placement for Dedicated LUT-Level FPGA Interconnect1
fSEAD: A Composable FPGA-based Streaming Ensemble Anomaly Detection Library1
BISWSRBS: A Winograd-based CNN Accelerator with a Fine-grained Regular Sparsity Pattern and Mixed Precision Quantization1
Across Time and Space: Senju ’s Approach for Scaling Iterative Stencil Loop Accelerators on Single and Multiple FPGAs1
Reconfigurable Framework for Resilient Semantic Segmentation for Space Applications1
Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis1
Introduction to the Special Section on FCCM 20221
0.035636901855469