OOIR: Observatory of International Research

Papers

(The median citation count of ACM Transactions on Reconfigurable Technology and Systems is 1. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-11-01 to 2024-11-01.)

Article	Citations
The Future of FPGA Acceleration in Datacenters and the Cloud	63
FPGA HLS Today: Successes, Challenges, and Opportunities	60
A Software/Hardware Co-Design of Crystals-Dilithium Signature Scheme	26
Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future Prospects	20
Low-precision Floating-point Arithmetic for High-performance FPGA-based CNN Acceleration	19
SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs	16
FlexCNN: An End-to-end Framework for Composing CNN Accelerators on FPGA	15
NASCENT2: Generic Near-Storage Sort Accelerator for Data Analytics on SmartSSD	14
LW-GCN: A Lightweight FPGA-based Graph Convolutional Network Accelerator	14
Mitigating Voltage Attacks in Multi-Tenant FPGAs	14
An Optimized GIB Routing Architecture with Bent Wires for FPGA	13
Elastic-DF: Scaling Performance of DNN Inference in FPGA Clouds through Automatic Partitioning	12
Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL Components	11
Voltage Sensor Implementations for Remote Power Attacks on FPGAs	11
Deploying Multi-tenant FPGAs within Linux-based Cloud Infrastructure	11
RWRoute: An Open-source Timing-driven Router for Commercial FPGAs	10
Cross-VM Covert- and Side-Channel Attacks in Cloud FPGAs	9
ThunderGP: Resource-Efficient Graph Processing Framework on FPGAs with HLS	9
Near-memory Computing on FPGAs with 3D-stacked Memories: Applications, Architectures, and Optimizations	9
The Strong Scaling Advantage of FPGAs in HPC for N-body Simulations	8
FPGA-based Deep Learning Inference Accelerators: Where Are We Standing?	8
BlastFunction: A Full-stack Framework Bringing FPGA Hardware Acceleration to Cloud-native Applications	7
A Survey on FPGA Cybersecurity Design Strategies	7
Tensor Slices: FPGA Building Blocks For The Deep Learning Era	7
Design of Distributed Reconfigurable Robotics Systems with ReconROS	7

FPGA Implementation of Compact Hardware Accelerators for Ring-Binary-LWE-based Post-quantum Cryptography	7
AIgean : An Open Framework for Deploying Machine Learning on Heterogeneous Clusters	7
Accelerating Weather Prediction Using Near-Memory Reconfigurable Fabric	7
CGRA-EAM—Rapid Energy and Area Estimation for Coarse-grained Reconfigurable Architectures	6
High-performance and Configurable SW/HW Co-design of Post-quantum Signature CRYSTALS-Dilithium	6
AutoScaleDSE: A Scalable Design Space Exploration Engine for High-Level Synthesis	6
A Deep Learning Framework to Predict Routability for FPGA Circuit Placement	5
Enhancing the Security of FPGA-SoCs via the Usage of ARM TrustZone and a Hybrid-TPM	5
FPGA Architecture Exploration for DNN Acceleration	5
TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design	5
Process Variability Analysis in Interconnect, Logic, and Arithmetic Blocks of 16-nm FinFET FPGAs	5
Jitter-based Adaptive True Random Number Generation Circuits for FPGAs in the Cloud	5
ACE-GCN: A Fast Data-driven FPGA Accelerator for GCN Embedding	5
RapidStream 2.0: Automated Parallel Implementation of Latency–Insensitive FPGA Designs Through Partial Reconfiguration	5
A Scalable Many-core Overlay Architecture on an HBM2-enabled Multi-Die FPGA	5
Automatic Creation of High-bandwidth Memory Architectures from Domain-specific Languages: The Case of Computational Fluid Dynamics	5
Stratix 10 NX Architecture	5
xDNN: Inference for Deep Convolutional Neural Networks	5
Approaches for FPGA Design Assurance	4
An Empirical Approach to Enhance Performance for Scalable CORDIC-Based Deep Neural Networks	4
Specializing FGPU for Persistent Deep Learning	4
A BNN Accelerator Based on Edge-skip-calculation Strategy and Consolidation Compressed Tree	4
BurstZ+: Eliminating The Communication Bottleneck of Scientific Computing Accelerators via Accelerated Compression	4
The Impact of Terrestrial Radiation on FPGAs in Data Centers	4
ADAS: A High Computational Utilization D ynamic Reconfigurable Hardware A ccelerator for S	4
Exploiting HBM on FPGAs for Data Processing	3
CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning Acceleration	3
CHIP-KNNv2: AConfigurable andHigh-PerformanceK-NearestNeighbors Accelerator on HBM-based FPGAs	3
Design and Analysis of Configurable Ring Oscillators for True Random Number Generation Based on Coherent Sampling	3
A Unified FPGA Virtualization Framework for General-Purpose Deep Neural Networks in the Cloud	3
ZyPR: End-to-end Build Tool and Runtime Manager for Partial Reconfiguration of FPGA SoCs at the Edge	3
Hardware Optimizations of Fruit-80 Stream Cipher: Smaller than Grain	3
Demystifying the Soft and Hardened Memory Systems of Modern FPGAs for Software Programmers through Microbenchmarking	3
RapidLayout: Fast Hard Block Placement of FPGA-optimized Systolic Arrays Using Evolutionary Algorithm	3
High-efficiency TRNG Design Based on Multi-bit Dual-ring Oscillator	3
When Massive GPU Parallelism Ain’t Enough: A Novel Hardware Architecture of 2D-LSTM Neural Network	3
A Real-Time Deep Learning OFDM Receiver	3
Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains	3
Algorithm-hardware Co-optimization for Energy-efficient Drone Detection on Resource-constrained FPGA	3
A Reconfigurable Architecture for Real-time Event-based Multi-Object Tracking	3
Hipernetch: High-Performance FPGA Network Switch	3
Approximate Constant-Coefficient Multiplication Using Hybrid Binary-Unary Computing for FPGAs	3
SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs	3
Detailed Placement for Dedicated LUT-Level FPGA Interconnect	2
Streaming Overlay Architecture for Lightweight LSTM Computation on FPGA SoCs	2
An Efficient FPGA-based Depthwise Separable Convolutional Neural Network Accelerator with Hardware Pruning	2
Programmable Analog System Benchmarks Leading to Efficient Analog Computation Synthesis	2
FPGA Acceleration of Probabilistic Sentential Decision Diagrams with High-level Synthesis	2
A Scalable Systolic Accelerator for Estimation of the Spectral Correlation Density Function and Its FPGA Implementation	2
Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units	2

FPGA-based Acceleration of Time Series Similarity Prediction: From Cloud to Edge	2
Data and Computation Reuse in CNNs Using Memristor TCAMs	2
A Hardware Design Framework for Computer Vision Models Based on Reconfigurable Devices	2
A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol and its Application	2
Inducing Non-uniform FPGA Aging Using Configuration-based Short Circuits	2
Cloud Building Block Chip for Creating FPGA and ASIC Clouds	2
Stream Aggregation with Compressed Sliding Windows	2
Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-switched Inter-FPGA Networks	2
Design Space Exploration of Galois and Fibonacci Configuration Based on Espresso Stream Cipher	2
VCSN: Virtual Circuit-Switching Network for Flexible and Simple-to-Operate Communication in HPC FPGA Cluster	2
Toward Software-like Debugging for FPGAs via Checkpointing and Transaction-based Co-Simulation	2
fSEAD: A Composable FPGA-based Streaming Ensemble Anomaly Detection Library	1
Across Time and Space: Senju ’s Approach for Scaling Iterative Stencil Loop Accelerators on Single and Multiple FPGAs	1
Reconfigurable Framework for Resilient Semantic Segmentation for Space Applications	1
DyRecMul: Fast and Low-Cost Approximate Multiplier for FPGAs using Dynamic Reconfiguration	1
Hardware Acceleration of High-Performance Computational Flow Dynamics Using High-Bandwidth Memory-Enabled Field-Programmable Gate Arrays	1
Topgun: An ECC Accelerator for Private Set Intersection	1
FDRA: A Framework for a Dynamically Reconfigurable Accelerator Supporting Multi-Level Parallelism	1
End-to-end codesign of Hessian-aware quantized neural networks for FPGAs	1
Understanding the Potential of FPGA-Based Spatial Acceleration for Large Language Model Inference	1
Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs	1
Tailor : Altering Skip Connections for Resource-Efficient Inference	1
Scalable Phylogeny Reconstruction with Disaggregated Near-memory Processing	1
Resource Sharing in Dataflow Circuits	1
Introduction to Special Issue on FPGAs in Data Centers, Part II	1
High Throughput FPGA-Based Object Detection via Algorithm-Hardware Co-Design	1
PQA: Exploring the Potential of Product Quantization in DNN Hardware Acceleration	1
GraphScale: Scalable Processing on FPGAs for HBM and Large Graphs	1
A Hardware Accelerator for the Semi-Global Matching Stereo Algorithm: An Efficient Implementation for the Stratix V and Zynq UltraScale+ FPGA Technology	1
Buffer Placement and Sizing for High-Performance Dataflow Circuits	1
Montgomery Multiplication Scalable Systolic Designs Optimized for DSP48E2	1
Parallelising Control Flow in Dynamic-scheduling High-level Synthesis	1
BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining	1
NAPOLY: A Non-deterministic Automata Processor OverLaY	1
Hardware Context Switch-based Cryptographic Accelerator for Handling Multiple Streams	1
HLPerf: Demystifying the Performance of HLS-based Graph Neural Networks with Dataflow Architectures	1
BISWSRBS: A Winograd-based CNN Accelerator with a Fine-grained Regular Sparsity Pattern and Mixed Precision Quantization	1
Deterministic Approach for Range-enhanced Reconfigurable Packet Classification Engine	1
Large-scale Cellular Automata on FPGAs	1
Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis	1
Introduction to the Special Section on FCCM 2022	1
Design and Implementation of Hardware-Software Architecture Based on Hashes for SPHINCS+	1
ScalaBFS2: A High-performance BFS Accelerator on an HBM-enhanced FPGA Chip	1
XVDPU: A High-Performance CNN Accelerator on the Versal Platform Powered by the AI Engine	1
Design and Evaluation of a Tunable PUF Architecture for FPGAs	1
Turn on, Tune in, and Listen up: Maximizing Side-Channel Recovery in Cross-Platform Time-to-Digital Converters	1
Fixed-point FPGA Implementation of the FFT Accumulation Method for Real-time Cyclostationary Analysis	1
Remarn: A Reconfigurable Multi-threaded Multi-core Accelerator for Recurrent Neural Networks	1