ACM Transactions on Reconfigurable Technology and Systems

Papers
(The H4-Index of ACM Transactions on Reconfigurable Technology and Systems is 19. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-08-01 to 2026-08-01.)
ArticleCitations
LHAM: Low-Cost and High-Accuracy Approximate Multiplier for FPGA-Based Computing164
HopliteML: Evolving Application Customized FPGA NoCs with Adaptable Routers and Regulators69
Tensor Slices: FPGA Building Blocks For The Deep Learning Era69
A Systematic Review of Fast, Scalable, and Efficient Hardware Implementations of Elliptic Curve Cryptography for Blockchain57
DF-BETA: An FPGA-based Memory Locality Aware Decision Forest Accelerator via Bit-Level Early Termination46
MCoreOPU: An FPGA-based Multi-Core Overlay Processor for Transformer-based Models40
FPGA-Based Sparse Matrix Multiplication Accelerators: From State-of-the-Art to Future Opportunities30
A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol and its Application30
Montgomery Multiplication Scalable Systolic Designs Optimized for DSP48E225
Eciton: Very Low-power Recurrent Neural Network Accelerator for Real-time Inference at the Edge24
RD-FAXID: Ransomware Detection with FPGA-Accelerated XGBoost24
High-Throughput TRNG Design with Novelty Adjustable TDC Based on STR22
An MLIR-Based Compilation Framework for Control Flow Management on Coarse Grained Reconfigurable Arrays21
Accelerating In-memory Database Functionality with FPGAs21
FDRA: A Framework for a Dynamically Reconfigurable Accelerator Supporting Multi-Level Parallelism21
FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs20
A Partitioned CAM Architecture with FPGA Acceleration for Binary Descriptor Matching19
A Speculative Loop Pipeline Framework with Accurate Path Modeling for High-Level Synthesis19
SIRA : Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators19
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