ACM Transactions on Reconfigurable Technology and Systems

Papers
(The H4-Index of ACM Transactions on Reconfigurable Technology and Systems is 17. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-05-01 to 2026-05-01.)
ArticleCitations
DF-BETA: An FPGA-based Memory Locality Aware Decision Forest Accelerator via Bit-Level Early Termination152
LHAM: Low-Cost and High-Accuracy Approximate Multiplier for FPGA-Based Computing61
HopliteML: Evolving Application Customized FPGA NoCs with Adaptable Routers and Regulators60
A Systematic Review of Fast, Scalable, and Efficient Hardware Implementations of Elliptic Curve Cryptography for Blockchain56
Tensor Slices: FPGA Building Blocks For The Deep Learning Era41
MCoreOPU: An FPGA-based Multi-Core Overlay Processor for Transformer-based Models36
FPGA-Based Sparse Matrix Multiplication Accelerators: From State-of-the-Art to Future Opportunities28
Eciton: Very Low-power Recurrent Neural Network Accelerator for Real-time Inference at the Edge27
FDRA: A Framework for a Dynamically Reconfigurable Accelerator Supporting Multi-Level Parallelism21
RD-FAXID: Ransomware Detection with FPGA-Accelerated XGBoost21
A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol and its Application21
Montgomery Multiplication Scalable Systolic Designs Optimized for DSP48E220
Accelerating In-memory Database Functionality with FPGAs19
High-Throughput TRNG Design with Novelty Adjustable TDC Based on STR19
FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs18
A Speculative Loop Pipeline Framework with Accurate Path Modeling for High-Level Synthesis17
A Partitioned CAM Architecture with FPGA Acceleration for Binary Descriptor Matching17
OpenDRAM: A Modular, High-performance Soft Memory Controller for DDR4 DRAM17
SPARTA: High-Level Synthesis of Parallel Multi-Threaded Accelerators17
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