IET Computers and Digital Techniques

Papers
(The TQCC of IET Computers and Digital Techniques is 3. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-03-01 to 2024-03-01.)
ArticleCitations
Ten years of hardware Trojans: a survey from the attacker's perspective33
Single bit‐line 11T SRAM cell for low power and improved stability33
High throughput and area‐efficient FPGA implementation of AES for high‐traffic applications19
Accelerating Deep Neural Networks implementation: A survey15
Lower complexity error location detection block of adjacent error correcting decoder for SRAMs13
Evaluation of the soft error assessment consistency of a JIT‐based virtual platform simulator13
Amdahl's law in the context of heterogeneous many‐core systems – a survey11
Low‐power fast Fourier transform hardware architecture combining a split‐radix butterfly and efficient adder compressors9
Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA8
In memory computation using quantum‐dot cellular automata8
VLSI implementation of anti‐notch lattice structure for identification of exon regions in Eukaryotic genes8
LUT‐based high‐speed point multiplier for Goldilocks‐Curve4487
Efficient design of 15:4 counter using a novel 5:3 counter for high‐speed multiplication6
Sparse convolutional neural network acceleration with lossless input feature map compression for resource‐constrained systems6
Network‐on‐chip heuristic mapping algorithm based on isomorphism elimination for NoC optimisation5
Ternary DDCVSL: a combined dynamic logic style for standard ternary logic with single power source5
A radix‐8 modulo 2 n multiplier using area and power‐optimized hard multiple generator5
Robustness of predictive energy harvesting systems: Analysis and adaptive prediction scaling5
Hybrid multi‐level hardware Trojan detection platform for gate‐level netlists based on XGBoost4
Flexible and high‐throughput structures of Camellia block cipher for security of the Internet of Things4
Optimised HEVC encoder intra‐only configuration4
Reliable SRAM using NAND‐NOR Gate in beyond‐CMOS QCA technology4
Efficient VLSI architectures of lifting based 3D discrete wavelet transform4
A novel task scheduling approach for dependent non‐preemptive tasks using fuzzy logic3
FPGA‐based implementation of floating point processing element for the design of efficient FIR filters3
Event‐based high throughput computing: A series of case studies on a massively parallel softcore machine3
Power efficient error correction coding for on‐chip interconnection links3
Sensitivity analysis of testability parameters for secure IC design3
Voltage over‐scaling CNT‐based 8‐bit multiplier by high‐efficient GDI‐based counters3
An embedded intelligence engine for driver drowsiness detection3
Technique for two‐dimensional nearest neighbour realisation of quantum circuits using weighted look‐ahead3
Analysis of power–accuracy trade‐off in digital signal processing applications using low‐power approximate adders3
The analogy of matchline sensing techniques for content addressable memory (CAM)3
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