IET Computers and Digital Techniques

Papers
(The TQCC of IET Computers and Digital Techniques is 3. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-11-01 to 2024-11-01.)
ArticleCitations
Accelerating Deep Neural Networks implementation: A survey18
Evaluation of the soft error assessment consistency of a JIT‐based virtual platform simulator13
Low‐power fast Fourier transform hardware architecture combining a split‐radix butterfly and efficient adder compressors10
Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA8
Sparse convolutional neural network acceleration with lossless input feature map compression for resource‐constrained systems8
A radix‐8 modulo 2nmultiplier using area and power‐optimized hard multiple generator7
Efficient design of 15:4 counter using a novel 5:3 counter for high‐speed multiplication7
Flexible and high‐throughput structures of Camellia block cipher for security of the Internet of Things7
Hybrid multi‐level hardware Trojan detection platform for gate‐level netlists based on XGBoost5
Low‐space bit‐serial systolic array architecture for interleaved multiplication over GF(2 m )5
Robustness of predictive energy harvesting systems: Analysis and adaptive prediction scaling5
An embedded intelligence engine for driver drowsiness detection4
Voltage over‐scaling CNT‐based 8‐bit multiplier by high‐efficient GDI‐based counters4
Reliable SRAM using NAND‐NOR Gate in beyond‐CMOS QCA technology4
Event‐based high throughput computing: A series of case studies on a massively parallel softcore machine4
Verification of serialising instructions for security against transient execution attacks3
Residual vulnerabilities to power side channel attacks of lightweight ciphers cryptography competition finalists3
FPGA‐based implementation of floating point processing element for the design of efficient FIR filters3
A four‐stage yield optimization technique for analog integrated circuits using optimal computing budget allocation and evolutionary algorithms3
Illegal Trojan design and detection in asynchronous NULL Convention Logic and Sleep Convention Logic circuits3
A novel task scheduling approach for dependent non‐preemptive tasks using fuzzy logic3
Analysis of power–accuracy trade‐off in digital signal processing applications using low‐power approximate adders3
Automatic diagnosis of single fault in interconnect testing of SRAM‐based FPGA3
Noise‐based logic locking scheme against signal probability skew analysis3
EmRep: Energy management relying on state‐of‐charge extrema prediction3
Accelerating the SM3 hash algorithm with CPU‐FPGA Co‐Designed architecture3
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