IET Computers and Digital Techniques

Papers
(The median citation count of IET Computers and Digital Techniques is 1. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-05-01 to 2025-05-01.)
ArticleCitations
Evaluation of the Soft Error Assessment Consistency of a JIT‐based Virtual Platform Simulator8
A FPGA Accelerator of Distributed A3C Algorithm with Optimal Resource Deployment6
Sparse convolutional neural network acceleration with lossless input feature map compression for resource‐constrained systems5
5
An embedded intelligence engine for driver drowsiness detection4
Guest Editorial: Special issue on battery‐free computing4
E‐Commerce Logistics Software Package Tracking and Route Planning and Optimization System of Embedded Technology Based on the Intelligent Era4
3
TLP: Towards three‐level loop parallelisation3
Q‐scheduler: A temperature and energy‐aware deep Q‐learning technique to schedule tasks in real‐time multiprocessor embedded systems3
A Configurable Accelerator for CNN‐Based Remote Sensing Object Detection on FPGAs3
Design and analysis of a novel fast adder using logical effort method3
A four‐stage yield optimization technique for analog integrated circuits using optimal computing budget allocation and evolutionary algorithms3
An Efficient RTL Design for a Wearable Brain–Computer Interface3
Energy‐Efficient Branch Predictor via Instruction Block Type Prediction in Decoupled Frontend2
Efficient implementation of low cost and secure framework with firmware updates2
Machine learning guided thermal management of Open Computing Language applications on CPU‐GPU based embedded platforms2
Voltage over‐scaling CNT‐based 8‐bit multiplier by high‐efficient GDI‐based counters2
A Reconfigurable Coarse‐to‐Fine Approach for the Execution of CNN Inference Models in Low‐Power Edge Devices2
EmRep: Energy management relying on state‐of‐charge extrema prediction2
Illegal Trojan design and detection in asynchronous NULL Convention Logic and Sleep Convention Logic circuits2
Event‐based high throughput computing: A series of case studies on a massively parallel softcore machine2
Residual vulnerabilities to power side channel attacks of lightweight ciphers cryptography competition finalists1
Accelerating the SM3 hash algorithm with CPU‐FPGA Co‐Designed architecture1
Multi‐objective digital circuit block optimisation based on cell mapping in an industrial electronic design automation flow1
Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme1
Fast approximation of the top‐k items in data streams using FPGAs1
Research on mapping recognition of arc welding molten pool characterisation and penetration state based on embedded system1
1
ActiveGuard: An active intellectual property protection technique for deep neural networks by leveraging adversarial examples as users' fingerprints1
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