IET Computers and Digital Techniques

Papers
(The median citation count of IET Computers and Digital Techniques is 1. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-03-01 to 2024-03-01.)
ArticleCitations
Ten years of hardware Trojans: a survey from the attacker's perspective33
Single bit‐line 11T SRAM cell for low power and improved stability33
High throughput and area‐efficient FPGA implementation of AES for high‐traffic applications19
Accelerating Deep Neural Networks implementation: A survey15
Lower complexity error location detection block of adjacent error correcting decoder for SRAMs13
Evaluation of the soft error assessment consistency of a JIT‐based virtual platform simulator13
Amdahl's law in the context of heterogeneous many‐core systems – a survey11
Low‐power fast Fourier transform hardware architecture combining a split‐radix butterfly and efficient adder compressors9
Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA8
In memory computation using quantum‐dot cellular automata8
VLSI implementation of anti‐notch lattice structure for identification of exon regions in Eukaryotic genes8
LUT‐based high‐speed point multiplier for Goldilocks‐Curve4487
Efficient design of 15:4 counter using a novel 5:3 counter for high‐speed multiplication6
Sparse convolutional neural network acceleration with lossless input feature map compression for resource‐constrained systems6
Network‐on‐chip heuristic mapping algorithm based on isomorphism elimination for NoC optimisation5
Ternary DDCVSL: a combined dynamic logic style for standard ternary logic with single power source5
A radix‐8 modulo 2 n multiplier using area and power‐optimized hard multiple generator5
Robustness of predictive energy harvesting systems: Analysis and adaptive prediction scaling5
Hybrid multi‐level hardware Trojan detection platform for gate‐level netlists based on XGBoost4
Flexible and high‐throughput structures of Camellia block cipher for security of the Internet of Things4
Optimised HEVC encoder intra‐only configuration4
Reliable SRAM using NAND‐NOR Gate in beyond‐CMOS QCA technology4
Efficient VLSI architectures of lifting based 3D discrete wavelet transform4
A novel task scheduling approach for dependent non‐preemptive tasks using fuzzy logic3
FPGA‐based implementation of floating point processing element for the design of efficient FIR filters3
Event‐based high throughput computing: A series of case studies on a massively parallel softcore machine3
Power efficient error correction coding for on‐chip interconnection links3
Sensitivity analysis of testability parameters for secure IC design3
Voltage over‐scaling CNT‐based 8‐bit multiplier by high‐efficient GDI‐based counters3
An embedded intelligence engine for driver drowsiness detection3
Technique for two‐dimensional nearest neighbour realisation of quantum circuits using weighted look‐ahead3
Analysis of power–accuracy trade‐off in digital signal processing applications using low‐power approximate adders3
The analogy of matchline sensing techniques for content addressable memory (CAM)3
Automatic diagnosis of single fault in interconnect testing of SRAM‐based FPGA2
Machine learning guided thermal management of Open Computing Language applications on CPU‐GPU based embedded platforms2
Recycled integrated circuit detection using reliability analysis and machine learning algorithms2
A four‐stage yield optimization technique for analog integrated circuits using optimal computing budget allocation and evolutionary algorithms2
Noise‐based logic locking scheme against signal probability skew analysis2
ASATM: Automated security assistant of threat models in intelligent transportation systems2
Homeland security video surveillance system utilising the internet of video things for smart cities2
Q‐scheduler: A temperature and energy‐aware deep Q‐learning technique to schedule tasks in real‐time multiprocessor embedded systems2
Low‐space bit‐serial systolic array architecture for interleaved multiplication over GF(2 m )2
EmRep: Energy management relying on state‐of‐charge extrema prediction2
Fast and low‐power leading‐one detectors for energy‐efficient logarithmic computing2
Illegal Trojan design and detection in asynchronous NULL Convention Logic and Sleep Convention Logic circuits1
Fragmented software‐based self‐test technique for online intermittent fault detection in processors1
Scalable pseudo‐exhaustive methodology for testing and diagnosis in flow‐based microfluidic biochips1
Rectilinear routing algorithm for crosstalk minimisation in 2D and 3D IC1
Accelerating the SM3 hash algorithm with CPU‐FPGA Co‐Designed architecture1
Fast approximation of the top‐k items in data streams using FPGAs1
Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme1
Synchronization in graph analysis algorithms on the Partially Ordered Event‐Triggered Systems many‐core architecture1
Introducing KeyRing self‐timed microarchitecture and timing‐driven design flow1
TLP: Towards three‐level loop parallelisation1
Automated planning for finding alternative bug traces1
Area and power‐efficient variable‐length fast Fourier transform for MR‐OFDM physical layer of IEEE 802.15.4‐g1
Towards IP integration on SoC: a case study of high‐throughput and low‐cost wrapper design on a novel IBUS architecture1
Static power model for CMOS and FPGA circuits1
Verification of serialising instructions for security against transient execution attacks1
Multi‐core hardware realisation of the quasi maximum likelihood PPS estimator1
Enhanced overloaded code division multiple access for network on chip1
Efficient parallelisation of the packet classification algorithms on multi‐core central processing units using multi‐threading application program interfaces1
New scan compression approach to reduce the test data volume1
SD‐SHO: Security‐dominated finite state machine state assignment technique with a satisfactory level of hardware optimization1
A novel FPGA‐Based Bi input‐reduced order extended Kalman filter for speed‐sensorless direct torque control of induction motor with constant switching frequency controller1
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