OOIR: Observatory of International Research

Papers

(The median citation count of IET Computers and Digital Techniques is 1. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-11-01 to 2024-11-01.)

Article	Citations
Accelerating Deep Neural Networks implementation: A survey	18
Evaluation of the soft error assessment consistency of a JIT‐based virtual platform simulator	13
Low‐power fast Fourier transform hardware architecture combining a split‐radix butterfly and efficient adder compressors	10
Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA	8
Sparse convolutional neural network acceleration with lossless input feature map compression for resource‐constrained systems	8
Flexible and high‐throughput structures of Camellia block cipher for security of the Internet of Things	7
A radix‐8 modulo 2ⁿmultiplier using area and power‐optimized hard multiple generator	7
Efficient design of 15:4 counter using a novel 5:3 counter for high‐speed multiplication	7
Robustness of predictive energy harvesting systems: Analysis and adaptive prediction scaling	5
Hybrid multi‐level hardware Trojan detection platform for gate‐level netlists based on XGBoost	5
Low‐space bit‐serial systolic array architecture for interleaved multiplication over GF(2 ^m )	5
Voltage over‐scaling CNT‐based 8‐bit multiplier by high‐efficient GDI‐based counters	4
Reliable SRAM using NAND‐NOR Gate in beyond‐CMOS QCA technology	4
Event‐based high throughput computing: A series of case studies on a massively parallel softcore machine	4
An embedded intelligence engine for driver drowsiness detection	4
Automatic diagnosis of single fault in interconnect testing of SRAM‐based FPGA	3
Noise‐based logic locking scheme against signal probability skew analysis	3
EmRep: Energy management relying on state‐of‐charge extrema prediction	3
Accelerating the SM3 hash algorithm with CPU‐FPGA Co‐Designed architecture	3
Verification of serialising instructions for security against transient execution attacks	3
Residual vulnerabilities to power side channel attacks of lightweight ciphers cryptography competition finalists	3
FPGA‐based implementation of floating point processing element for the design of efficient FIR filters	3
A four‐stage yield optimization technique for analog integrated circuits using optimal computing budget allocation and evolutionary algorithms	3
Illegal Trojan design and detection in asynchronous NULL Convention Logic and Sleep Convention Logic circuits	3
A novel task scheduling approach for dependent non‐preemptive tasks using fuzzy logic	3

Analysis of power–accuracy trade‐off in digital signal processing applications using low‐power approximate adders	3
Q‐scheduler: A temperature and energy‐aware deep Q‐learning technique to schedule tasks in real‐time multiprocessor embedded systems	2
Fragmented software‐based self‐test technique for online intermittent fault detection in processors	2
Homeland security video surveillance system utilising the internet of video things for smart cities	2
Machine learning guided thermal management of Open Computing Language applications on CPU‐GPU based embedded platforms	2
ASATM: Automated security assistant of threat models in intelligent transportation systems	2
Fast and low‐power leading‐one detectors for energy‐efficient logarithmic computing	2
Introducing KeyRing self‐timed microarchitecture and timing‐driven design flow	2
Recycled integrated circuit detection using reliability analysis and machine learning algorithms	2
Fast approximation of the top‐k items in data streams using FPGAs	2
A novel FPGA‐Based Bi input‐reduced order extended Kalman filter for speed‐sensorless direct torque control of induction motor with constant switching frequency controller	1
Efficient implementation of low cost and secure framework with firmware updates	1
Research on mapping recognition of arc welding molten pool characterisation and penetration state based on embedded system	1
Who is wearing me? TinyDL‐based user recognition in constrained personal devices	1
Static power model for CMOS and FPGA circuits	1
Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme	1
Enhanced overloaded code division multiple access for network on chip	1
TLP: Towards three‐level loop parallelisation	1
An optimized knight traversal technique to detect multiple faults and Module Sequence Graph based reconfiguration of microfluidic biochip	1
Phone‐nomenon 2.0: A compact thermal model for smartphones	1
The DFA/DFT‐based hacking techniques and countermeasures: Case study of the 32‐bit AES encryption crypto‐core	1
Synchronization in graph analysis algorithms on the Partially Ordered Event‐Triggered Systems many‐core architecture	1
New scan compression approach to reduce the test data volume	1
SD‐SHO: Security‐dominated finite state machine state assignment technique with a satisfactory level of hardware optimization	1