OOIR: Observatory of International Research

Papers

(The TQCC of IEEE Computer Architecture Letters is 2. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-05-01 to 2025-05-01.)

Article	Citations
Learned Performance Model for SSD	29
Speculative Multi-Level Access in LSM Tree-Based KV Store	26
Accelerating Programmable Bootstrapping Targeting Contemporary GPU Microarchitecture	17
Toward Practical 128-Bit General Purpose Microarchitectures	13
Characterization and Analysis of Text-to-Image Diffusion Models	12
A Characterization of Generative Recommendation Models: Study of Hierarchical Sequential Transduction Unit	11
SCALES: SCALable and Area-Efficient Systolic Accelerator for Ternary Polynomial Multiplication	11
Decoupled SSD: Reducing Data Movement on NAND-Based Flash SSD	11
SoCurity: A Design Approach for Enhancing SoC Security	10
2021 Index IEEE Computer Architecture Letters Vol. 20	10
Straw: A Stress-Aware WL-Based Read Reclaim Technique for High-Density NAND Flash-Based SSDs	10
Scale-Model Simulation	10
In-Memory Versioning (IMV)	9
RouteReplies: Alleviating Long Latency in Many-Chip-Module GPUs	9
Improving Energy-Efficiency of Capsule Networks on Modern GPUs	9
A Flexible Embedding-Aware Near Memory Processing Architecture for Recommendation System	9
A Case for In-Memory Random Scatter-Gather for Fast Graph Processing	8
Reorder Buffer Contention: A Forward Speculative Interference Attack for Speculation Invariant Instructions	8
Exploring the DIMM PIM Architecture for Accelerating Time Series Analysis	8
Security Helper Chiplets: A New Paradigm for Secure Hardware Monitoring	7
Mitigating Timing-Based NoC Side-Channel Attacks With LLC Remapping	7
Exploiting Intel Advanced Matrix Extensions (AMX) for Large Language Model Inference	7
QuArch: A Question-Answering Dataset for AI Agents in Computer Architecture	7
DeMM: A Decoupled Matrix Multiplication Engine Supporting Relaxed Structured Sparsity	6
NoHammer: Preventing Row Hammer With Last-Level Cache Management	6

Accelerating Deep Reinforcement Learning via Phase-Level Parallelism for Robotics Applications	6
Managing Prefetchers With Deep Reinforcement Learning	5
LADIO: Leakage-Aware Direct I/O for I/O-Intensive Workloads	5
High-Performance Winograd Based Accelerator Architecture for Convolutional Neural Network	5
Data-Aware Compression of Neural Networks	5
Memory-Centric MCM-GPU Architecture	5
SparseLeakyNets: Classification Prediction Attack Over Sparsity-Aware Embedded Neural Networks Using Timing Side-Channel Information	5
A Flexible Hybrid Interconnection Design for High-Performance and Energy-Efficient Chiplet-Based Systems	4
Chopping off the Tail: Bounded Non-Determinism for Real-Time Accelerators	4
Primate: A Framework to Automatically Generate Soft Processors for Network Applications	4
Fast Performance Prediction for Efficient Distributed DNN Training	4
Understanding the Implication of Non-Volatile Memory for Large-Scale Graph Neural Network Training	4
Enhancing the Reach and Reliability of Quantum Annealers by Pruning Longer Chains	4
Adaptive Web Browsing on Mobile Heterogeneous Multi-cores	4
FPGA-Accelerated Data Preprocessing for Personalized Recommendation Systems	4
PreGNN: Hardware Acceleration to Take Preprocessing Off the Critical Path in Graph Neural Networks	4
ZoneBuffer: An Efficient Buffer Management Scheme for ZNS SSDs	4
Guard Cache: Creating Noisy Side-Channels	4
A Quantum Computer Trusted Execution Environment	3
Energy-Efficient Bayesian Inference Using Bitstream Computing	3
PINSim: A Processing In- and Near-Sensor Simulator to Model Intelligent Vision Sensors	3
Accelerators & Security: The Socket Approach	3
Exploring Volatile FPGAs Potential for Accelerating Energy-Harvesting IoT Applications	3
T-CAT: Dynamic Cache Allocation for Tiered Memory Systems With Memory Interleaving	3
Characterization and Analysis of Deep Learning for 3D Point Cloud Analytics	3
SSE: Security Service Engines to Accelerate Enclave Performance in Secure Multicore Processors	3
Architectural Implications of GNN Aggregation Programming Abstractions	3
Enhancing DNN Training Efficiency Via Dynamic Asymmetric Architecture	2
A Case Study of a DRAM-NVM Hybrid Memory Allocator for Key-Value Stores	2
Analyzing and Exploiting Memory Hierarchy Parallelism With MLP Stacks	2
Unleashing the Potential of PIM: Accelerating Large Batched Inference of Transformer-Based Generative Models	2
Redundant Array of Independent Memory Devices	2
IntervalSim++: Enhanced Interval Simulation for Unbalanced Processor Designs	2
Reducing the Silicon Area Overhead of Counter-Based Rowhammer Mitigations	2
SEMS: Scalable Embedding Memory System for Accelerating Embedding-Based DNNs	2
Characterization and Implementation of Radar System Applications on a Reconfigurable Dataflow Architecture	2
Hungarian Qubit Assignment for Optimized Mapping of Quantum Circuits on Multi-Core Architectures	2
Computational CXL-Memory Solution for Accelerating Memory-Intensive Applications	2
Cost-Effective Extension of DRAM-PIM for Group-Wise LLM Quantization	2
Halis: A Hardware-Software Co-designed Near-Cache Accelerator for Graph Pattern Mining	2
Accelerating Page Migrations in Operating Systems With Intel DSA	2
DRAM-CAM: General-Purpose Bit-Serial Exact Pattern Matching	2
gem5-accel: A Pre-RTL Simulation Toolchain for Accelerator Architecture Validation	2
Overcoming Memory Capacity Wall of GPUs With Heterogeneous Memory Stack	2
R.I.P. Geomean Speedup Use Equal-Work (Or Equal-Time) Harmonic Mean Speedup Instead	2
Approximate Multiplier Design With LFSR-Based Stochastic Sequence Generators for Edge AI	2
Characterization and Analysis of the 3D Gaussian Splatting Rendering Pipeline	2
HBM3 RAS: Enhancing Resilience at Scale	2
FullPack: Full Vector Utilization for Sub-Byte Quantized Matrix-Vector Multiplication on General Purpose CPUs	2
A First-Order Model to Assess Computer Architecture Sustainability	2

FPGA-Based AI Smart NICs for Scalable Distributed AI Training Systems	2
Direct-Coding DNA With Multilevel Parallelism	2