OOIR: Observatory of International Research

Papers

(The median citation count of IEEE Computer Architecture Letters is 1. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-11-01 to 2024-11-01.)

Article	Citations
RAMBO: Resource Allocation for Microservices Using Bayesian Optimization	33
Lightweight Hardware Implementation of Binary Ring-LWE PQC Accelerator	20
MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator	16
Flexion: A Quantitative Metric for Flexibility in DNN Accelerators	14
HBM3 RAS: Enhancing Resilience at Scale	12
Cryogenic PIM: Challenges & Opportunities	11
STONNE: Enabling Cycle-Level Microarchitectural Simulation for DNN Inference Accelerators	9
TRiM: Tensor Reduction in Memory	9
A Day In the Life of a Quantum Error	9
FPGA-Based AI Smart NICs for Scalable Distributed AI Training Systems	8
Reorder Buffer Contention: A Forward Speculative Interference Attack for Speculation Invariant Instructions	8
Heterogeneity-Aware Scheduling on SoCs for Autonomous Vehicles	8
DRAM-CAM: General-Purpose Bit-Serial Exact Pattern Matching	7
LT-PIM: An LUT-Based Processing-in-DRAM Architecture With RowHammer Self-Tracking	7
Accelerating Concurrent Priority Scheduling Using Adaptive in-Hardware Task Distribution in Multicores	7
GraNDe: Near-Data Processing Architecture With Adaptive Matrix Mapping for Graph Convolutional Networks	7
Characterizing and Understanding End-to-End Multi-Modal Neural Networks on GPUs	7
BTB-X: A Storage-Effective BTB Organization	7
Understanding the Implication of Non-Volatile Memory for Large-Scale Graph Neural Network Training	6
Instruction Criticality Based Energy-Efficient Hardware Data Prefetching	6
Characterizing and Understanding HGNNs on GPUs	6
Characterizing and Understanding Distributed GNN Training on GPUs	6
Computational CXL-Memory Solution for Accelerating Memory-Intensive Applications	6
Infinity Stream: Enabling Transparent and Automated In-Memory Computing	5
Towards Improved Power Management in Cloud GPUs	5

A First-Order Model to Assess Computer Architecture Sustainability	5
Deep Partitioned Training From Near-Storage Computing to DNN Accelerators	5
X-ray: Discovering DRAM Internal Structure and Error Characteristics by Issuing Memory Commands	5
Hardware Acceleration for GCNs via Bidirectional Fusion	5
Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays	4
WPC: Whole-Picture Workload Characterization Across Intermediate Representation, ISA, and Microarchitecture	4
Zero-Copying I/O Stack for Low-Latency SSDs	4
Decoupled SSD: Reducing Data Movement on NAND-Based Flash SSD	4
Mitigating Timing-Based NoC Side-Channel Attacks With LLC Remapping	4
Row-Streaming Dataflow Using a Chaining Buffer and Systolic Array+ Structure	4
Adaptive Web Browsing on Mobile Heterogeneous Multi-cores	4
Last-Level Cache Insertion and Promotion Policy in the Presence of Aggressive Prefetching	4
Characterization and Implementation of Radar System Applications on a Reconfigurable Dataflow Architecture	4
OpenMDS: An Open-Source Shell Generation Framework for High-Performance Design on Xilinx Multi-Die FPGAs	4
DAM: Deadblock Aware Migration Techniques for STT-RAM-Based Hybrid Caches	4
Dynamic Optimization of On-Chip Memories for HLS Targeting Many-Accelerator Platforms	4
Managing Prefetchers With Deep Reinforcement Learning	4
Hungarian Qubit Assignment for Optimized Mapping of Quantum Circuits on Multi-Core Architectures	4
Accelerating Graph Processing With Lightweight Learning-Based Data Reordering	3
A Quantum Computer Trusted Execution Environment	3
Near-Data Processing in Memory Expander for DNN Acceleration on GPUs	3
MQSim-E: An Enterprise SSD Simulator	3
Data-Aware Compression of Neural Networks	3
gem5-accel: A Pre-RTL Simulation Toolchain for Accelerator Architecture Validation	3
Making a Better Use of Caches for GCN Accelerators with Feature Slicing and Automatic Tile Morphing	3
Unleashing the Potential of PIM: Accelerating Large Batched Inference of Transformer-Based Generative Models	3
DAMARU: A Denial-of-Service Attack on Randomized Last-Level Caches	2
Hardware-Implemented Lightweight Accelerator for Large Integer Polynomial Multiplication	2
BayesTuner: Leveraging Bayesian Optimization For DNN Inference Configuration Selection	2
Fine-Grained Scheduling in Heterogeneous-ISA Architectures	2
Balancing Performance Against Cost and Sustainability in Multi-Chip-Module GPUs	2
FPGA-Accelerated Data Preprocessing for Personalized Recommendation Systems	2
The Case for Replication-Aware Memory-Error Protection in Disaggregated Memory	2
PreGNN: Hardware Acceleration to Take Preprocessing Off the Critical Path in Graph Neural Networks	2
The Case for Dynamic Bias in Global Adaptive Routing	2
A Case for Speculative Strength Reduction	2
A Case Study of a DRAM-NVM Hybrid Memory Allocator for Key-Value Stores	2
Reducing the Silicon Area Overhead of Counter-Based Rowhammer Mitigations	2
Multi-Prediction Compression: An Efficient and Scalable Memory Compression Framework for GP-GPU	2
Accelerators & Security: The Socket Approach	2
Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator	2
Scale-Model Simulation	2
Advancing Compilation of DNNs for FPGAs Using Operation Set Architectures	2
Exploring PIM Architecture for High-Performance Graph Pattern Mining	2
MPU-Sim: A Simulator for In-DRAM Near-Bank Processing Architectures	2
Stride Equality Prediction for Value Speculation	2
XLA-NDP: Efficient Scheduling and Code Generation for Deep Learning Model Training on Near-Data Processing Memory	2
A Flexible Embedding-Aware Near Memory Processing Architecture for Recommendation System	2
Characterization and Analysis of Deep Learning for 3D Point Cloud Analytics	1
DVFaaS: Leveraging DVFS for FaaS Workflows	1

Modeling Periodic Energy-Harvesting Computing Systems	1
LV: Latency-Versatile Floating-Point Engine for High-Performance Deep Neural Networks	1
A Pre-Silicon Approach to Discovering Microarchitectural Vulnerabilities in Security Critical Applications	1
DRAMA: Commodity DRAM Based Content Addressable Memory	1
TokenSmart: Distributed, Scalable Power Management in the Many-Core Era	1
Runtime Support for Accelerating CNN Models on Digital DRAM Processing-in-Memory Hardware	1
Overcoming Memory Capacity Wall of GPUs With Heterogeneous Memory Stack	1
Energy-Efficient Bayesian Inference Using Bitstream Computing	1
SSE: Security Service Engines to Accelerate Enclave Performance in Secure Multicore Processors	1
FlexScore: Quantifying Flexibility	1
Modeling DRAM Timing in Parallel Simulators With Immediate-Response Memory Model	1
Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems	1
Improving Energy-Efficiency of Capsule Networks on Modern GPUs	1
Hardware Accelerated Reusable Merkle Tree Generation for Bitcoin Blockchain Headers	1
Analysis of Data Transfer Bottlenecks in Commercial PIM Systems: A Study With UPMEM-PIM	1
Approximate Multiplier Design With LFSR-Based Stochastic Sequence Generators for Edge AI	1
Direct-Coding DNA With Multilevel Parallelism	1
DNA Pre-Alignment Filter Using Processing Near Racetrack Memory	1
Ensuring Data Confidentiality in eADR-Based NVM Systems	1
ADT: Aggressive Demotion and Promotion for Tiered Memory	1
RouteReplies: Alleviating Long Latency in Many-Chip-Module GPUs	1
SmaQ: Smart Quantization for DNN Training by Exploiting Value Clustering	1
By-Software Branch Prediction in Loops	1
LADIO: Leakage-Aware Direct I/O for I/O-Intensive Workloads	1
A Model for Scalable and Balanced Accelerators for Graph Processing	1
NoHammer: Preventing Row Hammer With Last-Level Cache Management	1
Architectural Implications of GNN Aggregation Programming Abstractions	1
T-CAT: Dynamic Cache Allocation for Tiered Memory Systems With Memory Interleaving	1