IEEE Computer Architecture Letters

Article	Citations
DRAMsim3: A Cycle-Accurate, Thermal-Capable DRAM Simulator	86
SmartSSD: FPGA Accelerated Near-Storage Data Analytics on SSD	39
RAMBO: Resource Allocation for Microservices Using Bayesian Optimization	29
GPU-NEST: Characterizing Energy Efficiency of Multi-GPU Inference Servers	27
pPIM: A Programmable Processor-in-Memory Architecture With Precision-Scaling for Deep Learning	18
The Entangling Instruction Prefetcher	16
Lightweight Hardware Implementation of Binary Ring-LWE PQC Accelerator	14
MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator	13
A Cross-Stack Approach Towards Defending Against Cryptojacking	12
Flexion: A Quantitative Metric for Flexibility in DNN Accelerators	11
Rebasing Instruction Prefetching: An Industry Perspective	10
HBM3 RAS: Enhancing Resilience at Scale	9
Cryogenic PIM: Challenges & Opportunities	9
STONNE: Enabling Cycle-Level Microarchitectural Simulation for DNN Inference Accelerators	8
Reorder Buffer Contention: A Forward Speculative Interference Attack for Speculation Invariant Instructions	8
Heterogeneity-Aware Scheduling on SoCs for Autonomous Vehicles	7
TRiM: Tensor Reduction in Memory	7
A Day In the Life of a Quantum Error	7
Characterizing and Understanding End-to-End Multi-Modal Neural Networks on GPUs	6
Harnessing Pairwise-Correlating Data Prefetching With Runahead Metadata	6
Accelerating Concurrent Priority Scheduling Using Adaptive in-Hardware Task Distribution in Multicores	6
MCsim: An Extensible DRAM Memory Controller Simulator	6
Understanding the Implication of Non-Volatile Memory for Large-Scale Graph Neural Network Training	5
Dagger: Towards Efficient RPCs in Cloud Microservices With Near-Memory Reconfigurable NICs	5
FPGA-Based AI Smart NICs for Scalable Distributed AI Training Systems	5

Computational CXL-Memory Solution for Accelerating Memory-Intensive Applications	5
Instruction Criticality Based Energy-Efficient Hardware Data Prefetching	5
BTB-X: A Storage-Effective BTB Organization	5
Row-Streaming Dataflow Using a Chaining Buffer and Systolic Array+ Structure	4
Dynamic Optimization of On-Chip Memories for HLS Targeting Many-Accelerator Platforms	4
GraNDe: Near-Data Processing Architecture With Adaptive Matrix Mapping for Graph Convolutional Networks	4
DAM: Deadblock Aware Migration Techniques for STT-RAM-Based Hybrid Caches	4
A Lightweight Memory Access Pattern Obfuscation Framework for NVM	4
Adaptive Web Browsing on Mobile Heterogeneous Multi-cores	4
Characterizing and Understanding HGNNs on GPUs	4
A First-Order Model to Assess Computer Architecture Sustainability	3
Deep Partitioned Training From Near-Storage Computing to DNN Accelerators	3
Zero-Copying I/O Stack for Low-Latency SSDs	3
Hardware Acceleration for GCNs via Bidirectional Fusion	3
OpenMDS: An Open-Source Shell Generation Framework for High-Performance Design on Xilinx Multi-Die FPGAs	3
WPC: Whole-Picture Workload Characterization Across Intermediate Representation, ISA, and Microarchitecture	3
Infinity Stream: Enabling Transparent and Automated In-Memory Computing	3
Managing Prefetchers With Deep Reinforcement Learning	3
Decoupled SSD: Reducing Data Movement on NAND-Based Flash SSD	3
DRAM-CAM: General-Purpose Bit-Serial Exact Pattern Matching	3
Making a Better Use of Caches for GCN Accelerators with Feature Slicing and Automatic Tile Morphing	3
Characterizing and Understanding Distributed GNN Training on GPUs	3
LT-PIM: An LUT-Based Processing-in-DRAM Architecture With RowHammer Self-Tracking	3
Near-Data Processing in Memory Expander for DNN Acceleration on GPUs	3
Last-Level Cache Insertion and Promotion Policy in the Presence of Aggressive Prefetching	2
Characterization and Implementation of Radar System Applications on a Reconfigurable Dataflow Architecture	2
The Case for Domain-Specialized Branch Predictors for Graph-Processing	2
DAMARU: A Denial-of-Service Attack on Randomized Last-Level Caches	2
A Case for Speculative Strength Reduction	2
PIM-GraphSCC: PIM-Based Graph Processing Using Graph’s Community Structures	2
Enabling In-SRAM Pattern Processing With Low-Overhead Reporting Architecture	2
Exploring PIM Architecture for High-Performance Graph Pattern Mining	2
Data-Aware Compression of Neural Networks	2
Accelerating Graph Processing With Lightweight Learning-Based Data Reordering	2
The Case for Dynamic Bias in Global Adaptive Routing	2
Balancing Performance Against Cost and Sustainability in Multi-Chip-Module GPUs	1
Fine-Grained Scheduling in Heterogeneous-ISA Architectures	1
Characterization and Analysis of Deep Learning for 3D Point Cloud Analytics	1
Modeling DRAM Timing in Parallel Simulators With Immediate-Response Memory Model	1
By-Software Branch Prediction in Loops	1
X-ray: Discovering DRAM Internal Structure and Error Characteristics by Issuing Memory Commands	1
Aging-Aware Context Switching in Multicore Processors Based on Workload Classification	1
Hungarian Qubit Assignment for Optimized Mapping of Quantum Circuits on Multi-Core Architectures	1
A Model for Scalable and Balanced Accelerators for Graph Processing	1
MPU-Sim: A Simulator for In-DRAM Near-Bank Processing Architectures	1
Stride Equality Prediction for Value Speculation	1
Accelerators & Security: The Socket Approach	1
FlexScore: Quantifying Flexibility	1
LV: Latency-Versatile Floating-Point Engine for High-Performance Deep Neural Networks	1
SmaQ: Smart Quantization for DNN Training by Exploiting Value Clustering	1

A Pre-Silicon Approach to Discovering Microarchitectural Vulnerabilities in Security Critical Applications	1
Energy-Efficient Bayesian Inference Using Bitstream Computing	1
Advancing Compilation of DNNs for FPGAs Using Operation Set Architectures	1
Runtime Support for Accelerating CNN Models on Digital DRAM Processing-in-Memory Hardware	1
Multi-Prediction Compression: An Efficient and Scalable Memory Compression Framework for GP-GPU	1
gem5-accel: A Pre-RTL Simulation Toolchain for Accelerator Architecture Validation	1
XLA-NDP: Efficient Scheduling and Code Generation for Deep Learning Model Training on Near-Data Processing Memory	1
The Case for Replication-Aware Memory-Error Protection in Disaggregated Memory	1
Modeling Periodic Energy-Harvesting Computing Systems	1
FastDrain: Removing Page Victimization Overheads in NVMe Storage Stack	1
Scale-Model Simulation	1
BayesTuner: Leveraging Bayesian Optimization For DNN Inference Configuration Selection	1
A Case Study of a DRAM-NVM Hybrid Memory Allocator for Key-Value Stores	1
Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays	1
On Variable Strength Quantum ECC	0
Value Locality Based Approximation With ODIN	0
PreGNN: Hardware Acceleration to Take Preprocessing Off the Critical Path in Graph Neural Networks	0
Intelligent SSD Firmware for Zero-Overhead Journaling	0
Exploiting Direct Memory Operands in GPU Instructions	0
LSim: Fine-Grained Simulation Framework for Large-Scale Performance Evaluation	0
Characterizing and Understanding Defense Methods for GNNs on GPUs	0
DRAMA: Commodity DRAM based Content Addressable Memory	0
A Hardware-Friendly Tiled Singular-Value Decomposition-Based Matrix Multiplication for Transformer-Based Models	0
Structured Combinators for Efficient Graph Reduction	0
TURBULENCE: Complexity-effective Out-of-order Execution on GPU with Distance-based ISA	0
Efficient Memory Layout for Pre-Alignment Filtering of Long DNA Reads Using Racetrack Memory	0
Reducing the Silicon Area Overhead of Counter-Based Rowhammer Mitigations	0
Revisiting Browser Performance Benchmarking From an Architectural Perspective	0
Fast Performance Prediction for Efficient Distributed DNN Training	0
Chopping off the Tail: Bounded Non-Determinism for Real-Time Accelerators	0
Speculative Multi-Level Access in LSM Tree-Based KV Store	0
FPGA-Accelerated Data Preprocessing for Personalized Recommendation Systems	0
2021 Index IEEE Computer Architecture Letters Vol. 20	0
DeMM: A Decoupled Matrix Multiplication Engine Supporting Relaxed Structured Sparsity	0
MQSim-E: An Enterprise SSD Simulator	0
HAMMER: Hardware-Friendly Approximate Computing for Self-Attention With Mean-Redistribution And Linearization	0
Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator	0
LADIO: Leakage-Aware Direct I/O for I/O-Intensive Workloads	0
Voltage Noise Mitigation With Barrier Approximation	0
Enhancing the Reach and Reliability of Quantum Annealers by Pruning Longer Chains	0
Unleashing the Potential of PIM: Accelerating Large Batched Inference of Transformer-Based Generative Models	0
DNA Pre-Alignment Filter Using Processing Near Racetrack Memory	0
LMT: Accurate and Resource-Scalable Slowdown Prediction	0
Enhancing DNN Training Efficiency Via Dynamic Asymmetric Architecture	0
Supporting a Virtual Vector Instruction Set on a Commercial Compute-in-SRAM Accelerator	0
Adapting In Situ Accelerators for Sparsity with Granular Matrix Reordering	0
FullPack: Full Vector Utilization for Sub-Byte Quantized Vector-Matrix Multiplication on General Purpose CPUs	0
A Study of Memory Placement on Hardware-Assisted Tiered Memory Systems	0
CoreNap: Energy Efficient Core Allocation for Latency-Critical Workloads	0
Redundant Array of Independent Memory Devices	0
Ensuring Data Confidentiality in eADR-Based NVM Systems	0
Design of a High-Performance, High-Endurance Key-Value SSD for Large-Key Workloads	0
Accelerating Deep Reinforcement Learning via Phase-Level Parallelism for Robotics Applications	0
Guard Cache: Creating Noisy Side-Channels	0
The Jaseci Programming Paradigm and Runtime Stack: Building Scale-Out Production Applications Easy and Fast	0
Architectural Security Regulation	0
Guessing Outputs of Dynamically Pruned CNNs Using Memory Access Patterns	0
DVFaaS: Leveraging DVFS for FaaS Workflows	0
Improving Energy-efficiency of Capsule Networks on Modern GPUs	0
T-CAT: Dynamic Cache Allocation for Tiered Memory Systems With Memory Interleaving	0
Toward Practical 128-Bit General Purpose Microarchitectures	0
SSE: Security Service Engines to Accelerate Enclave Performance in Secure Multicore Processors	0
Probability-Based Address Translationfor Flash SSDs	0
SmartIndex: Learning to Index Caches to Improve Performance	0
Achieving Forward Progress Guarantee in Small Hardware Transactions	0
eDKM: An Efficient and Accurate Train-Time Weight Clustering for Large Language Models	0
2020 Index IEEE Computer Architecture Letters Vol. 19	0
Exploiting Intrinsic Redundancies in Dynamic Graph Neural Networks for Processing Efficiency	0
Primate: A Framework to Automatically Generate Soft Processors for Network Applications	0
Hardware Accelerated Reusable Merkle Tree Generation for Bitcoin Blockchain Headers	0
Simulating Our Way to Safer Software: A Tale of Integrating Microarchitecture Simulation and Leakage Estimation Modeling	0
Architectural Implications of GNN Aggregation Programming Abstractions	0
Hy-Sched: A Simple Hyperthreading-Aware Thread to Core Allocation Strategy	0
Hardware-Implemented Lightweight Accelerator for Large Integer Polynomial Multiplication	0
Mitigating Timing-Based NoC Side-Channel Attacks With LLC Remapping	0
In-Memory Versioning (IMV)	0
Open-Source Hardware Memory Protection Engine Integrated With NVMM Simulator	0
Overcoming Memory Capacity Wall of GPUs With Heterogeneous Memory Stack	0
Containerized In-Storage Processing Model and Hardware Acceleration for Fully-Flexible Computational SSDs	0
NoHammer: Preventing Row Hammer With Last-Level Cache Management	0

Exploring the Latency Sensitivity of Cache Replacement Policies	0
Pulley: An Algorithm/Hardware Co-Optimization for In-Memory Sorting	0
Tulip: Turn-Free Low-Power Network-on-Chip	0
An Intermediate Language for General Sparse Format Customization	0
SEMS: Scalable Embedding Memory System for Accelerating Embedding-Based DNNs	0
Smart Memory: Deep Learning Acceleration In 3D-Stacked Memories	0
ADT: Aggressive Demotion and Promotion for Tiered Memory	0
SoCurity: A Design Approach for Enhancing SoC Security	0
Inter-Temperature Bandwidth Reduction in Cryogenic QAOA Machines	0
Learned Performance Model for SSD	0
A Quantum Computer Trusted Execution Environment	0
Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems	0
R.i.p. Geomean Speedup Use Equal-Work (Or Equal-Time) Harmonic Mean Speedup Instead	0
The Mirage of Breaking MIRAGE: Analyzing the Modeling Pitfalls in Emerging “Attacks” on MIRAGE	0
RIO: ROB-Centric In-Order Modeling of Out-of-Order Processors	0
Baobab Merkle Tree for Efficient Secure Memory	0
Kobold: Simplified Cache Coherence for Cache-Attached Accelerators	0
Towards Improved Power Management in Cloud GPUs	0
JANM-IK: Jacobian Argumented Nelder-Mead Algorithm for Inverse Kinematics and Its Hardware Acceleration	0
UDIR: Towards a Unified Compiler Framework for Reconfigurable Dataflow Architectures	0
A Flexible Embedding-Aware Near Memory Processing Architecture for Recommendation System	0
Towards an Accelerator for Differential and Algebraic Equations Useful to Scientists	0
TokenSmart: Distributed, Scalable Power Management in the Many-Core Era	0
LINAC: A Spatially Linear Accelerator for Convolutional Neural Networks	0
Hardware-Assisted Code-Pointer Tagging for Forward-Edge Control-Flow Integrity	0
Address Scaling: Architectural Support for Fine-Grained Thread-Safe Metadata Management	0
Direct-Coding DNA With Multilevel Parallelism	0
RouteReplies: Alleviating Long Latency in Many-Chip-Module GPUs	0