IEEE Computer Architecture Letters

Papers
(The median citation count of IEEE Computer Architecture Letters is 0. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-02-01 to 2025-02-01.)
ArticleCitations
A Model for Scalable and Balanced Accelerators for Graph Processing20
Characterization and Implementation of Radar System Applications on a Reconfigurable Dataflow Architecture12
Baobab Merkle Tree for Efficient Secure Memory9
FullPack: Full Vector Utilization for Sub-Byte Quantized Matrix-Vector Multiplication on General Purpose CPUs8
GPU-centric Memory Tiering for LLM Serving with NVIDIA Grace Hopper Superchip8
High-Performance Winograd Based Accelerator Architecture for Convolutional Neural Network8
IntervalSim++: Enhanced Interval Simulation for Unbalanced Processor Designs8
Redundant Array of Independent Memory Devices7
Address Scaling: Architectural Support for Fine-Grained Thread-Safe Metadata Management7
BTB-X: A Storage-Effective BTB Organization7
A Case Study of a DRAM-NVM Hybrid Memory Allocator for Key-Value Stores7
Revisiting Browser Performance Benchmarking From an Architectural Perspective6
SmartIndex: Learning to Index Caches to Improve Performance6
Toward Practical 128-Bit General Purpose Microarchitectures6
Intelligent SSD Firmware for Zero-Overhead Journaling6
Speculative Multi-Level Access in LSM Tree-Based KV Store6
Guessing Outputs of Dynamically Pruned CNNs Using Memory Access Patterns5
Runtime Support for Accelerating CNN Models on Digital DRAM Processing-in-Memory Hardware5
Enhancing DNN Training Efficiency Via Dynamic Asymmetric Architecture5
Structured Combinators for Efficient Graph Reduction5
The Importance of Generalizability in Machine Learning for Systems4
Approximate Multiplier Design With LFSR-Based Stochastic Sequence Generators for Edge AI4
Near-Data Processing in Memory Expander for DNN Acceleration on GPUs4
Analysis of Data Transfer Bottlenecks in Commercial PIM Systems: A Study With UPMEM-PIM4
DeMM: A Decoupled Matrix Multiplication Engine Supporting Relaxed Structured Sparsity4
Open-Source Hardware Memory Protection Engine Integrated With NVMM Simulator4
Hungarian Qubit Assignment for Optimized Mapping of Quantum Circuits on Multi-Core Architectures4
R.I.P. Geomean Speedup Use Equal-Work (Or Equal-Time) Harmonic Mean Speedup Instead4
Smart Memory: Deep Learning Acceleration in 3D-Stacked Memories4
On Variable Strength Quantum ECC4
Hashing ATD Tags for Low-Overhead Safe Contention Monitoring4
Computational CXL-Memory Solution for Accelerating Memory-Intensive Applications3
NoHammer: Preventing Row Hammer With Last-Level Cache Management3
Learned Performance Model for SSD3
Proactive Embedding on Cold Data for Deep Learning Recommendation Model Training3
A Case for Hardware Memoization in Server CPUs3
An Area Efficient Architecture of a Novel Chaotic System for High Randomness Security in e-Health3
GATe: Streamlining Memory Access and Communication to Accelerate Graph Attention Network With Near-Memory Processing3
GraNDe: Near-Data Processing Architecture With Adaptive Matrix Mapping for Graph Convolutional Networks3
LADIO: Leakage-Aware Direct I/O for I/O-Intensive Workloads2
Towards an Accelerator for Differential and Algebraic Equations Useful to Scientists2
Simulating Our Way to Safer Software: A Tale of Integrating Microarchitecture Simulation and Leakage Estimation Modeling2
Exploring PIM Architecture for High-Performance Graph Pattern Mining2
Accelerating Programmable Bootstrapping Targeting Contemporary GPU Microarchitecture2
SPAM: Streamlined Prefetcher-Aware Multi-Threaded Cache Covert-Channel Attack2
Exploiting Intrinsic Redundancies in Dynamic Graph Neural Networks for Processing Efficiency2
BayesTuner: Leveraging Bayesian Optimization For DNN Inference Configuration Selection2
UDIR: Towards a Unified Compiler Framework for Reconfigurable Dataflow Architectures2
Hardware-Implemented Lightweight Accelerator for Large Integer Polynomial Multiplication2
Decoupled SSD: Reducing Data Movement on NAND-Based Flash SSD2
Efficient Implementation of Knuth Yao Sampler on Reconfigurable Hardware2
Towards Improved Power Management in Cloud GPUs2
HAMMER: Hardware-Friendly Approximate Computing for Self-Attention With Mean-Redistribution And Linearization2
Managing Prefetchers With Deep Reinforcement Learning2
Unleashing the Potential of PIM: Accelerating Large Batched Inference of Transformer-Based Generative Models2
eDKM: An Efficient and Accurate Train-Time Weight Clustering for Large Language Models2
Characterization and Analysis of Text-to-Image Diffusion Models2
Accelerating Page Migrations in Operating Systems with Intel DSA2
Characterizing Machine Learning-Based Runtime Prefetcher Selection1
Hardware Accelerated Reusable Merkle Tree Generation for Bitcoin Blockchain Headers1
GCStack: A GPU Cycle Accounting Mechanism for Providing Accurate Insight Into GPU Performance1
Editorial: A Letter From the Editor-in-Chief of IEEE Computer Architecture Letters1
DRAMA: Commodity DRAM Based Content Addressable Memory1
DAMARU: A Denial-of-Service Attack on Randomized Last-Level Caches1
A Pre-Silicon Approach to Discovering Microarchitectural Vulnerabilities in Security Critical Applications1
Chopping off the Tail: Bounded Non-Determinism for Real-Time Accelerators1
SoCurity: A Design Approach for Enhancing SoC Security1
A Quantitative Analysis of State Space Model-Based Large Language Model: Study of Hungry Hungry Hippos1
HBM3 RAS: Enhancing Resilience at Scale1
SparseLeakyNets: Classification Prediction Attack Over Sparsity-Aware Embedded Neural Networks Using Timing Side-Channel Information1
Characterization and Analysis of the 3D Gaussian Splatting Rendering Pipeline1
Data-Aware Compression of Neural Networks1
Architecting Compatible PIM Protocol for CPU-PIM Collaboration1
Improving Energy-Efficiency of Capsule Networks on Modern GPUs1
An Intermediate Language for General Sparse Format Customization1
Design of a High-Performance, High-Endurance Key-Value SSD for Large-Key Workloads1
SPGPU: Spatially Programmed GPU1
Empirical Architectural Analysis on Performance Scalability of Petascale All-Flash Storage Systems1
Last-Level Cache Insertion and Promotion Policy in the Presence of Aggressive Prefetching1
Advancing Compilation of DNNs for FPGAs Using Operation Set Architectures1
LT-PIM: An LUT-Based Processing-in-DRAM Architecture With RowHammer Self-Tracking1
By-Software Branch Prediction in Loops1
The Jaseci Programming Paradigm and Runtime Stack: Building Scale-Out Production Applications Easy and Fast1
Characterizing and Understanding HGNNs on GPUs1
LSim: Fine-Grained Simulation Framework for Large-Scale Performance Evaluation1
2021 Index IEEE Computer Architecture Letters Vol. 201
SCALES: SCALable and Area-Efficient Systolic Accelerator for Ternary Polynomial Multiplication1
Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems0
PINSim: A Processing In- and Near-Sensor Simulator to Model Intelligent Vision Sensors0
X-ray: Discovering DRAM Internal Structure and Error Characteristics by Issuing Memory Commands0
Overcoming Memory Capacity Wall of GPUs With Heterogeneous Memory Stack0
Straw: A Stress-Aware WL-Based Read Reclaim Technique for High-Density NAND Flash-Based SSDs0
Supporting a Virtual Vector Instruction Set on a Commercial Compute-in-SRAM Accelerator0
Modeling Periodic Energy-Harvesting Computing Systems0
Characterization and Analysis of Deep Learning for 3D Point Cloud Analytics0
DVFaaS: Leveraging DVFS for FaaS Workflows0
Making a Better Use of Caches for GCN Accelerators with Feature Slicing and Automatic Tile Morphing0
RouteReplies: Alleviating Long Latency in Many-Chip-Module GPUs0
Fast Performance Prediction for Efficient Distributed DNN Training0
ADT: Aggressive Demotion and Promotion for Tiered Memory0
SEMS: Scalable Embedding Memory System for Accelerating Embedding-Based DNNs0
A Case for In-Memory Random Scatter-Gather for Fast Graph Processing0
gem5-accel: A Pre-RTL Simulation Toolchain for Accelerator Architecture Validation0
Accelerators & Security: The Socket Approach0
FPGA-Based AI Smart NICs for Scalable Distributed AI Training Systems0
Reorder Buffer Contention: A Forward Speculative Interference Attack for Speculation Invariant Instructions0
STONNE: Enabling Cycle-Level Microarchitectural Simulation for DNN Inference Accelerators0
The Mirage of Breaking MIRAGE: Analyzing the Modeling Pitfalls in Emerging “Attacks” on MIRAGE0
Inter-Temperature Bandwidth Reduction in Cryogenic QAOA Machines0
A Flexible Hybrid Interconnection Design for High-Performance and Energy-Efficient Chiplet-Based Systems0
Characterizing and Understanding Defense Methods for GNNs on GPUs0
SLO-Aware GPU DVFS for Energy-Efficient LLM Inference Serving0
Hardware-Accelerated Kernel-Space Memory Compression Using Intel QAT0
LTE: Lightweight and Time-Efficient Hardware Encoder for Post-Quantum Scheme HQC0
MajorK: Majority Based kmer Matching in Commodity DRAM0
A First-Order Model to Assess Computer Architecture Sustainability0
FPGA-Accelerated Data Preprocessing for Personalized Recommendation Systems0
RoPIM: A Processing-in-Memory Architecture for Accelerating Rotary Positional Embedding in Transformer Models0
CoreNap: Energy Efficient Core Allocation for Latency-Critical Workloads0
MPU-Sim: A Simulator for In-DRAM Near-Bank Processing Architectures0
Stride Equality Prediction for Value Speculation0
Infinity Stream: Enabling Transparent and Automated In-Memory Computing0
Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays0
Characterizing and Understanding Distributed GNN Training on GPUs0
OpenMDS: An Open-Source Shell Generation Framework for High-Performance Design on Xilinx Multi-Die FPGAs0
Quantum Assertion Scheme for Assuring Qudit Robustness0
Adaptive Web Browsing on Mobile Heterogeneous Multi-cores0
Achieving Forward Progress Guarantee in Small Hardware Transactions0
Primate: A Framework to Automatically Generate Soft Processors for Network Applications0
Energy-Efficient Bayesian Inference Using Bitstream Computing0
Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator0
Ensuring Data Confidentiality in eADR-Based NVM Systems0
JANM-IK: Jacobian Argumented Nelder-Mead Algorithm for Inverse Kinematics and its Hardware Acceleration0
Heterogeneity-Aware Scheduling on SoCs for Autonomous Vehicles0
Exploiting Intel Advanced Matrix Extensions (AMX) for Large Language Model Inference0
Guard Cache: Creating Noisy Side-Channels0
Kobold: Simplified Cache Coherence for Cache-Attached Accelerators0
A Hardware-Friendly Tiled Singular-Value Decomposition-Based Matrix Multiplication for Transformer-Based Models0
Characterizing and Understanding End-to-End Multi-Modal Neural Networks on GPUs0
SSE: Security Service Engines to Accelerate Enclave Performance in Secure Multicore Processors0
Dramaton: A Near-DRAM Accelerator for Large Number Theoretic Transforms0
LINAC: A Spatially Linear Accelerator for Convolutional Neural Networks0
ZoneBuffer: An Efficient Buffer Management Scheme for ZNS SSDs0
Lightweight Hardware Implementation of Binary Ring-LWE PQC Accelerator0
Hardware-Assisted Code-Pointer Tagging for Forward-Edge Control-Flow Integrity0
Architectural Security Regulation0
Octopus: A Cycle-Accurate Cache System Simulator0
TURBULENCE: Complexity-Effective Out-of-Order Execution on GPU With Distance-Based ISA0
Containerized In-Storage Processing Model and Hardware Acceleration for Fully-Flexible Computational SSDs0
SmartQuant: CXL-Based AI Model Store in Support of Runtime Configurable Weight Quantization0
Efficient Memory Layout for Pre-Alignment Filtering of Long DNA Reads Using Racetrack Memory0
Exploring the Latency Sensitivity of Cache Replacement Policies0
T-CAT: Dynamic Cache Allocation for Tiered Memory Systems With Memory Interleaving0
Understanding the Implication of Non-Volatile Memory for Large-Scale Graph Neural Network Training0
Direct-Coding DNA With Multilevel Parallelism0
LV: Latency-Versatile Floating-Point Engine for High-Performance Deep Neural Networks0
Reducing the Silicon Area Overhead of Counter-Based Rowhammer Mitigations0
ONNXim: A Fast, Cycle-Level Multi-Core NPU Simulator0
Mitigating Timing-Based NoC Side-Channel Attacks With LLC Remapping0
2024 Reviewers List0
Accelerating Deep Reinforcement Learning via Phase-Level Parallelism for Robotics Applications0
A Quantum Computer Trusted Execution Environment0
A Flexible Embedding-Aware Near Memory Processing Architecture for Recommendation System0
DNA Pre-Alignment Filter Using Processing Near Racetrack Memory0
PreGNN: Hardware Acceleration to Take Preprocessing Off the Critical Path in Graph Neural Networks0
Toward Scalable RDMA through Resource Prefetching0
Tulip: Turn-Free Low-Power Network-on-Chip0
The Case for Replication-Aware Memory-Error Protection in Disaggregated Memory0
WPC: Whole-Picture Workload Characterization Across Intermediate Representation, ISA, and Microarchitecture0
LMT: Accurate and Resource-Scalable Slowdown Prediction0
MQSim-E: An Enterprise SSD Simulator0
XLA-NDP: Efficient Scheduling and Code Generation for Deep Learning Model Training on Near-Data Processing Memory0
Multi-Prediction Compression: An Efficient and Scalable Memory Compression Framework for GP-GPU0
Enhancing the Reach and Reliability of Quantum Annealers by Pruning Longer Chains0
Instruction Criticality Based Energy-Efficient Hardware Data Prefetching0
Modeling DRAM Timing in Parallel Simulators With Immediate-Response Memory Model0
Balancing Performance Against Cost and Sustainability in Multi-Chip-Module GPUs0
Electra: Eliminating the Ineffectual Computations on Bitmap Compressed Matrices0
Accelerating Graph Processing With Lightweight Learning-Based Data Reordering0
In-Memory Versioning (IMV)0
Dynamic Optimization of On-Chip Memories for HLS Targeting Many-Accelerator Platforms0
Exploiting Direct Memory Operands in GPU Instructions0
SmaQ: Smart Quantization for DNN Training by Exploiting Value Clustering0
TeleVM: A Lightweight Virtual Machine for RISC-V Architecture0
Cycle-Oriented Dynamic Approximation: Architectural Framework to Meet Performance Requirements0
Pulley: An Algorithm/Hardware Co-Optimization for In-Memory Sorting0
Architectural Implications of GNN Aggregation Programming Abstractions0
Cooperative Memory Deduplication with Intel Data Streaming Accelerator0
Scale-Model Simulation0
DRAM-CAM: General-Purpose Bit-Serial Exact Pattern Matching0
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