OOIR: Observatory of International Research

Papers

(The median citation count of IEEE Computer Architecture Letters is 1. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-01-01 to 2026-01-01.)

Article	Citations
Old is Gold: Optimizing Single-Threaded Applications With ExGen-Malloc	60
The Architectural Sustainability Indicator	33
Toward Practical 128-Bit General Purpose Microarchitectures	19
Speculative Multi-Level Access in LSM Tree-Based KV Store	19
A Characterization of Generative Recommendation Models: Study of Hierarchical Sequential Transduction Unit	17
Characterization and Analysis of Text-to-Image Diffusion Models	17
Accelerating Programmable Bootstrapping Targeting Contemporary GPU Microarchitecture	16
SCALES: SCALable and Area-Efficient Systolic Accelerator for Ternary Polynomial Multiplication	16
Time Series Machine Learning Models for Precise SSD Access Latency Prediction	16
Context-Aware Set Dueling for Dynamic Policy Arbitration	15
MoSKA: Mixture of Shared KV Attention for Efficient Long-Sequence LLM Inference	13
A Quantitative Analysis of Mamba-2-Based Large Language Model: Study of State Space Duality	13
In-Depth Characterization of Machine Learning on an Optimized Multi-Party Computing Library	13
Breaking the HBM Bit Cost Barrier: Domain-Specific ECC for AI Inference Infrastructure	13
SoCurity: A Design Approach for Enhancing SoC Security	10
OASIS: Outlier-Aware KV Cache Clustering for Scaling LLM Inference in CXL Memory Systems	10
Improving Energy-Efficiency of Capsule Networks on Modern GPUs	10
Straw: A Stress-Aware WL-Based Read Reclaim Technique for High-Density NAND Flash-Based SSDs	10
2021 Index IEEE Computer Architecture Letters Vol. 20	10
AiDE: Attention-FFN Disaggregated Execution for Cost-Effective LLM Decoding on CXL-PNM	10
Exploring KV Cache Quantization in Multimodal Large Language Model Inference	9
A Flexible Embedding-Aware Near Memory Processing Architecture for Recommendation System	9
Exploring the DIMM PIM Architecture for Accelerating Time Series Analysis	9
RouteReplies: Alleviating Long Latency in Many-Chip-Module GPUs	8
A Case for In-Memory Random Scatter-Gather for Fast Graph Processing	7

REDIT: Redirection-Enabled Memory-Side Directory Architecture for CXL Memory Fabric	7
StreamDQ: HBM-Integrated On-the-Fly DeQuantization via Memory Load for Large Language Models	7
In-Memory Versioning (IMV)	7
Disaggregated Speculative Decoding for Carbon-Efficient LLM Serving	6
Improving Performance on Tiered Memory With Semantic Data Placement	6
Mitigating Timing-Based NoC Side-Channel Attacks With LLC Remapping	6
Exploiting Intel Advanced Matrix Extensions (AMX) for Large Language Model Inference	6
Security Helper Chiplets: A New Paradigm for Secure Hardware Monitoring	6
Thread-Adaptive: High-Throughput Parallel Architectures of SLH-DSA on GPUs	6
QuArch: A Question-Answering Dataset for AI Agents in Computer Architecture	6
PUDTune: Multi-Level Charging for High-Precision Calibration in Processing-Using-DRAM	6
NoHammer: Preventing Row Hammer With Last-Level Cache Management	5
Efficient Deadlock Avoidance by Considering Stalling, Message Dependencies, and Topology	5
Managing Prefetchers With Deep Reinforcement Learning	5
pNet-gem5: Full-System Simulation With High-Performance Networking Enabled by Parallel Network Packet Processing	5
DeMM: A Decoupled Matrix Multiplication Engine Supporting Relaxed Structured Sparsity	5
LADIO: Leakage-Aware Direct I/O for I/O-Intensive Workloads	5
Accelerating Deep Reinforcement Learning via Phase-Level Parallelism for Robotics Applications	5
High-Performance Winograd Based Accelerator Architecture for Convolutional Neural Network	5
Memory-Centric MCM-GPU Architecture	5
RAESC: A Reconfigurable AES Countermeasure Architecture for RISC-V With Enhanced Power Side-Channel Resilience	5
SparseLeakyNets: Classification Prediction Attack Over Sparsity-Aware Embedded Neural Networks Using Timing Side-Channel Information	4
FPGA-Accelerated Data Preprocessing for Personalized Recommendation Systems	4
SSD Offloading for LLM Mixture-of-Experts Weights Considered Harmful in Energy Efficiency	4
Primate: A Framework to Automatically Generate Soft Processors for Network Applications	4
Adaptive Web Browsing on Mobile Heterogeneous Multi-cores	4
ZoneBuffer: An Efficient Buffer Management Scheme for ZNS SSDs	4
PreGNN: Hardware Acceleration to Take Preprocessing Off the Critical Path in Graph Neural Networks	4
A Flexible Hybrid Interconnection Design for High-Performance and Energy-Efficient Chiplet-Based Systems	4
Fast Performance Prediction for Efficient Distributed DNN Training	4
Enhancing the Reach and Reliability of Quantum Annealers by Pruning Longer Chains	4
SSE: Security Service Engines to Accelerate Enclave Performance in Secure Multicore Processors	3
Exploring Volatile FPGAs Potential for Accelerating Energy-Harvesting IoT Applications	3
LeakDiT: Diffusion Transformers for Trace-Augmented Side-Channel Analysis	3
SEMS: Scalable Embedding Memory System for Accelerating Embedding-Based DNNs	3
Camulator: A Lightweight and Extensible Trace-Driven Cache Simulator for Embedded Multicore SoCs	3
Understanding the Performance Behaviors of End-to-End Protein Design Pipelines on GPUs	3
T-CAT: Dynamic Cache Allocation for Tiered Memory Systems With Memory Interleaving	3
CABANA : Cluster-Aware Query Batching for Accelerating Billion-Scale ANNS With Intel AMX	3
Enabling Cost-Efficient LLM Inference on Mid-Tier GPUs With NMP DIMMs	3
Guard Cache: Creating Noisy Side-Channels	3
Accelerators & Security: The Socket Approach	3
Direct-Coding DNA With Multilevel Parallelism	3
A Quantum Computer Trusted Execution Environment	3
Minimal Counters, Maximum Insight: Simplifying System Performance With HPC Clusters for Optimized Monitoring	2
A First-Order Model to Assess Computer Architecture Sustainability	2
Unleashing the Potential of PIM: Accelerating Large Batched Inference of Transformer-Based Generative Models	2
On Internally Tagged Instruction Set Architectures	2
FullPack: Full Vector Utilization for Sub-Byte Quantized Matrix-Vector Multiplication on General Purpose CPUs	2
A Case Study of a DRAM-NVM Hybrid Memory Allocator for Key-Value Stores	2

Accelerating Page Migrations in Operating Systems With Intel DSA	2
Reducing the Silicon Area Overhead of Counter-Based Rowhammer Mitigations	2
IntervalSim++: Enhanced Interval Simulation for Unbalanced Processor Designs	2
PINSim: A Processing In- and Near-Sensor Simulator to Model Intelligent Vision Sensors	2
EgDiff: An Enhanced Global Load Value Predictor	2
R.I.P. Geomean Speedup Use Equal-Work (Or Equal-Time) Harmonic Mean Speedup Instead	2
Cost-Effective Extension of DRAM-PIM for Group-Wise LLM Quantization	2
Hungarian Qubit Assignment for Optimized Mapping of Quantum Circuits on Multi-Core Architectures	2
Redundant Array of Independent Memory Devices	2
Approximate Multiplier Design With LFSR-Based Stochastic Sequence Generators for Edge AI	2
Architectural Implications of GNN Aggregation Programming Abstractions	2
Overcoming Memory Capacity Wall of GPUs With Heterogeneous Memory Stack	2
DRAM-CAM: General-Purpose Bit-Serial Exact Pattern Matching	2
gem5-accel: A Pre-RTL Simulation Toolchain for Accelerator Architecture Validation	2
Per-Row Activation Counting on Real Hardware: Demystifying Performance Overheads	2
Analyzing and Exploiting Memory Hierarchy Parallelism With MLP Stacks	2
Characterization and Implementation of Radar System Applications on a Reconfigurable Dataflow Architecture	2
Computational CXL-Memory Solution for Accelerating Memory-Intensive Applications	2
Enhancing DNN Training Efficiency Via Dynamic Asymmetric Architecture	2
Energy-Efficient Bayesian Inference Using Bitstream Computing	2
FPGA-Based AI Smart NICs for Scalable Distributed AI Training Systems	2
Characterization and Analysis of the 3D Gaussian Splatting Rendering Pipeline	1
Halis: A Hardware-Software Co-Designed Near-Cache Accelerator for Graph Pattern Mining	1
An Intermediate Language for General Sparse Format Customization	1
Exploiting Intel AMX Power Gating	1
Exploiting Direct Memory Operands in GPU Instructions	1
Low-Latency PIM Accelerator for Edge LLM Inference	1
Address Scaling: Architectural Support for Fine-Grained Thread-Safe Metadata Management	1
Architectural Security Regulation	1
Characterizing and Understanding End-to-End Multi-Modal Neural Networks on GPUs	1
MQSim-E: An Enterprise SSD Simulator	1
Characterizing and Understanding HGNNs on GPUs	1
A Partial Tag–Data Decoupled Architecture for Last-Level Cache Optimization	1
eDKM: An Efficient and Accurate Train-Time Weight Clustering for Large Language Models	1
MOST: Memory Oversubscription-Aware Scheduling for Tensor Migration on GPU Unified Storage	1
Enhancing DCIM Efficiency with Multi-Storage-Row Architecture for Edge AI Workloads	1
HINT: A Hardware Platform for Intra-Host NIC Traffic and SmartNIC Emulation	1
On Variable Strength Quantum ECC	1
Supporting a Virtual Vector Instruction Set on a Commercial Compute-in-SRAM Accelerator	1
TeleVM: A Lightweight Virtual Machine for RISC-V Architecture	1
Approximate SFQ-Based Computing Architecture Modeling With Device-Level Guidelines	1
Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays	1
A Multiple-Aspect Optimal CNN Accelerator in Top1 Accuracy, Performance, and Power Efficiency	1
Pyramid: Accelerating LLM Inference With Cross-Level Processing-in-Memory	1
MajorK: Majority Based kmer Matching in Commodity DRAM	1
A Pre-Silicon Approach to Discovering Microarchitectural Vulnerabilities in Security Critical Applications	1
Accelerating LLM Inference via Dynamic KV Cache Placement in Heterogeneous Memory System	1
CGR-NPU: A Hybrid CGRA and NPU Architecture for Adaptive Neural Computing Workloads	1
A Data Prefetcher-Based 1000-Core RISC-V Processor for Efficient Processing of Graph Neural Networks	1
Cache and Near-Data Co-Design for Chiplets	1
A Case for Hardware Memoization in Server CPUs	1
Balancing Performance Against Cost and Sustainability in Multi-Chip-Module GPUs	1
MixDiT: Accelerating Image Diffusion Transformer Inference With Mixed-Precision MX Quantization	1
A Hardware-Friendly Tiled Singular-Value Decomposition-Based Matrix Multiplication for Transformer-Based Models	1
LSim: Fine-Grained Simulation Framework for Large-Scale Performance Evaluation	1
Tulip: Turn-Free Low-Power Network-on-Chip	1
Electra: Eliminating the Ineffectual Computations on Bitmap Compressed Matrices	1
X-PPR: Post Package Repair for CXL Memory	1
Characterizing and Understanding Distributed GNN Training on GPUs	1
Amethyst: Reducing Data Center Emissions With Dynamic Autotuning and VM Management	1