OOIR: Observatory of International Research

Papers

(The median citation count of ACM Journal on Emerging Technologies in Computing Systems is 3. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-05-01 to 2025-05-01.)

Article	Citations
Introduction to the Special Issue on Hardware-Assisted Security for Emerging Internet of Things	65
Breaking On-Chip Communication Anonymity Using Flow Correlation Attacks	60
EM-X-DL: Efficient Cross-device Deep Learning Side-channel Attack With Noisy EM Signatures	55
STAP: An Architecture and Design Tool for Automata Processing on Memristor TCAMs	40
A Reconfigurable Multiplier for Signed Multiplications with Asymmetric Bit-Widths	33
Defending against Adversarial Attacks in Deep Learning with Robust Auxiliary Classifiers Utilizing Bit-plane Slicing	31
Test Points for Online Monitoring of Quantum Circuits	28
STIFT: A Spatio-Temporal Integrated Folding Tree for Efficient Reductions in Flexible DNN Accelerators	20
Sorting in Memristive Memory	20
Low-Rank Gradient Descent for Memory-Efficient Training of Deep In-Memory Arrays	19
Software-driven Security Attacks: From Vulnerability Sources to Durable Hardware Defenses	19
A Survey Describing Beyond Si Transistors and Exploring Their Implications for Future Processors	19
A Cost-Effective Built-In Self-Test Mechanism for Post-Manufacturing TSV Defects in 3D ICs	18
A Survey on Silicon Photonics for Deep Learning	17
All-spin PUF: An Area-efficient and Reliable PUF Design with Signature Improvement for Spin-transfer Torque Magnetic Cell-based All-spin Circuits	17
OpenQL: A Portable Quantum Programming Framework for Quantum Accelerators	17
The Bitlet Model: A Parameterized Analytical Model to Compare PIM and CPU Systems	17
ANT-UNet: Accurate and Noise-Tolerant Segmentation for Pathology Image Processing	17
Introduction to the Special Issue on Hardware and Algorithms for Efficient Machine Learning—Part 2	16
NORM: An FPGA-based Non-volatile Memory Emulation Framework for Intermittent Computing	16
SkyBridge 2.0: A Fine-grained Vertical 3D-IC Technology for Future ICs	15
Secure and Lightweight Authentication Protocol Using PUF for the IoT-based Wireless Sensor Network	14
Unsupervised Digit Recognition Using Cosine Similarity In A Neuromemristive Competitive Learning System	12
The Uncertainty of Side-channel Analysis: A Way to Leverage from Heuristics	12
DINOS: Data INspired Oligo Synthesis for DNA Data Storage	12

Timing-Optimized Hardware Implementation to Accelerate Polynomial Multiplication in the NTRU Algorithm	12
A Fast Object Detection-Based Framework for Via Modeling on PCB X-Ray CT Images	11
Hardware-accelerated Simulation-based Inference of Stochastic Epidemiology Models for COVID-19	11
Compressing RNNs to Kilobyte Budget for IoT Devices Using Kronecker Products	11
Introduction to the Special Issue on Monolithic 3D: Technology, Design and Computing Systems Applications Perspectives	11
Dynamic Regularization on Activation Sparsity for Neural Network Efficiency Improvement	10
Characterization of Timing-based Software Side-channel Attacks and Mitigations on Network-on-Chip Hardware	10
Hardware Trust and Assurance through Reverse Engineering: A Tutorial and Outlook from Image Analysis and Machine Learning Perspectives	10
Image Complexity Guided Network Compression for Biomedical Image Segmentation	10
Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach	10
Integrated Power Signature Generation Circuit for IoT Abnormality Detection	10
A Neoteric Approach for Logic with Embedded Memory Leveraging Crosstalk Computing	9
Diverse, Neural Trojan Resilient Ecosystem of Neural Network IP	9
Analyzing Security Vulnerabilities Induced by High-level Synthesis	9
Accelerating On-Chip Training with Ferroelectric-Based Hybrid Precision Synapse	9
Virtualizing Existing Fluidic Programs	8
Enhancing Privacy in PUF-Cash through Multiple Trusted Third Parties and Reinforcement Learning	8
SRLL: Improving Security and Reliability with User-Defined Constraint-Aware Logic Locking	8
Robust and Attack Resilient Logic Locking with a High Application-Level Impact	8
Hardware Trojan Horse Detection through Improved Switching of Dormant Nets	7
Low-overhead Hardware Supervision for Securing an IoT Bluetooth-enabled Device: Monitoring Radio Frequency and Supply Voltage	7
B-open Defect: A Novel Defect Model in FinFET Technology	7
Introduction to the Special Issue on Design Automation for Quantum Computing	7
SAT-Based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs	7
Spiking-NeRF: Spiking Neural Network for Energy-Efficient Neural Rendering	6
A Quasi-digital QPSK Modulator Design for Biomedical Devices	6
PUF-based Digital Money with Propagation-of-Provenance and Offline Transfers between Two Parties	6
F-Bypass: A Low-Power Network-on-Chip Design Utilizing Bypass to Improve Network Connectivity	6
HDRLPIM: A Simulator for Hyper-Dimensional Reinforcement Learning Based on Processing In-Memory	6
A Spiking Neuromorphic Architecture Using Gated-RRAM for Associative Memory	6
Dynamic Reliability Management in Neuromorphic Computing	6
Applications and Challenges of AI in PCB X-ray Inspection: A Comprehensive Study	6
NN-Lock : A Lightweight Authorization to Prevent IP Threats of Deep Learning Models	6
A Novel Highly-Efficient Inexact Full Adder Cell for Motion and Edge Detection Systems of Image Processing in CNFET Technology	5
Digital Fault-based Built-in Self-test and Evaluation of Low Dropout Voltage Regulators	5
A Quality-assured Approximate Hardware Accelerators–based on Machine Learning and Dynamic Partial Reconfiguration	5
Building an Open Representation for Biological Protocols	5
Fusing In-storage and Near-storage Acceleration of Convolutional Neural Networks	5
Extreme Partial-Sum Quantization for Analog Computing-In-Memory Neural Network Accelerators	5
Reliable Constructions for the Key Generator of Code-based Post-quantum Cryptosystems on FPGA	5
Machine Learning Vulnerability Analysis of FPGA-based Ring Oscillator PUFs and Counter Measures	5
A ReRAM Memory Compiler for Monolithic 3D Integrated Circuits in a Carbon Nanotube Process	4
Photonic Networks-on-Chip Employing Multilevel Signaling: A Cross-Layer Comparative Study	4
Generation of Black-box Audio Adversarial Examples Based on Gradient Approximation and Autoencoders	4
Repercussions of Using DNN Compilers on Edge GPUs for Real Time and Safety Critical Systems: A Quantitative Audit	4
Towards Compact Modeling of Noisy Quantum Computers: A Molecular-Spin-Qubit Case of Study	4
Hardware Trojan Detection Using Unsupervised Deep Learning on Quantum Diamond Microscope Magnetic Field Images	4
AroMa : Evaluating Deep Learning Systems for Stealthy Integrity Attacks on Multi-tenant Accelerators	4
Towards a Truly Integrated Vector Processing Unit for Memory-bound Applications Based on a Cost-competitive Computational SRAM Design Solution	4
Improving the Quality of FPGA RO-PUF by Principal Component Analysis (PCA)	4

Direction-aggregated Attack for Transferable Adversarial Examples	4
Guest Editorial: ACM JETC Special Issue on Hardware-Aware Learning for Medical Applications	4
Guest Editorial: Computation-In-Memory (CIM): from Device to Applications	4
Optimizing 3D U-Net-based Brain Tumor Segmentation with Integer-arithmetic Deep Learning Accelerators	4
Genetic Cache: A Machine Learning Approach to Designing DRAM Cache Controllers in HBM Systems	4
Graphene-Based Artificial Synapses with Tunable Plasticity	4
AccHashtag : Accelerated Hashing for Detecting Fault-Injection Attacks on Embedded Neural Networks	4
Impact of On-chip Interconnect on In-memory Acceleration of Deep Neural Networks	3
Toward the Generation of Test Vectors for the Detection of Hardware Trojan Targeting Effective Switching Activity	3
SPLIT PUF: Efficient PUF Implementation Using Underutilized FPGA Resources	3
Towards All-optical Stochastic Computing Using Photonic Crystal Nanocavities	3
Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs	3
Introduction to the Special Issue on CAD for Security: Pre-silicon Security Sign-off Solutions Through Design Cycle	3
Towards Energy-Efficient Spiking Neural Networks: A Robust Hybrid CMOS-Memristive Accelerator	3
A Genetic-algorithm-based Approach to the Design of DCT Hardware Accelerators	3
Toward Practical Superconducting Accelerators for Machine Learning Using U-SFQ	3
A Deep Neural Network Accelerator using Residue Arithmetic in a Hybrid Optoelectronic System	3
Zallocator: A High Throughput Write-Optimized Persistent Allocator for Non-Volatile Memory	3
Parallel Computing of Graph-based Functions in ReRAM	3
On Securing Cryptographic ICs against Scan-based Attacks: A Hamming Weight Distribution Perspective	3
Power-based Attacks on Spatial DNN Accelerators	3
Hardware Trojan Detection Potential and Limits with the Quantum Diamond Microscope	3
Attack Mitigation of Hardware Trojans for Thermal Sensing via Micro-ring Resonator in Optical NoCs	3
Design-time Reference Current Generation for Robust Spintronic-based Neuromorphic Architecture	3