OOIR: Observatory of International Research

Papers

(The TQCC of IEEE Transactions on Circuits and Systems I-Regular Papers is 10. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-06-01 to 2026-06-01.)

Article	Citations
TechRxiv: Share Your Preprint Research with the World!	168
Learning, Optimization, and Implementation for Circuits and Systems driven by Artificial Intelligence	160
IEEE Open Access Publishing	126
Implementation of Group-Approximate Expectation Propagation Algorithm for Uplink MIMO-SCMA Detection Using 16-Point Codebook	121
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	120
Non-Linear Cyclic Variable Clock Feistel Bridge-Inspired Countermeasure for Securing RISC-V Crypto-Core Against Power Attacks	118
Digital Time-Domain Predistortion of Linear Periodically Time-Varying Effects and Its Application to a 100-GS/s Time-Interleaved CMOS DAC	102
Parallel Delta-Sigma Modulator-Based Digital Predistortion of Wideband RF Power Amplifiers	98
Welcome to a New Term in TCAS-I	98
A Compact One-Transistor-Multiple-RRAM Characterization Platform	87
Retraction Notice: Robustness Margins for Attainable Consensusability of Unstable Multi-Agent Systems: Output Consensus Protocols Over Directed Network Topology	86
A Wide-Range Inter-Wire De-Skewing for IL Warping Mitigation in Spatially Correlated Coded Signaling-Based Transceiver	85
An 11T1C Bit-Level-Sparsity-Aware Computing- in-Memory Macro With Adaptive Conversion Time and Computation Voltage	78
Fast Algorithms for Resistance Distances on Signed Graphs	78
A 1-GS/s 12-bit Pipelined-SAR ADC With Dither-Based Background Calibration of Interstage Gain and Comparator Offset in 28-nm CMOS	74
A Fully Symmetric Oscillator-Based CMOS Ising Machine Architecture With Successive Approximation Sampling and Power Efficient Solution Refinement	69
FREYA: A 0.023-mm²/Channel, 20.8- μW/Channel, Event-Driven 8-Channel SoC for Spiking End-to-End Sensing of Time-Sparse Biosignals	69
A Proximal ADMM-Based Distributed Optimal Energy Management Approach for Smart Grid With Stochastic Wind Power	68
Programmable Analog-to-Digital Converter Array Supporting Architecture Restructuring and Mode Concurrency	66
On the Efficacy and Vulnerabilities of Logic Locking in Tree-Based Machine Learning	65
An All NMOS KY-Boost Converter With Double Injection Control for Fast Line and Load Transient Response	64
Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference	63
Light-Weight Low-Latency Reconfigurable CORDIC Architecture With a New Non-Power-of-2 Angle Set of Microrotations	60
A 20 nW +0.8°C/-0.8°C Inaccuracy (3σ) Leakage-Based CMOS Temperature Sensor With Supply Sensitivity of 0.9°C/V	60
A New Macromodeling Method Based on Deep Gated Recurrent Unit Regularized With Gaussian Dropout for Nonlinear Circuits	60

Novel Optimized Implementations of Lightweight Cryptographic S-Boxes via SAT Solvers	60
Exploring Hybrid FitzHugh-Rinzel (FHR) Neuron Model Behavior: Cost-Effective FPGA Implementation for High-Frequency and High-Precision Matching by Electromagnetic Flux Effects	59
Design of Miniaturized Sub-6 GHz Rectifier With Self-Impedance Matching Technique	58
A 16.5-31 GHz Area-Efficient Tapered Tunable Transmission Line Phase Shifter	57
Adaptive Formation for Multiagent Systems Subject to Denial-of-Service Attacks	57
Frequency Response Model for Power Systems Including HVDC-Connected Offshore Wind Power With Communication-Free Frequency Control	57
Double-Ended Superposition Anti-Noise Resistance Monitoring Write Termination Scheme for Reliable Write Operation in STT-MRAM	57
Pipe-LPAQ: A Fully Pipelined Architecture for LPAQ Data Compression on FPGA	56
A Handgrip-Responsive mmWave Phased Array Antenna-PA Module With Antenna-Based Capacitive Sensor for EIRP Recovery via Adaptive Current Redistribution	56
A 4.25–8.45-GHz 67% Chirp-Fractional Bandwidth −121.5-dBc/Hz PN at 1-MHz 88-fs Jitter FMCW Synthesizer With Fractional-Bandwidth-Boosting and Phase-Noise-Cancellation Techniques	56
Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode	55
A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined ADCs	54
A Cryo-CMOS SAR ADC With FIA Sampling Driver Enabled by Cryogenic-Aware Back-Biasing	54
A Consistency Enhancement Technique for MIMO Power Amplifier Modules	54
Data-Driven Fault-Tolerant Control Framework for EV Dynamic Wireless Power Transfer System Based on Self-Learning Predictor	54
A Novel Design Method for CML Frequency Divider Based on C/I_d and G/I_d and Application for Quadrature-Injection	53
A Simultaneous Bidirectional Link With 6–12.8-Gb/s Forward and 12–25.6-Gb/s Backward Channels for System Chips Interconnects	53
Guest Editorial TCAS-I Special Issue Guest Editorial Based on the 16th IEEE Latin American Symposium on Circuits and Systems	53
HLS-Based Algorithm-Hardware Co-Design of MIMO-OFDM Receiver for Tactical Jamming Suppression	52
A Linear-Array Receiver AFE Circuit Embedded 8-to-1 Multiplexer for Direct ToF Imaging LiDAR Applications	52
Multi-Objective Surrogate-Model-Based Neural Architecture and Physical Design Co-Optimization of Energy Efficient Neural Network Hardware Accelerators	51
A RISC-V Domain-Specific Processor for Deep Learning-Based Channel Estimation	51
Bipartite Containment of Multi-Leader Multi-Agent Systems With Antagonistic Information and Measurement Noise	50
Nonlinear Capacitance Effect on Stability and Stabilization of SiGe Power Amplifiers for 17.3–21.2 GHz SATCOM	49
Setting Up the State Equations of Switched Circuits Using Homogeneous Models	48
Fixed-Time Composite Anti-Disturbance Control for Flexible-Link Manipulators Based on Disturbance Observer	47
0.4-V Tail-Less Quasi-Two-Stage OTA Using a Novel Self-Biasing Transconductance Cell	47
A Self-Supervised Learning of a Foundation Model for Analog Layout Design Automation	46
Compounding and Synchronization of Fractional Order Chaotic Systems With Prescribed Performance for Secure Communication	46
An Octave Tuning Range and Low Phase Noise Multi-Core Mode-Switching Oscillator Using Compact Hybrid Parallel-Series Resonator	46
A 25 MHz Fast Transient Adaptive-On/Off-Time Controlled Three-Level Buck Converter	45
Adaptive Horizon Seeking for Generalized Predictive Control via Deep Reinforcement Learning With Application to DC/DC Converters	45
Cross-Coupled Ferroelectric FET-Based Ternary Content Addressable Memory With Energy-Efficient Match Line Scheme	45
An SDMT-Based CMOS Voltage Reference With a Novel NCC Scheme for PSRR Bandwidth Enhancement	45
A Level Shifter With Almost Full Immunity to Positive dv/dt for Buck Converters	44
A Separated Pre-Charge Sense Amplifier With Fast Sensing, Low Power, Small Area, and High Reliability for Hybrid MTJ/CMOS Logic Circuits	44
A 24.25–29.5-GHz CMOS Upconversion Transmitter With Built-In Automatic LO Feedthrough and I/Q Imbalance Calibration for 5G New Radio	44
Voltage Control Ratiometric Readout Technique With Improved Dynamic Range and Power-Efficiency for Open-Loop MEMS Capacitive Accelerometer	44
Design of an Aging-Aware Memory With BTI-Mitigated SA and System-Visible Lifetime Management	44
Autaptic Self-Feedback for FPGA Realization and Real-Time Monitoring of Epileptic-Like Synchrony in Cubic–Quadratic Neuron Networks	44
IEEE Circuits and Systems Society Information	43
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS	43
IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors	43
A Knowledge Distillation Online Training Circuit for Fault Tolerance in Memristor Crossbar Array-Based Neural Networks	43
IEEE Circuits and Systems Society Information	43
Digraph Filter Design Based on Directed Laplacian Matrix and Least Squares Method	42
IEEE Circuits and Systems Society Information	42
X-NVDLA: Runtime Accuracy Configurable NVDLA Based on Applying Voltage Overscaling to Computing and Memory Units	41
Small Signal Modeling of a Four-Level Flying Capacitor Multilevel Totem-Pole PFC Converter	41
A Switched Capacitor Modified Fibonacci Cell Used for a DC–AC Circuit Supplied by Solar Energy	41

IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	41
Analysis and Design of a Novel Gain-Boosting Technique Based on Lossy Series Embedding Network for Near-f_max Embedded Amplifier	41
Robust Guaranteed Synchronization for Chaotic Systems With Incremental Quadratic Constraints	41
Optimization of Quantum Circuits for Stabilizer Codes	40
Guest Editorial Special Issue on the IEEE Latin American Symposium on Circuits and Systems (LASCAS 2023)	40
IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors	40
A Highly Power- and Area-Efficient PMU for Cell-Size Autonomous Microsystems	40
An Energy-Efficient Approximate Divider Based on Logarithmic Conversion and Piecewise Constant Approximation	39
Frequency-Flexible High Selectivity Multichannel Filtering Crossover Based on Slow-Wave Substrate Integrated Waveguide	39
Highly Dense Capacitor SRAM Computation-In-Memory With Dynamic Range Calibrated Column-by-Column ADCs	39
A Triode-Based Analog Gate and Its Application in Chaotic Circuits	39
The Mismatch Performance of Pseudo Digital Ring Oscillators Used in VCO ADCs: PSRR and CMRR	39
A General Efficiency Enhancement Method for Compact Broadband Rectifiers	38
SoC Reconfigurable Architecture for Implementing Software Trained Recurrent Neural Networks on FPGA	38
Broadband GaAs HBT Doherty Power Amplifier Using Lumped Compensation Network and Input Phase Correction for 5G Applications	38
Guest Editorial TCAS-I Special Issue on the ESSERC 2024 Conference	38
A Dual 7T SRAM-Based Zero-Skipping Compute- In-Memory Macro With 1-6b Binary Searching ADCs for Processing Quantized Neural Networks	38
Design Approaches for Efficient Parallel Pseudo-Random Ternary Sequence Generation	38
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	38
An Energy-Efficient Capacitive-RRAM Content Addressable Memory	37
A 0.65-pJ/bit 3.6-TB/s/mm I/O Interface With XTalk Minimizing Affine Signaling for Next-Generation HBM With High Interconnect Density	37
An Energy-Efficient Accelerator for Medical Image Reconstruction From Implicit Neural Representation	37
Model-Independent Observer-Based Critically Damped Terminal Voltage Stabilization for Single Machine Infinite Bus Systems via High-Order Pole-Zero Cancellation Approach	37
Finite-Time Stabilization of Semi-Markov Reaction-Diffusion Memristive NNs With Unbounded Time-Varying Delays	37
Generalized Active N-Port Network Analysis for Load Modulation: Doherty Power Amplifier Incorporating Tri-Coupled-Line Combiner	37
QSAP: Energy and Area-Efficient Query-Based Sparsity-Aware Accelerator for Voxel-Based Point Cloud Neural Networks	36
Adaptive Switching Control for Nonlinear Uncertain Systems With Sensor Faults and Quantization	36
Latency Insertion Method for Fast FinFET Simulation Based on the BSIM-CMG Model	36
Robust Fuzzy Control of Network-Type Re-Entrant Manufacturing Systems With Communication Delays	35
Analog Spiking Neural Network Based Phase Detector	35
Semi-Global Bounded Output Regulation of Linear Two-Time-Scale Systems With Input Saturation	35
Accelerating Deep Convolutional Neural Networks Using Number Theoretic Transform	35
Benchmarking of Scaled Majority-Logic-Synthesized Spintronic Circuits Based on Magnetic Tunnel Junction Transducers	35
Guest Editorial Special Issue on the International Symposium on Integrated Circuits and Systems—ISICAS 2025	34
Flocking Dynamics for Cooperation-Antagonism Multi-Agent Networks Subject to Limited Communication Resources	33
Compressed Sensing Σ-Δ Modulators and a Recovery Algorithm for Multi-Channel Wireless Bio-Signal Acquisition	33
Table of Contents	33
Fault-Tolerant Consensus of Multi-Agent Systems Subject to Multiple Faults and Random Attacks	33
A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks	33
Dual-Path Reactance Cell Theory and Its Application to a 6-bit K-Band True-Time-Delay Circuit	33
Stackelberg and Nash Equilibrium Computation in Non-Convex Leader-Follower Network Aggregative Games	32
Infinite Horizon Stabilization and Linear Quadratic Optimal Control of Descriptor Stochastic Markov Jump Systems	32
Virtual-Sensor-Based Model-Free Adaptive Fault-Tolerant Constrained Control for Discrete-Time Nonlinear Systems	32
EAGLE: A Flexible Heterogeneous Analog Compute-In-Memory Architecture With RISC-V Programmable Multi-Core Accelerators	32
Bayesian Deep-Learning Processor for Real-Time Bio-Applications With Structured Monte Carlo Dropout for High-Volume Sample Generation	32
RIVL: A Low-Cost SoC Agile Development Platform for Multiple RISC-V Processors Design and Verification	31
Event-Driven Vision Sensor With In-Pixel Spatial Contrast Computation Capabilities and On-Chip AER Sequencer	31
An AFD-Based ILC Dynamics Adaptive Matching Method in Frequency Domain for Distributed Consensus Control of Unknown Multiagent Systems	31
Reconfigurable 2.4/5.0-GHz Dual-Band CMOS Power Amplifier for WLAN 802.11ax	31
110–170 GHz On-Chip Calibration Using Deep Neural Networks	31
CINOC: Computing in Network-On-Chip With Tiled Many-Core Architectures for Large-Scale General Matrix Multiplications	31
A 0.0106 mm ² 8 nW Resistor-Less BJT Bandgap Reference Circuit in 65 nm CMOS With Orthogonal Voltage and Temperature Coefficient Trims	31
Homogeneous Versus Heterogeneous Graph Representation for Graph Neural Network Tasks on Electric Circuits	31
FPGA Implementation of Reconfigurable CORDIC Algorithm and a Memristive Chaotic System With Transcendental Nonlinearities	31
Skew-CIM: Process-Variation-Resilient and Energy-Efficient Computation-in-Memory Design Technique With Skewed Weights	31
A Novel Method for Authentication Using Chaotic Behaviour of Chua’s Oscillator in (n,k) Secret Shared Data Scheme for Secure Communication	31
CREAM: Computing in ReRAM-Assisted Energy- and Area-Efficient SRAM for Reliable Neural Network Acceleration	31
A Transformer-Based Technique to Improve Tuning Range and Phase Noise of a 20–28GHz LCVCO and a 51–62GHz Self-Mixing LCVCO	31
Bandwidth-Enhanced Mixed-Mode Outphasing Power Amplifiers Based on the Analytic Role-Exchange Doherty-Chireix Continuum Theory	31
Output-Feedback Stabilization of Uncertain Nonlinear Systems With Multiple Unknown Control Directions via an Integrated Switching Controller	31
A Highly Stable Physically Unclonable Function Using Algorithm-Based Mismatch Hardening Technique in 28-nm CMOS	31
A 3-bit Digitally-Reconfigurable Driving-Capability nW-Powered Three-Stage Fully-Synthesizable Inverter-Based OTA for Multi-Load/Applications	30
Finite-Time Dissipative Tracking Control of Semi-Markov Jump Systems Under Multi-Channel Hybrid Attacks	30
FAPSO: Fast Adaptive Particle Swarm Optimization-Based Background Timing Skew Calibration for TI-ADCs	30
Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K	30
Machine Learning-Assisted Electro-Thermal Co-Optimization Framework for PDN in 3-D Integrated Microsystem With Embedded Microchannel Heatsink	30
Resilient Decentralized Frequency Regulation for Multi-Area Power Systems With Electric Vehicles Under Hybrid Cyber-Attacks	30
IEEE Circuits and Systems Society Information	29
Table of Contents	29
Table of Contents	29
Guest Editorial Special Issue on the International Symposium on Integrated Circuits and Systems—ISICAS 2023	29
Editorial Special Issue on Circuits and Systems for Emerging Computing Paradigms	29
How Do Higher-Order Interactions Affect the Dynamic Evolution of Layered Neural Networks	29
Comprehensive Evaluation of Toroid Ring Core Parallel Inductor and Resistor as a Transformer Protection Device	29
Introducing IEEE Collabratec	29
Approximate Multipliers Using Static Segmentation: Error Analysis and Improvements	28
CMOS Current Driver for Electrothermal MEMS Switches With Actuation and Diagnostic Circuitry	28
Flexible FPGA Gaussian Random Number Generators With Reconfigurable Variance	28
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	28
A Reconfigurable Floating-Point Division and Square Root Architecture for High-Precision Softmax	28

Attractor Dynamics of 2-Lobe Discrete Corsage Memristor-Coupled Neuron Map	28
A 36–55 V Input 0.6–2.5 V Output Bypass-Assist Series-Capacitor Power Converter With 93.1% Peak Efficiency and 1.5 mA–5 A Load Range	28
Fixed-Point Kernel Adaptive Filtering for Fractional-Order Nonlinear Dynamical Systems With Applications to Chaotic Circuits	27
An Advanced Fault-Tolerant HANPC Converter With Neutral-Point Voltage Balancing for Full Power Factor Range Under Multi-Switch Open-Circuit Fault	27
PRADO: A Low-Latency and Energy-Efficient 6DoF Pose Refinement Accelerator With Domain-Specific Explorations	27
Pole-Zero Cancellation Speed and Acceleration Filtering Technique With Disturbance Observer for Servo Drive Applications Without Model Parameter Information	27
IEEE Circuits and Systems Society Information	27
A Sub-Nanosecond Delay Floating Voltage Level Shifter With 300 V/ns Power Supply Slew Tolerance	27
Digital Low-Cost FPGA Implementation of Two-Coupled and Grid-Based Network of 2D Artificial Cochlea Using the Hopf Resonator Approach	27
A Low-Cost Digital Capacitor Current Estimation Algorithm Based on Parameter Identification for Buck Converter Application	27
Editorial A New Exciting Year Ahead for TCAS-I	27
A 15–28 GHz Low-Noise Amplifier With 0.75-dB Gain Ripple Across the Full K-Band	26
Data-Driven Control Algorithms for Unknown Discrete-Time Linear Periodic Systems	26
Optimal Subband Adaptive Filter Over Functional Link Neural Network: Algorithms and Applications	26
Design and Analysis of a Resistive Frequency-Locked Oscillator With Long-Term Stability Using Double Chopper Stabilization	26
Optimization of DTC-Based and Harmonic-Mixer-Based Fractional-N PLLs: Comparative Analysis of Jitter and Power Trade-Offs	26
A Critical-Set-Based Multi-Bit Successive Cancellation List Decoder for Polar Codes: Algorithm and Implementation	26
A Novel Approach to Prescribed-Time Cooperative Output Regulation in Linear Heterogeneous Multi-Agent Systems Using Cascade System Criteria	26
IEEE Circuits and Systems Society Information	26
Entrainment of Mutually Synchronized Spatially Distributed 24 GHz Oscillators	26
A −79 dBm 7.56 nW 433 MHz Wake-Up Receiver With Interference Suppression for IoT Application	25
A Novel Memristive Combinational Logic for Accelerating N-bit Adders	25
An Adaptive Fully Integrated Wide-Range Power Management Unit With Fractional Charge Pump for Micro-Scale Energy Harvesting Applications	25
A 5-mW 30-GHz Quasi-Rotary Traveling-Wave Oscillator With Extrinsic-Q-Enhanced Transmission Line	25
From Relaxation to Chaotic Oscillations: A New Paradigm for Memristor Circuits	25
A Loop-Break Decision Feedback Equalizer for DAC/ADC-DSP-Based Wireline Transceivers	25
An Open-Circuit Fault Diagnosis for Three-Phase PWM Rectifier Without Grid Voltage Sensor Based on Phase Angle Partition	25
Low Latency SEU Detection in FPGA CRAM With In-Memory ECC Checking	25
A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks	25
A Capacitor-Cross-Connected Boost Converter With Duty Cycle < 0.5 Control for Extended Conversion-Ratio and Soft Start-Up	25
Scalable Multi-Stage CMOS OTAs With a Wide C_L-Drivability Range Using Low-Frequency Zeros	25
A Resonant Switched-Capacitor Parallel Inductor Hybrid Buck Converter	25
A K-/Ka-Band Broadband Low-Noise Amplifier Based on the Multiple Resonant Frequency Technique	25
Trio-ViT: Post-Training Quantization and Acceleration for Softmax-Free Efficient Vision Transformer	25
A High-Efficiency RFEH System With Feedback-Free Fast (F³) MPPT Over a Wide Input Range	25
Modeling and Adaptive Parameter Estimation for a Piezoelectric Cantilever Beam	24
Floquet Modulation Optimizing the Tunable Isolators Based on PT-Symmetric LCR Resonators	24
Reinforcement Learning Solutions to Stochastic Multi-Agent Graphical Games With Multiplicative Noise	24
Dynamic Event-Triggered Target Encirclement Control for Heterogeneous UAV/UGV Swarm Based on Finite-Time Distributed Target Observation	24
Memristor-Based Neural Network Circuit of Full-Function Pavlov Associative Memory With Unconditioned Response Mechanisms	24
SPP-CNN: An Efficient Framework for Network Robustness Prediction	24
A Flexible Impedance Modeling Method and Stability Analysis Toward the Cascaded Solid-State Transformer	24
Bipartite Consensus for Quantization Communication Multi-Agents Systems With Event-Triggered Random Delayed Impulse Control	24
Efficiency Enhancement Technique for Outphasing Amplifier With Extended Power Back-Off Range	24
DQ-STP: An Efficient Sparse On-Device Training Processor Based on Low-Rank Decomposition and Quantization for DNN	24
A 7T-NDR Dual-Supply 28-nm FD-SOI Ultra-Low Power SRAM With 0.23-nW/kB Sleep Retention and 0.8 pJ/32b Access at 64 MHz With Forward Back Bias	24
Dynamic Tsetlin Machine Accelerators for On-Chip Training Using FPGAs	24
Semiglobal Finite-Time Stability of Impulsive Systems	24
Edge-Side Fine-Grained Sparse CNN Accelerator With Efficient Dynamic Pruning Scheme	24
Bipartite Event-Triggered Output Tracking Consensus of Heterogeneous Linear Multi-Agent Systems Under Switching Directed Topologies	24
A 28 nm 16 Kb Bit-Scalable Charge-Domain Transpose 6T SRAM In-Memory Computing Macro	24
Feedback Stabilization of Switched Linear Systems: A Quantization and Triggering Joint Event-Triggered Mechanism	24
Concurrent Learning Adaptive Command Filtered Backstepping Control for High-Order Strict-Feedback Systems	24
Programmable In-Memory Computing Circuit for Solving Combinatorial Matrix Operation in One Step	23
Table of Contents	23
Effect of Device Mismatches in Differential Oscillatory Neural Networks	23
IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors	23
Impact of Non-Idealities on the Behavior of Probabilistic Computing: Theoretical Investigation and Analysis	23
APCCAS 2022 Guest Editorial Special Issue Based on the 18th Asia Pacific Conference on Circuits and Systems	23
Low-Power Capacitively Coupled AC Amplifiers With Tunable Ultra Low-Frequency Operation	23
Intelligent Coordination of Traditional Power Plants and Inverters Air Conditioners Controlled With Feedback-Corrected MPC in LFC	23
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	23
FireFly-S: Exploiting Dual-Side Sparsity for Spiking Neural Networks Acceleration With Reconfigurable Spatial Architecture	23
A High-Voltage Differential SPDT T/R Switch for Ultrasound Systems	23
A 2 MHz Bandwidth Area-Efficient Multipath Hall Sensor With a Residual Ripple of 4.1 μT	23
CoDeepCL-Based Oscillation-Adaptive and Label-Free Instability Detection Approach for DC Power Electronic Systems	23
Novel Digital Conversion and Power Amplifier Linearization Unit for Wireless Transmitters	23
Stabilization of Impulsive Systems With Beyond-Interval Impulse Delays	23
Clock Period-Jitter Measurement With Low-Noise Runtime Calibration for Chips in FinFET CMOS	23
A High-Accuracy Single-Photon Time-Interval Measurement in Mega-Hz Detection Rates With Collaborative Variance Reduction: Theoretical Analysis and Realization Methodology	23
Prescribed Time Recovery From State Constraint Violation via Approximation-Free Control Approach	23
Broadband Doherty Power Amplifier Using Short Ended λ/4 Transmission Lines Based on the Analysis of Negative Characteristic Impedance	22
A Low-Cost Pipelined Architecture Based on a Hybrid Sorting Algorithm	22
A 16-Channel Analog CMOS SiPM With On-Chip Front-End for D-ToF LiDAR	22
PDE-Based Finite-Time Deployment of Heterogeneous Multi-Agent Systems Subject to Multiple Asynchronous Semi-Markov Chains	22
A 0.4–0.9 V Supply Voltage-Flexible Third-Order Passive ΔΣ Modulator With Switched-Capacitor Loop Filter Achieving 71.9 dB Peak SNDR at 4 MHz Bandwidth	22
Random Flip Bit Aware Reading for Improving High-Density 3-D NAND Flash Performance	22
A 28 nm CMOS Triple-Latch Feed-Forward Dynamic Comparator With <27 ps / 1 V and <70 ps / 0.6 V Delay at 5 mV-Sensitivity	22
Fast FPGA Prototyping to Explore and Compare New SPWM Strategies	22
A Class-C CMOS Rectifier With Active Modulation Achieving >76% Peak Efficiency and Extended Input Power Range Over 8.8 dB Across Multiple Frequency Bands	22
An E-Band Bidirectional Front-End With 20.9 dBm Peak Output Power in GaAs Process	22
A 0.92-pJ/b 112-Gb/s PAM-4 Transmitter With Bandwidth and Linearity Enhanced Quasi-Voltage-Mode Driver and Reconfigurable Three-Tap T/2–T Variable Fractional-Spaced FFE in 28-nm CMOS	22
Bearing-Only Formation Control of Nonholonomic Unicycles: A Conditional Disturbance Utilization Method	22
A High Precision Analog Temperature Compensated Crystal Oscillator Using a New Temperature Compensated Multiplier	22
Artificial Neural Network Based on Memristive Circuit for High-Speed Equalization	22
Dynamic Vision With Single Photon Detectors: A Discrete DVS Architecture Using Asynchronous Sensor Front-Ends	22
The Hidden Behavior of a D-Latch	22
Memristor-Based Temporal Memory Neural Network Circuit Influenced by Emotional Arousal and Memory Interaction	22
Interdependence Among Voltage-Unstable Buses During Cascading Failure in Power Systems	22
A 28/39-GHz Four-Channel Dual-Band Phased-Array Transmitter Front-End Exploiting Frequency Reconfigurable Technique	22
Miniaturization of a Nuclear Magnetic Resonance System: Architecture and Design Considerations of Transceiver Integrated Circuits	21
A Capacitor-Coupled Offset-Canceled Sense Amplifier for DRAMs With Hidden Offset-Cancellation Time and Cross-Coupled Pre-Sensing	21
A 9-to-42-GHz High-Gain Low-Noise Amplifier Using Coupled Interstage Feedback in 0.15-μm GaAs pHEMT Technology	21
H∞ State Estimation for Two-Time-Scale Markov Jump Complex Networks Under Analog Fading Channels: A Hidden-Markov-Model-Based Method	21
A 16–20 GHz Mixer First Receiver Architecture With Active Inductor-Based Low-Pass Elliptic Filter With High OOB-IIP3 in 180 nm CMOS	21