IEEE Transactions on Circuits and Systems I-Regular Papers

Article	Citations
TechRxiv: Share Your Preprint Research with the World!	292
Setting Up the State Equations of Switched Circuits Using Homogeneous Models	223
A Cryo-CMOS SAR ADC With FIA Sampling Driver Enabled by Cryogenic-Aware Back-Biasing	169
Double-Ended Superposition Anti-Noise Resistance Monitoring Write Termination Scheme for Reliable Write Operation in STT-MRAM	167
An All NMOS KY-Boost Converter With Double Injection Control for Fast Line and Load Transient Response	164
Implementation of Group-Approximate Expectation Propagation Algorithm for Uplink MIMO-SCMA Detection Using 16-Point Codebook	128
A 16.5-31 GHz Area-Efficient Tapered Tunable Transmission Line Phase Shifter	125
Control of Power Converters With Hybrid Affine Models and Pulse-Width Modulated Inputs	124
A Fast and Fully Parallel Analog CMOS Solver for Nonlinear PDEs	118
Synthesis of an Equivalent Circuit for Spike-Timing-Dependent Axon Growth: What Fires Together Now Really Wires Together	117
A Level Shifter With Almost Full Immunity to Positive dv/dt for Buck Converters	114
A Proximal ADMM-Based Distributed Optimal Energy Management Approach for Smart Grid With Stochastic Wind Power	114
Adaptive Horizon Seeking for Generalized Predictive Control via Deep Reinforcement Learning With Application to DC/DC Converters	102
Online Identification of Piecewise Affine Systems Using Integral Concurrent Learning	98
A 1.6-V Tolerant Multiplexer Switch With 0.96-V Core Devices in 28-nm CMOS Technology	93
A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined ADCs	88
A TM-Based Adaptive Learning Data-Model for Trajectory Tracking and Real-Time Control of a Class of Nonlinear Systems	84
FPGA Accelerator for Real-Time Non-Line-of-Sight Imaging	82
Fixed-Time Composite Anti-Disturbance Control for Flexible-Link Manipulators Based on Disturbance Observer	81
Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference	77
An 11T1C Bit-Level-Sparsity-Aware Computing- in-Memory Macro With Adaptive Conversion Time and Computation Voltage	75
A 25 MHz Fast Transient Adaptive-On/Off-Time Controlled Three-Level Buck Converter	75
Multi-Objective Surrogate-Model-Based Neural Architecture and Physical Design Co-Optimization of Energy Efficient Neural Network Hardware Accelerators	74
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	73
IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	71

IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	69
IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	69
IEEE Open Access Publishing	69
Light-Weight Low-Latency Reconfigurable CORDIC Architecture With a New Non-Power-of-2 Angle Set of Microrotations	67
Learning, Optimization, and Implementation for Circuits and Systems driven by Artificial Intelligence	65
A 20 MHz–2 GHz Inductorless Two-Fold Noise-Canceling Low-Noise Amplifier in 28-nm CMOS	64
TechRxiv: Share Your Preprint Research with the World!	63
A Novel Design Method for CML Frequency Divider Based on C/Id and G/Id and Application for Quadrature-Injection	63
A Consistency Enhancement Technique for MIMO Power Amplifier Modules	63
FREYA: A 0.023-mm²/Channel, 20.8- μW/Channel, Event-Driven 8-Channel SoC for Spiking End-to-End Sensing of Time-Sparse Biosignals	62
Non-Linear Cyclic Variable Clock Feistel Bridge-Inspired Countermeasure for Securing RISC-V Crypto-Core Against Power Attacks	62
0.4-V Tail-Less Quasi-Two-Stage OTA Using a Novel Self-Biasing Transconductance Cell	61
Nonlinear Capacitance Effect on Stability and Stabilization of SiGe Power Amplifiers for 17.3–21.2 GHz SATCOM	58
Exploring Hybrid FitzHugh-Rinzel (FHR) Neuron Model Behavior: Cost-Effective FPGA Implementation for High-Frequency and High-Precision Matching by Electromagnetic Flux Effects	57
On the Efficacy and Vulnerabilities of Logic Locking in Tree-Based Machine Learning	56
A 20 nW +0.8°C/-0.8°C Inaccuracy (3σ) Leakage-Based CMOS Temperature Sensor With Supply Sensitivity of 0.9°C/V	56
Programmable Analog-to-Digital Converter Array Supporting Architecture Restructuring and Mode Concurrency	56
A 3-Phase Resonant Switched-Capacitor Converter for Data Center 48-V Rack Power Distribution	54
A New Macromodeling Method Based on Deep Gated Recurrent Unit Regularized With Gaussian Dropout for Nonlinear Circuits	54
Novel Optimized Implementations of Lightweight Cryptographic S-Boxes via SAT Solvers	53
Cross-Coupled Ferroelectric FET-Based Ternary Content Addressable Memory With Energy-Efficient Match Line Scheme	53
Adaptive Formation for Multiagent Systems Subject to Denial-of-Service Attacks	53
Bipartite Containment of Multi-Leader Multi-Agent Systems With Antagonistic Information and Measurement Noise	52
Design of Digital OTAs With Operation Down to 0.3 V and nW Power for Direct Harvesting	52
Voltage Control Ratiometric Readout Technique With Improved Dynamic Range and Power-Efficiency for Open-Loop MEMS Capacitive Accelerometer	52
Compounding and Synchronization of Fractional Order Chaotic Systems With Prescribed Performance for Secure Communication	51
Digital Time-Domain Predistortion of Linear Periodically Time-Varying Effects and Its Application to a 100-GS/s Time-Interleaved CMOS DAC	50
A Compact One-Transistor-Multiple-RRAM Characterization Platform	50
Proposal of Analog In-Memory Computing With Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell	49
A 0.7-V Sub-mW Type-II Phase-Tracking Bluetooth Low Energy Receiver in 28-nm CMOS	49
Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode	49
A Linear-Array Receiver AFE Circuit Embedded 8-to-1 Multiplexer for Direct ToF Imaging LiDAR Applications	49
A Knowledge Distillation Online Training Circuit for Fault Tolerance in Memristor Crossbar Array-Based Neural Networks	48
Retraction Notice: Robustness Margins for Attainable Consensusability of Unstable Multi-Agent Systems: Output Consensus Protocols Over Directed Network Topology	47
Design of Miniaturized Sub-6 GHz Rectifier With Self-Impedance Matching Technique	47
Parallel Delta-Sigma Modulator-Based Digital Predistortion of Wideband RF Power Amplifiers	47
Neuromorphic Dynamics of Chua Corsage Memristor	47
Analysis and Design of a Broadband Receiver Front End for 0.1-to-40-GHz Application	47
A RISC-V Domain-Specific Processor for Deep Learning-Based Channel Estimation	46
Guest Editorial Special Issue on the IEEE International NEWCAS Conference 2020	46
CINOC: Computing in Network-On-Chip With Tiled Many-Core Architectures for Large-Scale General Matrix Multiplications	46
Table of Contents	45
Output-Feedback Stabilization of Uncertain Nonlinear Systems With Multiple Unknown Control Directions via an Integrated Switching Controller	44
IEEE Transactions on Circuits and Systems—I:Regular Papers publication information	44
IEEE Circuits and Systems Society Information	43
IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors	43
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS	43
IEEE Circuits and Systems Society Information	43
SymBIST: Symmetry-Based Analog and Mixed-Signal Built-In Self-Test for Functional Safety	43
IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors	41

An Energy-Efficient Approximate Divider Based on Logarithmic Conversion and Piecewise Constant Approximation	41
Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K	41
Radix-2 w Arithmetic for Scalar Multiplication in Elliptic Curve Cryptography	41
IEEE Circuits and Systems Society Information	41
Finite-Time Stabilization of Semi-Markov Reaction-Diffusion Memristive NNs With Unbounded Time-Varying Delays	41
An Energy-Efficient Accelerator for Medical Image Reconstruction From Implicit Neural Representation	40
Optimization of Quantum Circuits for Stabilizer Codes	40
Infinite Horizon Stabilization and Linear Quadratic Optimal Control of Descriptor Stochastic Markov Jump Systems	40
Reconfigurable 2.4/5.0-GHz Dual-Band CMOS Power Amplifier for WLAN 802.11ax	40
Virtual-Sensor-Based Model-Free Adaptive Fault-Tolerant Constrained Control for Discrete-Time Nonlinear Systems	40
Gain-Scheduling Fault Estimation for Discrete-Time Takagi-Sugeno Fuzzy Systems: A Depth Partitioning Approach	39
Robust Guaranteed Synchronization for Chaotic Systems With Incremental Quadratic Constraints	39
Flocking Dynamics for Cooperation-Antagonism Multi-Agent Networks Subject to Limited Communication Resources	39
A Reduced-Area Capacitor-Only Loop Filter With Polarity-Switched Gm for Large Multiplication Factor Millimeter-Wave Sub-Sampling PLLs	39
Bandwidth-Enhanced Mixed-Mode Outphasing Power Amplifiers Based on the Analytic Role-Exchange Doherty-Chireix Continuum Theory	39
Adaptive Switching Control for Nonlinear Uncertain Systems With Sensor Faults and Quantization	39
Hardware Architecture for Supersingular Isogeny Diffie-Hellman and Key Encapsulation Using a Fast Montgomery Multiplier	39
DyGA: A Hardware-Efficient Accelerator With Traffic-Aware Dynamic Scheduling for Graph Convolutional Networks	38
Skew-CIM: Process-Variation-Resilient and Energy-Efficient Computation-in-Memory Design Technique With Skewed Weights	38
Semi-Global Bounded Output Regulation of Linear Two-Time-Scale Systems With Input Saturation	38
Analysis and Design of a Novel Gain-Boosting Technique Based on Lossy Series Embedding Network for Near-fmax Embedded Amplifier	38
Accelerating Deep Convolutional Neural Networks Using Number Theoretic Transform	37
110–170 GHz On-Chip Calibration Using Deep Neural Networks	37
A Transformer-Based Technique to Improve Tuning Range and Phase Noise of a 20–28GHz LCVCO and a 51–62GHz Self-Mixing LCVCO	37
Fault-Tolerant Consensus of Multi-Agent Systems Subject to Multiple Faults and Random Attacks	37
The Mismatch Performance of Pseudo Digital Ring Oscillators Used in VCO ADCs: PSRR and CMRR	36
A Triode-Based Analog Gate and Its Application in Chaotic Circuits	35
A Hybrid-Mode On-Chip Router for the Large-Scale FPGA-Based Neuromorphic Platform	35
Stackelberg and Nash Equilibrium Computation in Non-Convex Leader-Follower Network Aggregative Games	35
A Dual 7T SRAM-Based Zero-Skipping Compute- In-Memory Macro With 1-6b Binary Searching ADCs for Processing Quantized Neural Networks	35
Frequency-Flexible High Selectivity Multichannel Filtering Crossover Based on Slow-Wave Substrate Integrated Waveguide	35
CREAM: Computing in ReRAM-Assisted Energy- and Area-Efficient SRAM for Reliable Neural Network Acceleration	34
X-NVDLA: Runtime Accuracy Configurable NVDLA Based on Applying Voltage Overscaling to Computing and Memory Units	34
Guest Editorial Special Issue on the IEEE Latin American Symposium on Circuits and Systems (LASCAS 2023)	34
Model-Independent Observer-Based Critically Damped Terminal Voltage Stabilization for Single Machine Infinite Bus Systems via High-Order Pole-Zero Cancellation Approach	34
FAPSO: Fast Adaptive Particle Swarm Optimization-Based Background Timing Skew Calibration for TI-ADCs	34
An Energy-Efficient Capacitive-RRAM Content Addressable Memory	34
Benchmarking of Scaled Majority-Logic-Synthesized Spintronic Circuits Based on Magnetic Tunnel Junction Transducers	34
Compressed Sensing Σ-Δ Modulators and a Recovery Algorithm for Multi-Channel Wireless Bio-Signal Acquisition	33
SoC Reconfigurable Architecture for Implementing Software Trained Recurrent Neural Networks on FPGA	33
A Highly Stable Physically Unclonable Function Using Algorithm-Based Mismatch Hardening Technique in 28-nm CMOS	33
IEEE Circuits and Systems Society Information	33
Analog Spiking Neural Network Based Phase Detector	33
A Highly Power-and Area-Efficient PMU for Cell-Size Autonomous Microsystems	33
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	32
RIVL: A Low-Cost SoC Agile Development Platform for Multiple RISC-V Processors Design and Verification	32
Digraph Filter Design Based on Directed Laplacian Matrix and Least Squares Method	32
Small Signal Modeling of a Four-Level Flying Capacitor Multilevel Totem-Pole PFC Converter	32
A Dynamic Event-Triggered Approach to State Estimation for Switched Memristive Neural Networks With Nonhomogeneous Sojourn Probabilities	31
Event-Driven Vision Sensor With In-Pixel Spatial Contrast Computation Capabilities and On-Chip AER Sequencer	31
An AFD-Based ILC Dynamics Adaptive Matching Method in Frequency Domain for Distributed Consensus Control of Unknown Multiagent Systems	31
Almost Sure Synchronization of Multilayer Networks via Intermittent Pinning Noises: A White-Noise-Based Time-Varying Coupling	31
A Novel Method for Authentication Using Chaotic Behaviour of Chua’s Oscillator in (n,k) Secret Shared Data Scheme for Secure Communication	31
A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks	31
A 28 nm 16 Kb Bit-Scalable Charge-Domain Transpose 6T SRAM In-Memory Computing Macro	30
A Switched Capacitor Modified Fibonacci Cell Used for a DC–AC Circuit Supplied by Solar Energy	30
Table of contents	30
Dynamic Triggering Mechanisms for Distributed Adaptive Synchronization Control and Its Application to Circuit Systems	30
FPGA Implementation of Reconfigurable CORDIC Algorithm and a Memristive Chaotic System With Transcendental Nonlinearities	30
Guest Editorial Special Issue on the International Symposium on Integrated Circuits and Systems—ISICAS 2023	30
A High-Sensitivity Wide Input-Power-Range Ultra-Low-Power RF Energy Harvester for IoT Applications	30
Introducing IEEE Collabratec	29
Impact of Analog Non-Idealities on the Design Space of 6T-SRAM Current-Domain Dot-Product Operators for In-Memory Computing	29
Table of Contents	29
FireFly-S: Exploiting Dual-Side Sparsity for Spiking Neural Networks Acceleration With Reconfigurable Spatial Architecture	29
A K-/Ka-Band Broadband Low-Noise Amplifier Based on the Multiple Resonant Frequency Technique	29
Entrainment of Mutually Synchronized Spatially Distributed 24 GHz Oscillators	28
Memristor-Based Neural Network Circuit of Full-Function Pavlov Associative Memory With Unconditioned Response Mechanisms	28
IEEE Circuits and Systems Society Information	28
Concurrent Learning Adaptive Command Filtered Backstepping Control for High-Order Strict-Feedback Systems	28
A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks	28
A −79 dBm 7.56 nW 433 MHz Wake-Up Receiver With Interference Suppression for IoT Application	28
A Novel Approach to Prescribed-Time Cooperative Output Regulation in Linear Heterogeneous Multi-Agent Systems Using Cascade System Criteria	28
Multi-Mode QC-LDPC Decoding Architecture With Novel Memory Access Scheduling for 5G New-Radio Standard	28
Radiation Hardened 12T SRAM With Crossbar-Based Peripheral Circuit in 28nm CMOS Technology	28
Programmable In-Memory Computing Circuit for Solving Combinatorial Matrix Operation in One Step	28
Flexible FPGA Gaussian Random Number Generators With Reconfigurable Variance	28
An Open-Circuit Fault Diagnosis for Three-Phase PWM Rectifier Without Grid Voltage Sensor Based on Phase Angle Partition	28
DQ-STP: An Efficient Sparse On-Device Training Processor Based on Low-Rank Decomposition and Quantization for DNN	27
A Wide Dynamic Range Multi-Sensor ROIC for Portable Environmental Monitoring Systems With Two-Step Self-Optimization Schemes	27

Modeling and Simulation of Variable Limits on Conditional Anti-Windup PI Controllers for VSC-Based Devices	27
Attractor Dynamics of 2-Lobe Discrete Corsage Memristor-Coupled Neuron Map	27
Efficiency Enhancement Technique for Outphasing Amplifier With Extended Power Back-Off Range	27
TechRxiv: Share Your Preprint Research with the World!	27
A Sub-Nanosecond Delay Floating Voltage Level Shifter With 300 V/ns Power Supply Slew Tolerance	27
Bipartite Consensus for Quantization Communication Multi-Agents Systems With Event-Triggered Random Delayed Impulse Control	27
Trio-ViT: Post-Training Quantization and Acceleration for Softmax-Free Efficient Vision Transformer	27
IEEE Open Access Publishing	27
Low Latency SEU Detection in FPGA CRAM With In-Memory ECC Checking	27
BitS-Net: Bit-Sparse Deep Neural Network for Energy-Efficient RRAM-Based Compute-In-Memory	26
Analysis and Design of Quasi-Circulating Quadrature Hybrid for Full-Duplex Wireless	26
Design and Analysis of a Resistive Frequency-Locked Oscillator With Long-Term Stability Using Double Chopper Stabilization	26
A Self-Matching Rectifier Based on an Artificial Transmission Line for Enhanced Dynamic Range	26
DetectX—Adversarial Input Detection Using Current Signatures in Memristive XBar Arrays	26
Intelligent Coordination of Traditional Power Plants and Inverters Air Conditioners Controlled With Feedback-Corrected MPC in LFC	26
A Capacitor-Cross-Connected Boost Converter With Duty Cycle < 0.5 Control for Extended Conversion-Ratio and Soft Start-Up	26
Editorial Special Issue on Circuits and Systems for Emerging Computing Paradigms	26
Comprehensive Evaluation of Toroid Ring Core Parallel Inductor and Resistor as a Transformer Protection Device	26
Scalable Multi-Stage CMOS OTAs With a Wide CL-Drivability Range Using Low-Frequency Zeros	26
A 650 kV/μs Common-Mode Resilient CMOS Galvanically Isolated Communication System	26
Extracting RLC Parasitics From a Flexible Electronic Hybrid Assembly Using On-Chip ESD Protection Circuits	26
Low-Voltage Low-Noise High-CMRR Biopotential Integrated Preamplifier	26
A 5-mW 30-GHz Quasi-Rotary Traveling-Wave Oscillator With Extrinsic-Q-Enhanced Transmission Line	26
A Loop-Break Decision Feedback Equalizer for DAC/ADC-DSP-Based Wireline Transceivers	26
SPP-CNN: An Efficient Framework for Network Robustness Prediction	25
Loading-Aware Reliability Improvement of Ultra-Low Power Memristive Neural Networks	25
A 7T-NDR Dual-Supply 28-nm FD-SOI Ultra-Low Power SRAM With 0.23-nW/kB Sleep Retention and 0.8 pJ/32b Access at 64 MHz With Forward Back Bias	25
Balanced and Unbalanced Duplexers Using Common Oval Dielectric Resonators	25
Pole-Zero Cancellation Speed and Acceleration Filtering Technique With Disturbance Observer for Servo Drive Applications Without Model Parameter Information	25
Modeling and Adaptive Parameter Estimation for a Piezoelectric Cantilever Beam	25
IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	25
Bipartite Event-Triggered Output Tracking Consensus of Heterogeneous Linear Multi-Agent Systems Under Switching Directed Topologies	24
IEEE Circuits and Systems Society Information	24
An Advanced Fault-Tolerant HANPC Converter With Neutral-Point Voltage Balancing for Full Power Factor Range Under Multi-Switch Open-Circuit Fault	24
Optimal Subband Adaptive Filter Over Functional Link Neural Network: Algorithms and Applications	24
An Adaptive Fully Integrated Wide-Range Power Management Unit With Fractional Charge Pump for Micro-Scale Energy Harvesting Applications	24
Editorial A New Exciting Year Ahead for TCAS-I	24
A Reconfigurable Floating-Point Division and Square Root Architecture for High-Precision Softmax	24
A High-Efficiency RFEH System With Feedback-Free Fast (F3) MPPT Over a Wide Input Range	24
Floquet Modulation Optimizing the Tunable Isolators Based on PT-Symmetric LCR Resonators	24
Feedback Stabilization of Switched Linear Systems: A Quantization and Triggering Joint Event-Triggered Mechanism	24
A 36–55 V Input 0.6–2.5 V Output Bypass-Assist Series-Capacitor Power Converter With 93.1% Peak Efficiency and 1.5 mA–5 A Load Range	23
Spur Immunity in MASH-Based Fractional-N CP-PLLs With Polynomial Nonlinearities	23
Reinforcement Learning Solutions to Stochastic Multi-Agent Graphical Games With Multiplicative Noise	23
Challenges and Trends of SRAM-Based Computing-In-Memory for AI Edge Devices	23
Digital Low-Cost FPGA Implementation of Two-Coupled and Grid-Based Network of 2D Artificial Cochlea Using the Hopf Resonator Approach	23
A Resonant Switched-Capacitor Parallel Inductor Hybrid Buck Converter	23
Optimization of DTC-Based and Harmonic-Mixer-Based Fractional-N PLLs: Comparative Analysis of Jitter and Power Trade-Offs	23
IEEE Circuits and Systems Society Information	23
Edge-Side Fine-Grained Sparse CNN Accelerator With Efficient Dynamic Pruning Scheme	23
A Critical-Set-Based Multi-Bit Successive Cancellation List Decoder for Polar Codes: Algorithm and Implementation	23
Approximate Multipliers Using Static Segmentation: Error Analysis and Improvements	23
Semiglobal Finite-Time Stability of Impulsive Systems	23
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	22
A 16-Channel Analog CMOS SiPM With On-Chip Front-End for D-ToF LiDAR	22
The Hidden Behavior of a D-Latch	22
Stabilization of Impulsive Systems With Beyond-Interval Impulse Delays	22
Effect of Device Mismatches in Differential Oscillatory Neural Networks	22
A Sneak Current Compensation Scheme With Offset Cancellation Sensing Circuit for ReRAM-Based Cross-Point Memory Array	22
A Dual-Entropy-Superposed PUF With In-Cell Entropy Sign-Based Stabilization	22
Miniaturization of a Nuclear Magnetic Resonance System: Architecture and Design Considerations of Transceiver Integrated Circuits	22
Clock Period-Jitter Measurement With Low-Noise Runtime Calibration for Chips in FinFET CMOS	22
A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique	22
Fully Integrated Galvanic Isolation Interface in GaN Technology	22
Guest Editorial: Special Issue Based on the 12th Edition of the Latin American Symposium on Circuits and Systems	22
Table of Contents	22
Interdependence Among Voltage-Unstable Buses During Cascading Failure in Power Systems	22
High Logic Density Cyclic Redundancy Check and Forward Error Correction Logic Sharing Encoding Circuit for JESD204C Controller	22
Dithering Concepts for Spur-Free Nonlinear DTC-Based Frequency Synthesizers	21
Signal Integrity Augmentation Techniques for the Design of 64-GBaud Coherent Transimpedance Amplifier in 90-nm SiGe BiCMOS	21
Efficient Adaptive Multi-Level Privilege Partitioning With RTrustSoC	21
Portable CMOS NMR System With 50-kHz IF, 10-μs Dead Time, and Frequency Tracking	21
Bidirectional High Step-Up/Down DC/DC Converter With a Coupled Inductor and Switched Capacitor	21
A High Precision Analog Temperature Compensated Crystal Oscillator Using a New Temperature Compensated Multiplier	21
MPPT Multiplexed Hybrid Energy Harvesting Interface With Adaptive Switching Cycle and Single-Cycle Sampling for Wearable Electronics	21
Dynamic Vision With Single Photon Detectors: A Discrete DVS Architecture Using Asynchronous Sensor Front-Ends	21
Artificial Neural Network Based on Memristive Circuit for High-Speed Equalization	21
ARBiS: A Hardware-Efficient SRAM CIM CNN Accelerator With Cyclic-Shift Weight Duplication and Parasitic-Capacitance Charge Sharing for AI Edge Application	21
Passive Post-Resonance Tuned Reflectors to Achieve Both 10-bit Phase-Shifting Resolution and Low Insertion Loss Across 20–30 GHz	21
A Low-Cost Pipelined Architecture Based on a Hybrid Sorting Algorithm	21
Voltage Boosted Fail Detecting Circuit for Selective Write Assist and Cell Current Boosting for High-Density Low-Power SRAM	21
Dilate-Invariant Temporal Convolutional Network for Real-Time Edge Applications	21
Impact of Non-Idealities on the Behavior of Probabilistic Computing: Theoretical Investigation and Analysis	21
A 55nA Quiescent Current Power-Wise Buck Converter With 1μA–600mA Load Range and 0.5V–1.8V Flexible Output Voltage Options	21
APCCAS 2022 Guest Editorial Special Issue Based on the 18th Asia Pacific Conference on Circuits and Systems	20
A 10 Gb/s/pin Single-Ended Transmitter With Reflection-Aided Duobinary Modulation for Dual-Rank Mobile Memory Interfaces	20
Ferroelectric FET Nonvolatile Sense-Amplifier-Based Flip-Flops for Low Voltage Operation	20
Random Flip Bit Aware Reading for Improving High-Density 3-D NAND Flash Performance	20
Carry Disregard Approximate Multipliers	20
Low-Power Capacitively Coupled AC Amplifiers With Tunable Ultra Low-Frequency Operation	20
An Energy Efficient Coherent IR-UWB Receiver With Non-Coherent-Assisted Synchronization	20
H∞ State Estimation for Two-Time-Scale Markov Jump Complex Networks Under Analog Fading Channels: A Hidden-Markov-Model-Based Method	20
Fast FPGA Prototyping to Explore and Compare New SPWM Strategies	20
Soft-Error-Immune Read-Stability-Improved SRAM for Multi-Node Upset Tolerance in Space Applications	19
A 16–20 GHz Mixer First Receiver Architecture With Active Inductor-Based Low-Pass Elliptic Filter With High OOB-IIP3 in 180 nm CMOS	19