IEEE Transactions on Circuits and Systems I-Regular Papers

Article	Citations
Introducing IEEE Collabratec	282
IEEE Open Access Publishing	256
Design of a Quadband Doherty Power Amplifier With Large Power Back-Off Range	188
IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors	149
Ultralow-Latency VLSI Architecture Based on a Linear Approximation Method for Computing Nth Roots of Floating-Point Numbers	136
IEEE Circuits and Systems Society Information	132
DNN-Based Optimization to Significantly Speed Up and Increase the Accuracy of Electronic Circuit Design	117
A Low Noise 8.3-Mpixel CMOS Image Sensor With Selectable Multiple Sampling Technique by 5.36 GHz Global Counter and Dual Latch Skew Canceler	106
Improved Vector Current Control for the VSC-HVdc Converter Connected to a Very Weak AC Grid	106
IEEE Circuits and Systems Society Information	99
IEEE Transactions on Circuits and Systems—I:Regular Papers publication information	98
A 3-Phase Resonant Switched-Capacitor Converter for Data Center 48-V Rack Power Distribution	95
IEEE Open Access Publishing	94
Novel Optimized Implementations of Lightweight Cryptographic S-Boxes via SAT Solvers	93
Implementation of Group-Approximate Expectation Propagation Algorithm for Uplink MIMO-SCMA Detection Using 16-Point Codebook	91
Adaptive Low-Order Harmonic Currents Suppression in AC Power System Using Fractional-Order Circuit	79
Hybrid-Bridge-Based Dual-Active-Bridge Converter With an Asymmetric Active-Neutral-Point-Clamped Three-Level Bridge	79
Modular Expansion Method for Wireless Power Transfer Systems With Arbitrary Topologies	72
Jitter-Power Trade-Offs in PLLs	71
Synthesis Design of Multiband Bandpass Filters Employing Multimode Bandstop Resonators With Star-Like Topology	71
DTC Linearization via Mismatch-Noise Cancellation for Digital Fractional-N PLLs	67
An Integer-Only and Group-Vector Systolic Accelerator for Efficiently Mapping Vision Transformer on Edge	65
Low-Variance Memristor-Based Multi-Level Ternary Combinational Logic	63
Finite-Time Adaptive Neural Network Observer-Based Output Voltage-Tracking Control for DC–DC Boost Converters	63
0.4-V Tail-Less Quasi-Two-Stage OTA Using a Novel Self-Biasing Transconductance Cell	62

More is Less: Domain-Specific Speech Recognition Microprocessor Using One-Dimensional Convolutional Recurrent Neural Network	61
High-Speed FPGA Implementation of SIKE Based on an Ultra-Low-Latency Modular Multiplier	58
Hybrid Event-Triggered Approach for Quasi-Consensus of Uncertain Multi-Agent Systems With Impulsive Protocols	58
A 2.4–6 GHz Broadband GaN Power Amplifier for 802.11ax Application	57
GQNA: Generic Quantized DNN Accelerator With Weight-Repetition-Aware Activation Aggregating	57
A Compact DC-DC Converter With Pulse-Counting MPPT and Fast One-Path Self-Startup for Thermal Energy Harvesting	55
FDSOI-Based Analog Computing for Ultra-Efficient Hamming Distance Similarity Calculation	55
Unknown System Dynamic Estimator-Based Two-Phase Power Reaching Law Control for DC–DC Buck Converter	55
TechRxiv: Share Your Preprint Research with the World!	54
IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors	54
High-Resolution Wideband Vector-Sum Digital Phase Shifter With On-Chip Phase Linearity Enhancement Technology	53
Adaptive Horizon Seeking for Generalized Predictive Control via Deep Reinforcement Learning With Application to DC/DC Converters	53
Millimeter-Wave Integrated Phased Arrays	52
A Network-on-Chip-Based Annealing Processing Architecture for Large-Scale Fully Connected Ising Model	51
A 50-ps Gated VCRO-Based TDC With Compact Phase Interpolators for Flash LiDAR	50
A 36 μW 2.8–3.4 dB Noise Figure Impedance Boosted and Noise Attenuated LNA for NB-IoT	50
Table of Contents	48
Distributed Fault Estimation and Fault-Tolerant Control of Interconnected Systems With Plug-and-Play Features	48
IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	48
Analysis and Comparison of Readout Architectures and Analog-to-Digital Converters for 3D-Stacked CMOS Image Sensors	47
Algorithm and Architecture Design of Random Fourier Features-Based Kernel Adaptive Filters	47
A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined ADCs	46
TechRxiv: Share Your Preprint Research with the World!	46
Analysis of RC Time-Constant Variations in Continuous-Time Pipelined ADCs	44
A Continuously-Tunable Optoelectronic Oscillator With Full Locking Range Utilizing Three Frequency Tuning Mechanisms	44
A Level Shifter With Almost Full Immunity to Positive dv/dt for Buck Converters	44
A New Adaptive Sparse Pseudospectral Approximation Method and its Application for Stochastic Power Flow	44
Analysis and Design of Precision-Scalable Computation Array for Efficient Neural Radiance Field Rendering	44
T3L: A Practical Implementation of Tri-Transistor Ternary Logic Based on Inkjet-Printed Anti-Ambipolar Transistors and CMOSs of Thin-Film Structure	43
Efficient Hardware Implementations of Legendre Symbol Suitable for MPC Applications	43
IEEE Circuits and Systems Society Information	43
FPGA Accelerator for Real-Time Non-Line-of-Sight Imaging	43
TechRxiv: Share Your Preprint Research with the World!	43
An 11 pJ/Bit Multichannel OOK/FSK/QPSK Transmitter With Multi-Phase Injection-Locking and Frequency Multiplication Techniques	43
Ternary LDPC Error Correction for Arrhythmia Classification in Wireless Wearable Electrocardiogram Sensors	41
UFBBR: A Unified Frequency and Back-Bias Regulation Unit for Ultralow-Power Microcontrollers in 28-nm FDSOI	41
IEEE Transactions on Circuits and Systems—I:Regular Papers publication information	41
Graph Attention Networks to Identify the Impact of Transistor Degradation on Circuit Reliability	40
A Potential Enabler for High-Performance In-Memory Multi-Bit Arithmetic Schemes With Unipolar Switching SOT-MRAM	40
Synchronization on Directed Delayed Duplex Networks: From the Perspective of Coupled Delays	39
Energy-Efficient and High-Throughput CNN Inference Engine Based on Memory-Sharing and Data-Reusing for Edge Applications	39
Table of contents	38
A Fully Probabilistic Model for Sigmoid Approximation and Its Hardware- Efficient Implementation	38
Self-Synchronized DS/SS With High Spread Factors for Robust Millimeter-Wave Datalinks	38
Enhanced Dual-Mode Reciprocal Doherty Power Amplifier Using Modified Combining Load and Parameter Sweeping Analysis	38
A TM-Based Adaptive Learning Data-Model for Trajectory Tracking and Real-Time Control of a Class of Nonlinear Systems	38
A Computing In-Memory Multibit Multiplication Based on Decoupling and In-Array Storing	38
Fractionally-Spaced Equalizers as Clock and Data Recovery Loops	38
Digital Non-Linearity Calibration for ADCs With Redundancy Using a New LUT Approach	37
A Heterogeneous Platform for 3D NAND-Based In-Memory Hyperdimensional Computing Engine for Genome Sequencing Applications	37

A Transistor-Based High-Efficiency Rectifier Using Input Second Harmonic Component	37
Construction and Application of a Neuromorphic Circuit With Excitatory and Inhibitory Post-Synaptic Conduction Channels Implemented Using Dual-Gate Thin-Film Transistors	37
An Energy-Efficient SAR ADC With a Coarse-Fine Bypass Window Technique	37
IEEE Transactions on Circuits and Systems—I:Regular Papers publication information	37
Trade-Off-Oriented Impedance Optimization of Chiplet-Based 2.5-D Integrated Circuits With a Hybrid MDP Algorithm for Noise Elimination	36
Setting Up the State Equations of Switched Circuits Using Homogeneous Models	36
A Chopper-Stabilized Switched-Capacitor Front-End for Peripheral Nervous System Recording	36
Control of Power Converters With Hybrid Affine Models and Pulse-Width Modulated Inputs	36
Derivative-Enhanced Rational Polynomial Chaos for Uncertainty Quantification	36
Circuit Modeling for RRAM-Based Neuromorphic Chip Crossbar Array With and Without Write-Verify Scheme	36
In-Memory Acceleration of Hyperdimensional Genome Matching on Unreliable Emerging Technologies	36
A Self-Clocked and Variation-Tolerant Unified Voltage-and-Frequency Regulator for In-Order Executed Digital Loads	36
A 10.4–16-Gb/s Reference-Less Baud-Rate Digital CDR With One-Tap DFE Using a Wide-Range FD	35
A 6.15–10.9 Gb/s 0.58 pJ/Bit Reference-Less Half-Rate Clock and Data Recovery With “Phase Reset” Scheme	35
IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	35
Reconfigurable Receiver With Adaptive Output Voltage for Wireless Power Transfer	34
A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures	34
Disturbance Utilization-Based Tracking Control for the Fixed-Wing UAV With Disturbance Estimation	34
A Highly Stable Low-Energy 10T SRAM for Near-Threshold Operation	33
IEEE Open Access Publishing	33
On Synchronization Design and State Observer Design of (Singular) Boolean Networks	33
IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	33
A Proximal ADMM-Based Distributed Optimal Energy Management Approach for Smart Grid With Stochastic Wind Power	33
TechRxiv: Share Your Preprint Research with the World!	32
Table of Contents	32
IEEE Open Access Publishing	32
IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	32
A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration	31
IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	31
Table of Contents	31
IEEE Transactions on Circuits and Systems—I:Regular Papers publication information	31
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	31
Flicker Phase-Noise Reduction Using Gate–Drain Phase Shift in Transformer-Based Oscillators	30
A Power-Efficient 13-Tap FIR Filter and an IIR Filter Embedded in a 10-Bit SAR ADC	30
Slew-Rate Booster and Frequency Compensation Circuit for Automotive LDOs	30
An Energy-Efficient SIFT Based Feature Extraction Accelerator for High Frame-Rate Video Applications	30
An Analog Circuit Building Block Generator via Nested Multi-Fidelity Modeling	30
Ascend: A Scalable and Energy-Efficient Deep Neural Network Accelerator With Photonic Interconnects	30
Buck Circuit Design With Pseudo-Constant Frequency and Constant On-Time for High Current Point-of-Load Regulation	30
PMU-Spill: A New Side Channel for Transient Execution Attacks	30
Distributed Adaptive Resilient Formation Control of Uncertain Nonholonomic Mobile Robots Under Deception Attacks	30
Reconfigurable Bit-Serial Operation Using Toggle SOT-MRAM for High-Performance Computing in Memory Architecture	29
In Vitro Study of Artifact-Recovery Using a 32-Channel Neuromodulator Platform	29
Differential Edge Modulation Signaling for Low-Energy, High-Speed Wireline Communication	29
Interval Observer-Based Robust Coordination Control of Multi-Agent Systems Over Directed Networks	29
CAMiSE: Content Addressable Memory-Integrated Searchable Encryption	29
Impedance-Circuit-Based Stability Analysis for PLL-Synchronized Voltage Source Converter in Weak Grid	29
A Practical Design-Space Analysis of Compute-in-Memory With SRAM	29
Accurate and Fast On-Wafer Test Circuitry Integrated With a 140-dB-Input-Range Current Digitizer for Parameter Tests in WAT	29
Analysis and Design of Broadband Balance-Compensated Transformer Baluns for Silicon-Based Millimeter-Wave Circuits	29
Observer-Based Event-Triggered Formation Control of Multi-Agent Systems With Switching Directed Topologies	28
A 1.6-V Tolerant Multiplexer Switch With 0.96-V Core Devices in 28-nm CMOS Technology	28
Optimizing Constrained Guidance Policy With Minimum Overload Regularization	28
Non-Weighted L 2-Gain Analysis for Synchronization of Switched Nonlinear Time-Delay Systems With Random Injection Attacks	28
Bipartite Average Tracking for Multi-Agent Systems With Disturbances: Finite-Time and Fixed-Time Convergence	28
Fixed-Time Composite Anti-Disturbance Control for Flexible-Link Manipulators Based on Disturbance Observer	28
Robustness Margins for Attainable Consensusability of Unstable Multi-Agent Systems: Output Consensus Protocols Over Directed Network Topology	28
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS	27
Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference	27
Random Telegraph Noise in Analog CMOS Circuits	27
Low-Complexity and Low-Latency SVC Decoding Architecture Using Modified MAP-SP Algorithm	27
Wideband Balanced Filters With Intrinsic Common-Mode Suppression on Coplanar Stripline-Based Multimode Resonators	27
Digital Time-Domain Predistortion of Linear Periodically Time-Varying Effects and Its Application to a 100-GS/s Time-Interleaved CMOS DAC	27
Analysis of Conditional Stability and Unconditional Stability and Instability for Microwave 3-Ports	27
A 16-Bit 4.0-GS/s Calibration-Free 65 nm DAC Achieving >70 dBc SFDR and < −80 dBc IM3 Up to 1 GHz With Enhanced Constant-Switching-Activity Data-Weighted-Averaging	26
Synthesis of an Equivalent Circuit for Spike-Timing-Dependent Axon Growth: What Fires Together Now Really Wires Together	26
Hardware-Efficient and Short Sensing-Time Multicoset-Sampling Based Wideband Spectrum Sensor for Cognitive Radio Network	26
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	26
An SoC FPAA Based Programmable, Ladder-Filter Based, Linear-Phase Analog Filter	26
Noise Model of Large-Format Readout Integrated Circuit for Infrared Focal Plane Array	26
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	26
Double-Ended Superposition Anti-Noise Resistance Monitoring Write Termination Scheme for Reliable Write Operation in STT-MRAM	26
A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition	26
A 6.78 MHz Single-Stage Wireless Power Transmitter Using a 3-Mode Zero-Voltage Switching Class-D PA	26
Characterization of Inter-Cell Interference in 3D NAND Flash Memory	26
Analysis of a Multiwire, Multilevel, and Symbol Correlation Combination Scheme	25
An In-Depth Evaluation of Externally Amplified Coupling (EAC) Attacks—A Concrete Threat for Masked Cryptographic Implementations	25
TechRxiv: Share Your Preprint Research with the World!	25
Analysis and Design of a Broadband Receiver Front End for 0.1-to-40-GHz Application	25
IEEE Circuits and Systems Society Information	25

Design and Analysis of an On-Chip Current-Driven CMOS Parametric Frequency Divider	24
Nonlinear Capacitance Effect on Stability and Stabilization of SiGe Power Amplifiers for 17.3–21.2 GHz SATCOM	24
Guest Editorial Special Issue on the International Symposium on Integrated Circuits and Systems—ISICAS 2024	24
A Comprehensive Framework for the Thévenin–Norton Theorem Using Homogeneous Circuit Models	24
A Compact Wideband SPDT Switch Using Compensating Inductors and Highpass Matching Network	24
Motion Detection and Analysis Using Multimaterial Fiber Sensors	24
A Ka-Band Reconfigurable Dual-Band Variable Gain Amplifier With Low Phase Variation for 5G Communications	24
Improved Fixed-Time Stability Lemma of Discontinuous System and its Application	23
Low-Latency Low-Complexity Method and Architecture for Computing Arbitrary Nth Root of Complex Numbers	23
Joint Digital Online Compensation of TX and RX Time-Varying I/Q Mismatch and DC-Offset in mmWave Transceiver System	23
Sub-ppm/°C Bandgap References With Natural Basis Expansion for Curvature Cancellation	23
TDPRO: Time-Domain-Based Computing-in Memory Engine for Ultra-Low Power ECG Processor	23
A Linear-Array Receiver AFE Circuit Embedded 8-to-1 Multiplexer for Direct ToF Imaging LiDAR Applications	23
Analysis and Calibration for Wideband Times-2 Interleaved Current-Steering DACs	23
Proposal of Analog In-Memory Computing With Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell	23
Event-Based Neural Networks Adaptive Control of Nonlinear Systems: A Fully Actuated System Approach	22
A New Macromodeling Method Based on Deep Gated Recurrent Unit Regularized With Gaussian Dropout for Nonlinear Circuits	22
Time-Domain Computing in Memory Using Spintronics for Energy-Efficient Convolutional Neural Network	22
NTT Architecture for a Linux-Ready RISC-V Fully-Homomorphic Encryption Accelerator	22
MARLIN: A Co-Design Methodology for Approximate ReconfigurabLe Inference of Neural Networks at the Edge	22
On the Resilience Analysis of DC Microgrids With Power Buffer Control	22
Voltage Control Ratiometric Readout Technique With Improved Dynamic Range and Power-Efficiency for Open-Loop MEMS Capacitive Accelerometer	22
HAMSA-DI: A Low-Power Dual-Issue RISC-V Core Targeting Energy-Efficient Embedded Systems	22
HAS-RL: A Hierarchical Approximate Scheme Optimized With Reinforcement Learning for NoC-Based NN Accelerators	22
Facilitating and Determining Turing Patterns in 3-D Memristor Cellular Neural Networks	22
Compounding and Synchronization of Fractional Order Chaotic Systems With Prescribed Performance for Secure Communication	22
Extended Dissipative Scalable Control for AC Islanded Microgrids	22
A Complex Band-Pass Filter for Low-Power and High-Performance Transceivers	21
Learning, Optimization, and Implementation for Circuits and Systems driven by Artificial Intelligence	21
Outlooks on Transmitter Energy Efficiency and FOM and a −189.7-dBJ/bit ULP DPPM Transmitter	21
Robust H∞ Adaptive Sliding Mode Fault Tolerant Control for T-S Fuzzy Fractional Order Systems With Mismatched Disturbances	21
PL-NPU: An Energy-Efficient Edge-Device DNN Training Processor With Posit-Based Logarithm-Domain Computing	21
Table of Contents	21
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	21
A 25 MHz Fast Transient Adaptive-On/Off-Time Controlled Three-Level Buck Converter	21
Fast Beam Training With True-Time-Delay Arrays in Wideband Millimeter-Wave Systems	21
Table of Contents	21
A 1.01 NEF Low-Noise Amplifier Using Complementary Parametric Amplification	21
17-aFrms Resolution Noise-Immune Fingerprint Scanning Analog Front-End for Under-Glass Mutual-Capacitive Fingerprint Sensors	20
A High-Temperature Model for GaN-HEMT Transistors and its Application to Resistive Mixer Design	20
IEEE Circuits and Systems Society Information	20
A Subgraph-Based Hierarchical Q-Learning Approach to Optimal Resource Scheduling for Complex Industrial Networks	20
Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop	20
Satisfiability Attack-Resilient Camouflaged Multiple Multivariable Logic-in-Memory Exploiting 3D NAND Flash Array	20
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	20
Hardware Architecture of Layered Decoders for PLDPC-Hadamard Codes	20
Continuous-Time, Configurable Analog Linear System Solutions With Transconductance Amplifiers	20
Using Strictly Dissipative Impedance Coupling in the Waveform Relaxation Method for the Analysis of Interconnect Circuits	20
A Cycle by Cycle FSK Demodulator With High Sensitivity of 1% Frequency Modulation Index for Implantable Medical Devices	20
Table of Contents	20
Distributed Time-Varying Economic Dispatch via a Prediction-Correction Method	19
A Graph Transformer-Driven Approach for Network Robustness Learning	19
LMI Stability Condition for Delta Fractional Order Systems With Region Approximation	19
Machine Learning Methodologies to Predict the Results of Simulation-Based Fault Injection	19
A MEMS-CMOS Microsystem for Contact-Less Temperature Measurements	19
Tunable CMOS Pseudo-Resistors for Resistances of Hundreds of GΩ	19
ACE-CNN: Approximate Carry Disregard Multipliers for Energy-Efficient CNN-Based Image Classification	19
Broadband Mismatch Calibration for Time-Interleaved ADC Based on Linear Frequency Modulated Signal	19
Sampled-Hold-Based Consensus Control for Second-Order Multiagent Systems Under Aperiodically Intermittent Communication	19
Lattice Trajectory Piecewise Linear Method for the Simulation of Diode Circuits	19
CARLA: A Convolution Accelerator With a Reconfigurable and Low-Energy Architecture	19
Vector Wave Digital Filters and Their Application to Circuits With Two-Port Elements	19
Synthesis Design of In-Line Pseudoelliptic SISL Bandpass Filter Employing Non-Resonating Mode in Low-Loss Patch Resonators	19
Cross-Coupled Ferroelectric FET-Based Ternary Content Addressable Memory With Energy-Efficient Match Line Scheme	18
Real-Time Compensation in Organic Light-Emitting Diode Television Displays Using Current Sensing Method With Charge Integrators	18
Low-Power and Scalable BEOL-Compatible IGZO TFT eDRAM-Based Charge-Domain Computing	18
Area-Efficient QC-LDPC Decoding Architecture With Thermometer Code-Based Sorting and Relative Quasi-Cyclic Shifting	18
A Secure Dynamic Event-Triggered Mechanism for Resilient Control of Multi-Agent Systems Under Sensor and Actuator Attacks	18
A Cryo-CMOS SAR ADC With FIA Sampling Driver Enabled by Cryogenic-Aware Back-Biasing	18
A Fully Integrated Low-Power Hall-Based Isolation Amplifier With IMR Greater Than 120 dB	18
A Detailed Model of Cyclostationary Noise in Switched-Resistor Circuits	18
Identification of Nonlinear Discrete Systems From Probability Density Sequences	18
A Coupling Matrix Synthesized Three-Dimensional Filtering Power Amplifier	18
LMI-Based Robust Stability Analysis of Discrete-Time Fractional-Order Systems With Interval Uncertainties	18
Bottleneck-Stationary Compact Model Accelerator With Reduced Requirement on Memory Bandwidth for Edge Applications	18
A 71.2-μW Speech Recognition Accelerator With Recurrent Spiking Neural Network	18
Taxonomy and Benchmarking of Precision-Scalable MAC Arrays Under Enhanced DNN Dataflow Representation	18
Finite-Time State Zonotopes Design for Asynchronously Switched Systems With Application to a Switched Converter	18
Inner Product Computation In-Memory Using Distributed Arithmetic	18
Parallel Delta-Sigma Modulator-Based Digital Predistortion of Wideband RF Power Amplifiers	18
Area Efficient Asynchronous SFQ Pulse Round-Robin Distribution Network	18
Real-Time External Compensation System With Error Correction Algorithm for High-Resolution Mobile Displays	18
Design of Multi-Port With Desired Reference Impedances Using Y-Matrix and Matching Networks	18
Neural Network Based Iterative Learning Control for Dynamic Hysteresis and Uncertainties in Magnetic Shape Memory Alloy Actuator	18
The Intrinsic Communication in Power Systems: A New Perspective to Understand Synchronization Stability	18
Balanced Filtering Phase Shifters With Low Phase Deviation and High Common-Mode Suppression	18
Active Charge Balancer With Adaptive 3.3 V to 38 V Supply Compliance for Neural Stimulators	18
A 0.003-mm2 440fsRMS-Jitter and −64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS	18
Robust H ∞ Control for ICPT Process With Coil Misalignment and Time Delay: A Sojourn-Probability-Based Switching Case	18
Low-Overhead Triple-Node-Upset Self-Recoverable Latch Design for Ultra-Dynamic Voltage Scaling Application	17
Design of Miniaturized Sub-6 GHz Rectifier With Self-Impedance Matching Technique	17
Comprehensive Diagnosis Strategy for Power Switch, Grid-Side Current Sensor, DC-Link Voltage Sensor Faults in Single-Phase Three-Level Rectifiers	17
An Efficient Three-Phase Soft-Switching Inverter With Simplified Asymmetric Single Auxiliary Circuit on Each Bridge Arm for Low-Speed AC Motor Drive	17
A Memristor Emulation in 180-nm CMOS Process for Spiking Signal Generation and Chaos Application	17
A 1.8–5.4-GHz GaN MMIC Distributed Efficient Power Amplifier With Reactance Compensation and Adaptive Biasing	17