OOIR: Observatory of International Research

Papers

(The TQCC of IEEE Transactions on Circuits and Systems I-Regular Papers is 10. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-08-01 to 2026-08-01.)

Article	Citations
TechRxiv: Share Your Preprint Research with the World!	168
Learning, Optimization, and Implementation for Circuits and Systems driven by Artificial Intelligence	131
IEEE Open Access Publishing	128
Implementation of Group-Approximate Expectation Propagation Algorithm for Uplink MIMO-SCMA Detection Using 16-Point Codebook	128
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	113
Digital Time-Domain Predistortion of Linear Periodically Time-Varying Effects and Its Application to a 100-GS/s Time-Interleaved CMOS DAC	106
Welcome to a New Term in TCAS-I	104
Retraction Notice: Robustness Margins for Attainable Consensusability of Unstable Multi-Agent Systems: Output Consensus Protocols Over Directed Network Topology	97
Fast Algorithms for Resistance Distances on Signed Graphs	96
A 1-GS/s 12-bit Pipelined-SAR ADC With Dither-Based Background Calibration of Interstage Gain and Comparator Offset in 28-nm CMOS	90
A Proximal ADMM-Based Distributed Optimal Energy Management Approach for Smart Grid With Stochastic Wind Power	84
Programmable Analog-to-Digital Converter Array Supporting Architecture Restructuring and Mode Concurrency	83
On the Efficacy and Vulnerabilities of Logic Locking in Tree-Based Machine Learning	83
An All NMOS KY-Boost Converter With Double Injection Control for Fast Line and Load Transient Response	80
Novel Optimized Implementations of Lightweight Cryptographic S-Boxes via SAT Solvers	78
Design of Miniaturized Sub-6 GHz Rectifier With Self-Impedance Matching Technique	75
Frequency Response Model for Power Systems Including HVDC-Connected Offshore Wind Power With Communication-Free Frequency Control	74
A 4.25–8.45-GHz 67% Chirp-Fractional Bandwidth −121.5-dBc/Hz PN at 1-MHz 88-fs Jitter FMCW Synthesizer With Fractional-Bandwidth-Boosting and Phase-Noise-Cancellation Techniques	68
A Handgrip-Responsive mmWave Phased Array Antenna-PA Module With Antenna-Based Capacitive Sensor for EIRP Recovery via Adaptive Current Redistribution	68
Pipe-LPAQ: A Fully Pipelined Architecture for LPAQ Data Compression on FPGA	67
A Consistency Enhancement Technique for MIMO Power Amplifier Modules	66
A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined ADCs	65
Data-Driven Fault-Tolerant Control Framework for EV Dynamic Wireless Power Transfer System Based on Self-Learning Predictor	64
Guest Editorial TCAS-I Special Issue Guest Editorial Based on the 16th IEEE Latin American Symposium on Circuits and Systems	64
A Simultaneous Bidirectional Link With 6–12.8-Gb/s Forward and 12–25.6-Gb/s Backward Channels for System Chips Interconnects	64

A Novel Design Method for CML Frequency Divider Based on C/I_d and G/I_d and Application for Quadrature-Injection	63
A RISC-V Domain-Specific Processor for Deep Learning-Based Channel Estimation	63
Multi-Objective Surrogate-Model-Based Neural Architecture and Physical Design Co-Optimization of Energy Efficient Neural Network Hardware Accelerators	61
An Octave Tuning Range and Low Phase Noise Multi-Core Mode-Switching Oscillator Using Compact Hybrid Parallel-Series Resonator	61
A 24.25–29.5-GHz CMOS Upconversion Transmitter With Built-In Automatic LO Feedthrough and I/Q Imbalance Calibration for 5G New Radio	60
Design of an Aging-Aware Memory With BTI-Mitigated SA and System-Visible Lifetime Management	60
A Separated Pre-Charge Sense Amplifier With Fast Sensing, Low Power, Small Area, and High Reliability for Hybrid MTJ/CMOS Logic Circuits	60
Bipartite Containment of Multi-Leader Multi-Agent Systems With Antagonistic Information and Measurement Noise	59
A 16.5-31 GHz Area-Efficient Tapered Tunable Transmission Line Phase Shifter	58
Nonlinear Capacitance Effect on Stability and Stabilization of SiGe Power Amplifiers for 17.3–21.2 GHz SATCOM	57
Adaptive Horizon Seeking for Generalized Predictive Control via Deep Reinforcement Learning With Application to DC/DC Converters	55
A Compact One-Transistor-Multiple-RRAM Characterization Platform	55
An 11T1C Bit-Level-Sparsity-Aware Computing- in-Memory Macro With Adaptive Conversion Time and Computation Voltage	54
An SDMT-Based CMOS Voltage Reference With a Novel NCC Scheme for PSRR Bandwidth Enhancement	54
Adaptive Formation for Multiagent Systems Subject to Denial-of-Service Attacks	53
Cross-Coupled Ferroelectric FET-Based Ternary Content Addressable Memory With Energy-Efficient Match Line Scheme	53
A 20 nW +0.8°C/-0.8°C Inaccuracy (3σ) Leakage-Based CMOS Temperature Sensor With Supply Sensitivity of 0.9°C/V	51
Voltage Control Ratiometric Readout Technique With Improved Dynamic Range and Power-Efficiency for Open-Loop MEMS Capacitive Accelerometer	50
Exploring Hybrid FitzHugh-Rinzel (FHR) Neuron Model Behavior: Cost-Effective FPGA Implementation for High-Frequency and High-Precision Matching by Electromagnetic Flux Effects	50
Parallel Delta-Sigma Modulator-Based Digital Predistortion of Wideband RF Power Amplifiers	50
Autaptic Self-Feedback for FPGA Realization and Real-Time Monitoring of Epileptic-Like Synchrony in Cubic–Quadratic Neuron Networks	50
FREYA: A 0.023-mm²/Channel, 20.8- μW/Channel, Event-Driven 8-Channel SoC for Spiking End-to-End Sensing of Time-Sparse Biosignals	49
Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode	48
Non-Linear Cyclic Variable Clock Feistel Bridge-Inspired Countermeasure for Securing RISC-V Crypto-Core Against Power Attacks	48
HLS-Based Algorithm-Hardware Co-Design of MIMO-OFDM Receiver for Tactical Jamming Suppression	48
A Self-Supervised Learning of a Foundation Model for Analog Layout Design Automation	47
Light-Weight Low-Latency Reconfigurable CORDIC Architecture With a New Non-Power-of-2 Angle Set of Microrotations	47
A Level Shifter With Almost Full Immunity to Positive dv/dt for Buck Converters	47
A Wide-Range Inter-Wire De-Skewing for IL Warping Mitigation in Spatially Correlated Coded Signaling-Based Transceiver	47
A Cryo-CMOS SAR ADC With FIA Sampling Driver Enabled by Cryogenic-Aware Back-Biasing	47
A Coupling Matrix Assisted Multi-Objective Optimization Scheme for Filters With Arbitrary Topology	46
Setting Up the State Equations of Switched Circuits Using Homogeneous Models	46
A Knowledge Distillation Online Training Circuit for Fault Tolerance in Memristor Crossbar Array-Based Neural Networks	46
A New Macromodeling Method Based on Deep Gated Recurrent Unit Regularized With Gaussian Dropout for Nonlinear Circuits	45
A Fully Symmetric Oscillator-Based CMOS Ising Machine Architecture With Successive Approximation Sampling and Power Efficient Solution Refinement	45
Fixed-Time Composite Anti-Disturbance Control for Flexible-Link Manipulators Based on Disturbance Observer	45
Compounding and Synchronization of Fractional Order Chaotic Systems With Prescribed Performance for Secure Communication	45
A Linear-Array Receiver AFE Circuit Embedded 8-to-1 Multiplexer for Direct ToF Imaging LiDAR Applications	45
Double-Ended Superposition Anti-Noise Resistance Monitoring Write Termination Scheme for Reliable Write Operation in STT-MRAM	45
Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference	45
IEEE Circuits and Systems Society Information	44
Digraph Filter Design Based on Directed Laplacian Matrix and Least Squares Method	43
IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors	43
IEEE Circuits and Systems Society Information	43
IEEE Circuits and Systems Society Information	43
Small Signal Modeling of a Four-Level Flying Capacitor Multilevel Totem-Pole PFC Converter	42
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	42
Robust Guaranteed Synchronization for Chaotic Systems With Incremental Quadratic Constraints	42
IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors	41
Guest Editorial Special Issue on the IEEE Latin American Symposium on Circuits and Systems (LASCAS 2023)	41

IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	40
Model-Independent Observer-Based Critically Damped Terminal Voltage Stabilization for Single Machine Infinite Bus Systems via High-Order Pole-Zero Cancellation Approach	40
Broadband GaAs HBT Doherty Power Amplifier Using Lumped Compensation Network and Input Phase Correction for 5G Applications	40
Guest Editorial TCAS-I Special Issue on the ESSERC 2024 Conference	40
Optimization of Quantum Circuits for Stabilizer Codes	40
Generalized Active N-Port Network Analysis for Load Modulation: Doherty Power Amplifier Incorporating Tri-Coupled-Line Combiner	40
A Triode-Based Analog Gate and Its Application in Chaotic Circuits	40
Design Approaches for Efficient Parallel Pseudo-Random Ternary Sequence Generation	40
QSAP: Energy and Area-Efficient Query-Based Sparsity-Aware Accelerator for Voxel-Based Point Cloud Neural Networks	40
Semi-Global Bounded Output Regulation of Linear Two-Time-Scale Systems With Input Saturation	39
Benchmarking of Scaled Majority-Logic-Synthesized Spintronic Circuits Based on Magnetic Tunnel Junction Transducers	39
Analog Spiking Neural Network Based Phase Detector	39
Table of Contents	38
Guest Editorial Special Issue on the International Symposium on Integrated Circuits and Systems—ISICAS 2025	38
A 3-bit Digitally-Reconfigurable Driving-Capability nW-Powered Three-Stage Fully-Synthesizable Inverter-Based OTA for Multi-Load/Applications	38
Compressed Sensing Σ-Δ Modulators and a Recovery Algorithm for Multi-Channel Wireless Bio-Signal Acquisition	38
CREAM: Computing in ReRAM-Assisted Energy- and Area-Efficient SRAM for Reliable Neural Network Acceleration	38
Output-Feedback Stabilization of Uncertain Nonlinear Systems With Multiple Unknown Control Directions via an Integrated Switching Controller	38
A 0.65-pJ/bit 3.6-TB/s/mm I/O Interface With XTalk Minimizing Affine Signaling for Next-Generation HBM With High Interconnect Density	37
Dual-Path Reactance Cell Theory and Its Application to a 6-bit K-Band True-Time-Delay Circuit	36
A Highly Power- and Area-Efficient PMU for Cell-Size Autonomous Microsystems	36
Virtual-Sensor-Based Model-Free Adaptive Fault-Tolerant Constrained Control for Discrete-Time Nonlinear Systems	36
A General Efficiency Enhancement Method for Compact Broadband Rectifiers	36
An AFD-Based ILC Dynamics Adaptive Matching Method in Frequency Domain for Distributed Consensus Control of Unknown Multiagent Systems	35
Machine Learning-Assisted Electro-Thermal Co-Optimization Framework for PDN in 3-D Integrated Microsystem With Embedded Microchannel Heatsink	35
Fault-Tolerant Consensus of Multi-Agent Systems Subject to Multiple Faults and Random Attacks	35
X-NVDLA: Runtime Accuracy Configurable NVDLA Based on Applying Voltage Overscaling to Computing and Memory Units	35
A Novel Method for Authentication Using Chaotic Behaviour of Chua’s Oscillator in (n,k) Secret Shared Data Scheme for Secure Communication	35
FAPSO: Fast Adaptive Particle Swarm Optimization-Based Background Timing Skew Calibration for TI-ADCs	35
A Dual 7T SRAM-Based Zero-Skipping Compute- In-Memory Macro With 1-6b Binary Searching ADCs for Processing Quantized Neural Networks	35
RIVL: A Low-Cost SoC Agile Development Platform for Multiple RISC-V Processors Design and Verification	34
Adaptive Switching Control for Nonlinear Uncertain Systems With Sensor Faults and Quantization	34
CINOC: Computing in Network-On-Chip With Tiled Many-Core Architectures for Large-Scale General Matrix Multiplications	34
Table of Contents	34
Frequency-Flexible High Selectivity Multichannel Filtering Crossover Based on Slow-Wave Substrate Integrated Waveguide	34
Event-Driven Vision Sensor With In-Pixel Spatial Contrast Computation Capabilities and On-Chip AER Sequencer	34
Skew-CIM: Process-Variation-Resilient and Energy-Efficient Computation-in-Memory Design Technique With Skewed Weights	34
Finite-Time Dissipative Tracking Control of Semi-Markov Jump Systems Under Multi-Channel Hybrid Attacks	34
Infinite Horizon Stabilization and Linear Quadratic Optimal Control of Descriptor Stochastic Markov Jump Systems	34
A 0.0106 mm ² 8 nW Resistor-Less BJT Bandgap Reference Circuit in 65 nm CMOS With Orthogonal Voltage and Temperature Coefficient Trims	34
Analysis and Design of a Novel Gain-Boosting Technique Based on Lossy Series Embedding Network for Near- f _max	33
How Do Higher-Order Interactions Affect the Dynamic Evolution of Layered Neural Networks	33
The Mismatch Performance of Pseudo Digital Ring Oscillators Used in VCO ADCs: PSRR and CMRR	33
An Energy-Efficient Accelerator for Medical Image Reconstruction From Implicit Neural Representation	33
Bandwidth-Enhanced Mixed-Mode Outphasing Power Amplifiers Based on the Analytic Role-Exchange Doherty-Chireix Continuum Theory	33
Latency Insertion Method for Fast FinFET Simulation Based on the BSIM-CMG Model	33
Reconfigurable 2.4/5.0-GHz Dual-Band CMOS Power Amplifier for WLAN 802.11ax	33
An Energy-Efficient Channel-Wise Segmented Sparse BNN Accelerator With Algorithm–Hardware Co-Optimization for Gesture Recognition	33
Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K	33
Robust Fuzzy Control of Network-Type Re-Entrant Manufacturing Systems With Communication Delays	33
Stackelberg and Nash Equilibrium Computation in Non-Convex Leader-Follower Network Aggregative Games	33
Resilient Decentralized Frequency Regulation for Multi-Area Power Systems With Electric Vehicles Under Hybrid Cyber-Attacks	33
Finite-Time Stabilization of Semi-Markov Reaction-Diffusion Memristive NNs With Unbounded Time-Varying Delays	33
A Highly Stable Physically Unclonable Function Using Algorithm-Based Mismatch Hardening Technique in 28-nm CMOS	33
Highly Dense Capacitor SRAM Computation-In-Memory With Dynamic Range Calibrated Column-by-Column ADCs	32
EAGLE: A Flexible Heterogeneous Analog Compute-In-Memory Architecture With RISC-V Programmable Multi-Core Accelerators	32
Bayesian Deep-Learning Processor for Real-Time Bio-Applications With Structured Monte Carlo Dropout for High-Volume Sample Generation	32
Accelerating Deep Convolutional Neural Networks Using Number Theoretic Transform	32
A Switched Capacitor Modified Fibonacci Cell Used for a DC–AC Circuit Supplied by Solar Energy	32
An Energy-Efficient Capacitive-RRAM Content Addressable Memory	31
SoC Reconfigurable Architecture for Implementing Software Trained Recurrent Neural Networks on FPGA	31
Homogeneous Versus Heterogeneous Graph Representation for Graph Neural Network Tasks on Electric Circuits	31
A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks	31
IEEE Circuits and Systems Society Information	31
Flocking Dynamics for Cooperation-Antagonism Multi-Agent Networks Subject to Limited Communication Resources	31
Table of Contents	31
110–170 GHz On-Chip Calibration Using Deep Neural Networks	31
Table of Contents	30
An Adaptive Fully Integrated Wide-Range Power Management Unit With Fractional Charge Pump for Micro-Scale Energy Harvesting Applications	30
Guest Editorial Special Issue on the International Symposium on Integrated Circuits and Systems—ISICAS 2023	30
Flexible FPGA Gaussian Random Number Generators With Reconfigurable Variance	30
Introducing IEEE Collabratec	30
Efficiency Enhancement Technique for Outphasing Amplifier With Extended Power Back-Off Range	30
Scalable Multi-Stage CMOS OTAs With a Wide C_L-Drivability Range Using Low-Frequency Zeros	29
FireFly-S: Exploiting Dual-Side Sparsity for Spiking Neural Networks Acceleration With Reconfigurable Spatial Architecture	29
Bipartite Event-Triggered Output Tracking Consensus of Heterogeneous Linear Multi-Agent Systems Under Switching Directed Topologies	29
Trio-ViT: Post-Training Quantization and Acceleration for Softmax-Free Efficient Vision Transformer	29
A 7T-NDR Dual-Supply 28-nm FD-SOI Ultra-Low Power SRAM With 0.23-nW/kB Sleep Retention and 0.8 pJ/32b Access at 64 MHz With Forward Back Bias	29
A 36–55 V Input 0.6–2.5 V Output Bypass-Assist Series-Capacitor Power Converter With 93.1% Peak Efficiency and 1.5 mA–5 A Load Range	29
Intelligent Coordination of Traditional Power Plants and Inverters Air Conditioners Controlled With Feedback-Corrected MPC in LFC	28

SPP-CNN: An Efficient Framework for Network Robustness Prediction	28
Programmable In-Memory Computing Circuit for Solving Combinatorial Matrix Operation in One Step	28
IEEE Circuits and Systems Society Information	28
CoDeepCL-Based Oscillation-Adaptive and Label-Free Instability Detection Approach for DC Power Electronic Systems	28
Entrainment of Mutually Synchronized Spatially Distributed 24 GHz Oscillators	28
A 5-mW 30-GHz Quasi-Rotary Traveling-Wave Oscillator With Extrinsic-Q-Enhanced Transmission Line	28
DQ-STP: An Efficient Sparse On-Device Training Processor Based on Low-Rank Decomposition and Quantization for DNN	28
From Relaxation to Chaotic Oscillations: A New Paradigm for Memristor Circuits	28
A Critical-Set-Based Multi-Bit Successive Cancellation List Decoder for Polar Codes: Algorithm and Implementation	27
IEEE Circuits and Systems Society Information	27
Low Latency SEU Detection in FPGA CRAM With In-Memory ECC Checking	27
Editorial A New Exciting Year Ahead for TCAS-I	27
Digital Low-Cost FPGA Implementation of Two-Coupled and Grid-Based Network of 2D Artificial Cochlea Using the Hopf Resonator Approach	27
Data-Driven Control Algorithms for Unknown Discrete-Time Linear Periodic Systems	27
Optimization of DTC-Based and Harmonic-Mixer-Based Fractional-N PLLs: Comparative Analysis of Jitter and Power Trade-Offs	27
A Resonant Switched-Capacitor Parallel Inductor Hybrid Buck Converter	27
An Advanced Fault-Tolerant HANPC Converter With Neutral-Point Voltage Balancing for Full Power Factor Range Under Multi-Switch Open-Circuit Fault	27
PRADO: A Low-Latency and Energy-Efficient 6DoF Pose Refinement Accelerator With Domain-Specific Explorations	27
Design and Analysis of a Resistive Frequency-Locked Oscillator With Long-Term Stability Using Double Chopper Stabilization	27
An Open-Circuit Fault Diagnosis for Three-Phase PWM Rectifier Without Grid Voltage Sensor Based on Phase Angle Partition	27
Floquet Modulation Optimizing the Tunable Isolators Based on PT-Symmetric LCR Resonators	27
A Novel Approach to Prescribed-Time Cooperative Output Regulation in Linear Heterogeneous Multi-Agent Systems Using Cascade System Criteria	27
A Capacitor-Cross-Connected Boost Converter With Duty Cycle < 0.5 Control for Extended Conversion-Ratio and Soft Start-Up	26
Pole-Zero Cancellation Speed and Acceleration Filtering Technique With Disturbance Observer for Servo Drive Applications Without Model Parameter Information	26
Semiglobal Finite-Time Stability of Impulsive Systems	26
Novel Digital Conversion and Power Amplifier Linearization Unit for Wireless Transmitters	26
Fixed-Point Kernel Adaptive Filtering for Fractional-Order Nonlinear Dynamical Systems With Applications to Chaotic Circuits	26
Optimal Subband Adaptive Filter Over Functional Link Neural Network: Algorithms and Applications	26
A Reconfigurable Floating-Point Division and Square Root Architecture for High-Precision Softmax	26
Modeling and Adaptive Parameter Estimation for a Piezoelectric Cantilever Beam	26
A K-/Ka-Band Broadband Low-Noise Amplifier Based on the Multiple Resonant Frequency Technique	26
A Low-Cost Digital Capacitor Current Estimation Algorithm Based on Parameter Identification for Buck Converter Application	26
Memristor-Based Neural Network Circuit of Full-Function Pavlov Associative Memory With Unconditioned Response Mechanisms	26
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	26
A Current-Driven SSHI for Piezoelectric Vibration Energy Harvesters	26
A 144- μW Phase-Interval Balanced RVCO With 142% Tuning Range and 218.2-dBc/Hz FoM _TA	26
Enhancement in Dynamic Performance of Multi-Converter Architecture	25
Bipartite Consensus for Quantization Communication Multi-Agents Systems With Event-Triggered Random Delayed Impulse Control	25
RRAM-Based Computing-in-Memory FPGA Architecture for Low-Power Applications	25
Attractor Dynamics of 2-Lobe Discrete Corsage Memristor-Coupled Neuron Map	25
A 15–28 GHz Low-Noise Amplifier With 0.75-dB Gain Ripple Across the Full K-Band	25
A 12.5-GS/s 4× TI Pipelined Hybrid TD-SAR ADC With Residual Time-Voltage Amplification	25
Dynamic Event-Triggered Target Encirclement Control for Heterogeneous UAV/UGV Swarm Based on Finite-Time Distributed Target Observation	25
A Compact Dual-Mode SAR ADC With Mismatch Error Shaping Using Prediction-Error-Free 3-Level Analog Prediction and 1-bit Barrel-Shift Dithering	25
Comprehensive Evaluation of Toroid Ring Core Parallel Inductor and Resistor as a Transformer Protection Device	25
A Novel Memristive Combinational Logic for Accelerating N-bit Adders	25
A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks	25
Reinforcement Learning Solutions to Stochastic Multi-Agent Graphical Games With Multiplicative Noise	25
A 28 nm 16 Kb Bit-Scalable Charge-Domain Transpose 6T SRAM In-Memory Computing Macro	25
A −79 dBm 7.56 nW 433 MHz Wake-Up Receiver With Interference Suppression for IoT Application	25
Dynamic Tsetlin Machine Accelerators for On-Chip Training Using FPGAs	25
Concurrent Learning Adaptive Command Filtered Backstepping Control for High-Order Strict-Feedback Systems	25
A Flexible Impedance Modeling Method and Stability Analysis Toward the Cascaded Solid-State Transformer	25
CMOS Current Driver for Electrothermal MEMS Switches With Actuation and Diagnostic Circuitry	25
A Sub-Nanosecond Delay Floating Voltage Level Shifter With 300 V/ns Power Supply Slew Tolerance	24
A 0.35-V Untrimmed BJT-Based Temperature Sensor Achieving −1.0/+0.86 ^° C (p-p) Inaccuracy From –40 ^°	24
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	24
APCCAS 2022 Guest Editorial Special Issue Based on the 18th Asia Pacific Conference on Circuits and Systems	24
A High-Accuracy Single-Photon Time-Interval Measurement in Mega-Hz Detection Rates With Collaborative Variance Reduction: Theoretical Analysis and Realization Methodology	24
Interdependence Among Voltage-Unstable Buses During Cascading Failure in Power Systems	24
Edge-Side Fine-Grained Sparse CNN Accelerator With Efficient Dynamic Pruning Scheme	24
A Loop-Break Decision Feedback Equalizer for DAC/ADC-DSP-Based Wireline Transceivers	24
Stabilization of Impulsive Systems With Beyond-Interval Impulse Delays	24
IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors	24
Impact of Non-Idealities on the Behavior of Probabilistic Computing: Theoretical Investigation and Analysis	24
A Class-C CMOS Rectifier With Active Modulation Achieving >76% Peak Efficiency and Extended Input Power Range Over 8.8 dB Across Multiple Frequency Bands	24
A High-Efficiency RFEH System With Feedback-Free Fast (F ³ ) MPPT Over a Wide Input Range	24
SyPoDA: A Synergetic Power-Delivery Architecture for Simultaneous Flash Charging and Dual-Output Point-of-Load Supplies	24
Table of Contents	24
Effect of Device Mismatches in Differential Oscillatory Neural Networks	24
A High-Voltage Differential SPDT T/R Switch for Ultrasound Systems	24
A 2 MHz Bandwidth Area-Efficient Multipath Hall Sensor With a Residual Ripple of 4.1 μT	24
Clock Period-Jitter Measurement With Low-Noise Runtime Calibration for Chips in FinFET CMOS	24
Fast Scloud ⁺ : A High-Speed Hardware Implementation for Unstructured-LWE-Based Post-Quantum Cryptography	23
A 0.4–0.9 V Supply Voltage-Flexible Third-Order Passive ΔΣ Modulator With Switched-Capacitor Loop Filter Achieving 71.9 dB Peak SNDR at 4 MHz Bandwidth	23
Fast FPGA Prototyping to Explore and Compare New SPWM Strategies	23
A 16–20 GHz Mixer First Receiver Architecture With Active Inductor-Based Low-Pass Elliptic Filter With High OOB-IIP3 in 180 nm CMOS	23
ARBiS: A Hardware-Efficient SRAM CIM CNN Accelerator With Cyclic-Shift Weight Duplication and Parasitic-Capacitance Charge Sharing for AI Edge Application	23
A Low-Cost Pipelined Architecture Based on a Hybrid Sorting Algorithm	23
Ferroelectric FET Nonvolatile Sense-Amplifier-Based Flip-Flops for Low Voltage Operation	23
An E-Band Bidirectional Front-End With 20.9 dBm Peak Output Power in GaAs Process	23
An 8-ppm/°C 100-MHz RC Oscillator With Implicit Temperature Compensation and Resistor Aging Characterization	23
Artificial Neural Network Based on Memristive Circuit for High-Speed Equalization	23
An Energy Efficient STDP-Based SNN Architecture With On-Chip Learning	23
A Multi-Channel Auditory Signal Encoder With Adaptive Resolution Using Volatile Memristors	23
A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique	23
Memristor-Based Temporal Memory Neural Network Circuit Influenced by Emotional Arousal and Memory Interaction	23
DCiROM: A High-Density Fully-Digital Compute-in-Read-Only-Memory Macro for Energy-Efficient Task-Level DNN Inference	23
Low-Power Capacitively Coupled AC Amplifiers With Tunable Ultra Low-Frequency Operation	23
Broadband Doherty Power Amplifier Using Short Ended λ/4 Transmission Lines Based on the Analysis of Negative Characteristic Impedance	23
ML-Based Fully-Numerical Design Method for Load-Independent Class-EF WPT Systems	23
Modeling and Mitigating the Interconnect Resistance Issue in Analog RRAM Matrix Computing Circuits	23
CLAT: A Clustering-Based Attention Transformer Accelerator for Low-Latency Text Generation in LLMs	23
Efficient Adaptive Multi-Level Privilege Partitioning With RTrustSoC	23
Passive Post-Resonance Tuned Reflectors to Achieve Both 10-bit Phase-Shifting Resolution and Low Insertion Loss Across 20–30 GHz	23