OOIR: Observatory of International Research

Papers

(The H4-Index of IEEE Transactions on Circuits and Systems I-Regular Papers is 49. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-11-01 to 2025-11-01.)

Article	Citations
TechRxiv: Share Your Preprint Research with the World!	190
IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	171
Learning, Optimization, and Implementation for Circuits and Systems driven by Artificial Intelligence	151
IEEE Open Access Publishing	149
TechRxiv: Share Your Preprint Research with the World!	133
A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined ADCs	127
IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	98
Implementation of Group-Approximate Expectation Propagation Algorithm for Uplink MIMO-SCMA Detection Using 16-Point Codebook	98
Pipe-LPAQ: A Fully Pipelined Architecture for LPAQ Data Compression on FPGA	97
FREYA: A 0.023-mm²/Channel, 20.8- μW/Channel, Event-Driven 8-Channel SoC for Spiking End-to-End Sensing of Time-Sparse Biosignals	94
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	88
FPGA Accelerator for Real-Time Non-Line-of-Sight Imaging	85
A 1.6-V Tolerant Multiplexer Switch With 0.96-V Core Devices in 28-nm CMOS Technology	82
Data-Driven Fault-Tolerant Control Framework for EV Dynamic Wireless Power Transfer System Based on Self-Learning Predictor	78
Novel Optimized Implementations of Lightweight Cryptographic S-Boxes via SAT Solvers	77
A Cryo-CMOS SAR ADC With FIA Sampling Driver Enabled by Cryogenic-Aware Back-Biasing	76
A Compact One-Transistor-Multiple-RRAM Characterization Platform	74
Proposal of Analog In-Memory Computing With Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell	71
Multi-Objective Surrogate-Model-Based Neural Architecture and Physical Design Co-Optimization of Energy Efficient Neural Network Hardware Accelerators	70
A 1-GS/s 12-bit Pipelined-SAR ADC With Dither-Based Background Calibration of Interstage Gain and Comparator Offset in 28-nm CMOS	68
Design of Miniaturized Sub-6 GHz Rectifier With Self-Impedance Matching Technique	66
A 20 MHz–2 GHz Inductorless Two-Fold Noise-Canceling Low-Noise Amplifier in 28-nm CMOS	66
A TM-Based Adaptive Learning Data-Model for Trajectory Tracking and Real-Time Control of a Class of Nonlinear Systems	64
On the Efficacy and Vulnerabilities of Logic Locking in Tree-Based Machine Learning	63
Nonlinear Capacitance Effect on Stability and Stabilization of SiGe Power Amplifiers for 17.3–21.2 GHz SATCOM	62

A Linear-Array Receiver AFE Circuit Embedded 8-to-1 Multiplexer for Direct ToF Imaging LiDAR Applications	62
Digital Time-Domain Predistortion of Linear Periodically Time-Varying Effects and Its Application to a 100-GS/s Time-Interleaved CMOS DAC	61
A New Macromodeling Method Based on Deep Gated Recurrent Unit Regularized With Gaussian Dropout for Nonlinear Circuits	61
A RISC-V Domain-Specific Processor for Deep Learning-Based Channel Estimation	61
A Consistency Enhancement Technique for MIMO Power Amplifier Modules	61
Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode	60
Cross-Coupled Ferroelectric FET-Based Ternary Content Addressable Memory With Energy-Efficient Match Line Scheme	59
Setting Up the State Equations of Switched Circuits Using Homogeneous Models	58
Retraction Notice: Robustness Margins for Attainable Consensusability of Unstable Multi-Agent Systems: Output Consensus Protocols Over Directed Network Topology	58
An All NMOS KY-Boost Converter With Double Injection Control for Fast Line and Load Transient Response	58
Double-Ended Superposition Anti-Noise Resistance Monitoring Write Termination Scheme for Reliable Write Operation in STT-MRAM	58
Parallel Delta-Sigma Modulator-Based Digital Predistortion of Wideband RF Power Amplifiers	56
Programmable Analog-to-Digital Converter Array Supporting Architecture Restructuring and Mode Concurrency	55
Non-Linear Cyclic Variable Clock Feistel Bridge-Inspired Countermeasure for Securing RISC-V Crypto-Core Against Power Attacks	54
Exploring Hybrid FitzHugh-Rinzel (FHR) Neuron Model Behavior: Cost-Effective FPGA Implementation for High-Frequency and High-Precision Matching by Electromagnetic Flux Effects	53
Light-Weight Low-Latency Reconfigurable CORDIC Architecture With a New Non-Power-of-2 Angle Set of Microrotations	53
A Novel Design Method for CML Frequency Divider Based on C/I_d and G/I_d and Application for Quadrature-Injection	53
Bipartite Containment of Multi-Leader Multi-Agent Systems With Antagonistic Information and Measurement Noise	52
A Fully Symmetric Oscillator-Based CMOS Ising Machine Architecture With Successive Approximation Sampling and Power Efficient Solution Refinement	52
A 20 nW +0.8°C/-0.8°C Inaccuracy (3σ) Leakage-Based CMOS Temperature Sensor With Supply Sensitivity of 0.9°C/V	52
0.4-V Tail-Less Quasi-Two-Stage OTA Using a Novel Self-Biasing Transconductance Cell	52
A Wide-Range Inter-Wire De-Skewing for IL Warping Mitigation in Spatially Correlated Coded Signaling-Based Transceiver	51
Fast Algorithms for Resistance Distances on Signed Graphs	50
A Knowledge Distillation Online Training Circuit for Fault Tolerance in Memristor Crossbar Array-Based Neural Networks	49
A Proximal ADMM-Based Distributed Optimal Energy Management Approach for Smart Grid With Stochastic Wind Power	49
Compounding and Synchronization of Fractional Order Chaotic Systems With Prescribed Performance for Secure Communication	49