OOIR: Observatory of International Research

Papers

(The H4-Index of IEEE Transactions on Circuits and Systems I-Regular Papers is 51. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-05-01 to 2025-05-01.)

Article	Citations
TechRxiv: Share Your Preprint Research with the World!	292
Setting Up the State Equations of Switched Circuits Using Homogeneous Models	223
A Cryo-CMOS SAR ADC With FIA Sampling Driver Enabled by Cryogenic-Aware Back-Biasing	169
Double-Ended Superposition Anti-Noise Resistance Monitoring Write Termination Scheme for Reliable Write Operation in STT-MRAM	167
An All NMOS KY-Boost Converter With Double Injection Control for Fast Line and Load Transient Response	164
Implementation of Group-Approximate Expectation Propagation Algorithm for Uplink MIMO-SCMA Detection Using 16-Point Codebook	128
A 16.5-31 GHz Area-Efficient Tapered Tunable Transmission Line Phase Shifter	125
Control of Power Converters With Hybrid Affine Models and Pulse-Width Modulated Inputs	124
A Fast and Fully Parallel Analog CMOS Solver for Nonlinear PDEs	118
Synthesis of an Equivalent Circuit for Spike-Timing-Dependent Axon Growth: What Fires Together Now Really Wires Together	117
A Proximal ADMM-Based Distributed Optimal Energy Management Approach for Smart Grid With Stochastic Wind Power	114
A Level Shifter With Almost Full Immunity to Positive dv/dt for Buck Converters	114
Adaptive Horizon Seeking for Generalized Predictive Control via Deep Reinforcement Learning With Application to DC/DC Converters	102
Online Identification of Piecewise Affine Systems Using Integral Concurrent Learning	98
A 1.6-V Tolerant Multiplexer Switch With 0.96-V Core Devices in 28-nm CMOS Technology	93
A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined ADCs	88
A TM-Based Adaptive Learning Data-Model for Trajectory Tracking and Real-Time Control of a Class of Nonlinear Systems	84
FPGA Accelerator for Real-Time Non-Line-of-Sight Imaging	82
Fixed-Time Composite Anti-Disturbance Control for Flexible-Link Manipulators Based on Disturbance Observer	81
Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference	77
An 11T1C Bit-Level-Sparsity-Aware Computing- in-Memory Macro With Adaptive Conversion Time and Computation Voltage	75
A 25 MHz Fast Transient Adaptive-On/Off-Time Controlled Three-Level Buck Converter	75
Multi-Objective Surrogate-Model-Based Neural Architecture and Physical Design Co-Optimization of Energy Efficient Neural Network Hardware Accelerators	74
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	73
IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	71

IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	69
IEEE Open Access Publishing	69
IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors	69
Light-Weight Low-Latency Reconfigurable CORDIC Architecture With a New Non-Power-of-2 Angle Set of Microrotations	67
Learning, Optimization, and Implementation for Circuits and Systems driven by Artificial Intelligence	65
A 20 MHz–2 GHz Inductorless Two-Fold Noise-Canceling Low-Noise Amplifier in 28-nm CMOS	64
A Novel Design Method for CML Frequency Divider Based on C/I_d and G/I_d and Application for Quadrature-Injection	63
A Consistency Enhancement Technique for MIMO Power Amplifier Modules	63
TechRxiv: Share Your Preprint Research with the World!	63
Non-Linear Cyclic Variable Clock Feistel Bridge-Inspired Countermeasure for Securing RISC-V Crypto-Core Against Power Attacks	62
FREYA: A 0.023-mm²/Channel, 20.8- μW/Channel, Event-Driven 8-Channel SoC for Spiking End-to-End Sensing of Time-Sparse Biosignals	62
0.4-V Tail-Less Quasi-Two-Stage OTA Using a Novel Self-Biasing Transconductance Cell	61
Nonlinear Capacitance Effect on Stability and Stabilization of SiGe Power Amplifiers for 17.3–21.2 GHz SATCOM	58
Exploring Hybrid FitzHugh-Rinzel (FHR) Neuron Model Behavior: Cost-Effective FPGA Implementation for High-Frequency and High-Precision Matching by Electromagnetic Flux Effects	57
A 20 nW +0.8°C/-0.8°C Inaccuracy (3σ) Leakage-Based CMOS Temperature Sensor With Supply Sensitivity of 0.9°C/V	56
Programmable Analog-to-Digital Converter Array Supporting Architecture Restructuring and Mode Concurrency	56
On the Efficacy and Vulnerabilities of Logic Locking in Tree-Based Machine Learning	56
A New Macromodeling Method Based on Deep Gated Recurrent Unit Regularized With Gaussian Dropout for Nonlinear Circuits	54
A 3-Phase Resonant Switched-Capacitor Converter for Data Center 48-V Rack Power Distribution	54
Adaptive Formation for Multiagent Systems Subject to Denial-of-Service Attacks	53
Novel Optimized Implementations of Lightweight Cryptographic S-Boxes via SAT Solvers	53
Cross-Coupled Ferroelectric FET-Based Ternary Content Addressable Memory With Energy-Efficient Match Line Scheme	53
Design of Digital OTAs With Operation Down to 0.3 V and nW Power for Direct Harvesting	52
Voltage Control Ratiometric Readout Technique With Improved Dynamic Range and Power-Efficiency for Open-Loop MEMS Capacitive Accelerometer	52
Bipartite Containment of Multi-Leader Multi-Agent Systems With Antagonistic Information and Measurement Noise	52
Compounding and Synchronization of Fractional Order Chaotic Systems With Prescribed Performance for Secure Communication	51