OOIR: Observatory of International Research

Papers

(The H4-Index of IEEE Transactions on Circuits and Systems I-Regular Papers is 49. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-06-01 to 2026-06-01.)

Article	Citations
TechRxiv: Share Your Preprint Research with the World!	168
Learning, Optimization, and Implementation for Circuits and Systems driven by Artificial Intelligence	160
IEEE Open Access Publishing	126
Implementation of Group-Approximate Expectation Propagation Algorithm for Uplink MIMO-SCMA Detection Using 16-Point Codebook	121
IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information	120
Non-Linear Cyclic Variable Clock Feistel Bridge-Inspired Countermeasure for Securing RISC-V Crypto-Core Against Power Attacks	118
Digital Time-Domain Predistortion of Linear Periodically Time-Varying Effects and Its Application to a 100-GS/s Time-Interleaved CMOS DAC	102
Parallel Delta-Sigma Modulator-Based Digital Predistortion of Wideband RF Power Amplifiers	98
Welcome to a New Term in TCAS-I	98
A Compact One-Transistor-Multiple-RRAM Characterization Platform	87
Retraction Notice: Robustness Margins for Attainable Consensusability of Unstable Multi-Agent Systems: Output Consensus Protocols Over Directed Network Topology	86
A Wide-Range Inter-Wire De-Skewing for IL Warping Mitigation in Spatially Correlated Coded Signaling-Based Transceiver	85
An 11T1C Bit-Level-Sparsity-Aware Computing- in-Memory Macro With Adaptive Conversion Time and Computation Voltage	78
Fast Algorithms for Resistance Distances on Signed Graphs	78
A 1-GS/s 12-bit Pipelined-SAR ADC With Dither-Based Background Calibration of Interstage Gain and Comparator Offset in 28-nm CMOS	74
A Fully Symmetric Oscillator-Based CMOS Ising Machine Architecture With Successive Approximation Sampling and Power Efficient Solution Refinement	69
FREYA: A 0.023-mm²/Channel, 20.8- μW/Channel, Event-Driven 8-Channel SoC for Spiking End-to-End Sensing of Time-Sparse Biosignals	69
A Proximal ADMM-Based Distributed Optimal Energy Management Approach for Smart Grid With Stochastic Wind Power	68
Programmable Analog-to-Digital Converter Array Supporting Architecture Restructuring and Mode Concurrency	66
On the Efficacy and Vulnerabilities of Logic Locking in Tree-Based Machine Learning	65
An All NMOS KY-Boost Converter With Double Injection Control for Fast Line and Load Transient Response	64
Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference	63
Novel Optimized Implementations of Lightweight Cryptographic S-Boxes via SAT Solvers	60
Light-Weight Low-Latency Reconfigurable CORDIC Architecture With a New Non-Power-of-2 Angle Set of Microrotations	60
A 20 nW +0.8°C/-0.8°C Inaccuracy (3σ) Leakage-Based CMOS Temperature Sensor With Supply Sensitivity of 0.9°C/V	60

A New Macromodeling Method Based on Deep Gated Recurrent Unit Regularized With Gaussian Dropout for Nonlinear Circuits	60
Exploring Hybrid FitzHugh-Rinzel (FHR) Neuron Model Behavior: Cost-Effective FPGA Implementation for High-Frequency and High-Precision Matching by Electromagnetic Flux Effects	59
Design of Miniaturized Sub-6 GHz Rectifier With Self-Impedance Matching Technique	58
Double-Ended Superposition Anti-Noise Resistance Monitoring Write Termination Scheme for Reliable Write Operation in STT-MRAM	57
A 16.5-31 GHz Area-Efficient Tapered Tunable Transmission Line Phase Shifter	57
Adaptive Formation for Multiagent Systems Subject to Denial-of-Service Attacks	57
Frequency Response Model for Power Systems Including HVDC-Connected Offshore Wind Power With Communication-Free Frequency Control	57
A 4.25–8.45-GHz 67% Chirp-Fractional Bandwidth −121.5-dBc/Hz PN at 1-MHz 88-fs Jitter FMCW Synthesizer With Fractional-Bandwidth-Boosting and Phase-Noise-Cancellation Techniques	56
Pipe-LPAQ: A Fully Pipelined Architecture for LPAQ Data Compression on FPGA	56
A Handgrip-Responsive mmWave Phased Array Antenna-PA Module With Antenna-Based Capacitive Sensor for EIRP Recovery via Adaptive Current Redistribution	56
Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode	55
A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined ADCs	54
A Cryo-CMOS SAR ADC With FIA Sampling Driver Enabled by Cryogenic-Aware Back-Biasing	54
A Consistency Enhancement Technique for MIMO Power Amplifier Modules	54
Data-Driven Fault-Tolerant Control Framework for EV Dynamic Wireless Power Transfer System Based on Self-Learning Predictor	54
A Novel Design Method for CML Frequency Divider Based on C/I_d and G/I_d and Application for Quadrature-Injection	53
A Simultaneous Bidirectional Link With 6–12.8-Gb/s Forward and 12–25.6-Gb/s Backward Channels for System Chips Interconnects	53
Guest Editorial TCAS-I Special Issue Guest Editorial Based on the 16th IEEE Latin American Symposium on Circuits and Systems	53
HLS-Based Algorithm-Hardware Co-Design of MIMO-OFDM Receiver for Tactical Jamming Suppression	52
A Linear-Array Receiver AFE Circuit Embedded 8-to-1 Multiplexer for Direct ToF Imaging LiDAR Applications	52
Multi-Objective Surrogate-Model-Based Neural Architecture and Physical Design Co-Optimization of Energy Efficient Neural Network Hardware Accelerators	51
A RISC-V Domain-Specific Processor for Deep Learning-Based Channel Estimation	51
Bipartite Containment of Multi-Leader Multi-Agent Systems With Antagonistic Information and Measurement Noise	50
Nonlinear Capacitance Effect on Stability and Stabilization of SiGe Power Amplifiers for 17.3–21.2 GHz SATCOM	49