ACM Transactions on Architecture and Code Optimization

Papers
(The TQCC of ACM Transactions on Architecture and Code Optimization is 4. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-08-01 to 2026-08-01.)
ArticleCitations
TNT: A Modular Approach to Traversing Physically Heterogeneous NOCs at Bare-wire Latency62
ASM: An Adaptive Secure Multicore for Co-located Mutually Distrusting Processes52
ESMPC: An Efficient Neural Network Training Framework for Secure Two- and Three-Party Computation38
Accelerating Verifiable Queries over Blockchain Database System Using Processing-in-memory33
Intra-request Lag-aware Cache Management to Enhance I/O Responsiveness of SSDs31
Highly Efficient Self-checking Matrix Multiplication on Tiled AMX Accelerators30
Supporting QoS Guarantee in Heterogeneous Object Storage System: A Spatio-Temporal Graph Data Processing Method30
An Intelligent Scheduling Approach on Mobile OS for Optimizing UI Smoothness and Power29
Performance, Energy and NVM Lifetime-Aware Data Structure Refinement and Placement for Heterogeneous Memory Systems29
HierMine: Accelerating Graph Pattern Mining via Hierarchical Sampling27
Characterizing Digital DRAM PIM through Modeling and Benchmarking26
ModNEF : An Open Source Modular Neuromorphic Emulator for FPGA for Low-Power In-Edge Artificial Intelligence25
TransCL: An Automatic CUDA-to-OpenCL Programs Transformation Framework25
Tiaozhuan: A General and Efficient Indirect Branch Optimization for Binary Translation22
A Concise Concurrent B + -Tree for Persistent Memory20
COER: A Network Interface Offloading Architecture for RDMA and Congestion Control Protocol Codesign18
Source Matching and Rewriting for MLIR Using String-Based Automata18
DCMA: Accelerating Parallel DMA Transfers with a Multi-Port Direct Cached Memory Access in a Massive-Parallel Vector Processor18
Fast Convolution Meets Low Precision: Exploring Efficient Quantized Winograd Convolution on Modern CPUs17
Enabling Efficient All-Dimension Top-k Sparsification for High-Performance Distributed DNN Training Systems15
DeepZoning: Re-accelerate CNN Inference with Zoning Graph for Heterogeneous Edge Cluster14
Osiris: A Systolic Approach to Accelerating Fully Homomorphic Encryption14
iSwap: A New Memory Page Swap Mechanism for Reducing Ineffective I/O Operations in Cloud Environments14
A NUMA-Aware Version of an Adaptive Self-Scheduling Loop Scheduler13
Mentor: A Memory-Efficient Sparse-dense Matrix Multiplication Accelerator Based on Column-Wise Product13
PredComp: Predicting Compiler Optimization Options with Multi-stage Learning12
FlashGEMM: Optimizing Sequences of Matrix Multiplication by Exploiting Data Reuse on CPUs12
MLKAPS: Machine Learning and Adaptive Sampling for HPC Kernel Auto-tuning11
Accelerating Nearest Neighbor Search in 3D Point Cloud Registration on GPUs11
SnsBooster: Enhancing Sampling-based μ Arch Evaluation Efficiency through Online Performance Sensitivity Analysis11
Flexible and Effective Object Tiering for Heterogeneous Memory Systems11
ODGS: Dependency-Aware Scheduling for High-Level Synthesis with Graph Neural Network and Reinforcement Learning11
Mitigating the Bandwidth Wall via Data-Streaming System–Accelerator Co-Design11
AG-SpTRSV: An Automatic Framework to Optimize Sparse Triangular Solve on GPUs11
Power Scheduling for Maximizing Throughput and Fairness in Co-running Applications10
Quantifying Resource Contention of Co-located Workloads with the System-level Entropy10
Towards high scalability and fine-grained parallelism on distributed HPC platforms10
COX : Exposing CUDA Warp-level Functions to CPUs10
GraphSER: Distance-Aware Stream-Based Edge Repartition for Many-Core Systems10
Accelerating Parallel Structures in DNNs via Parallel Fusion and Operator Co-Optimization10
FDSR: Efficient Model Training via Adaptive Tensor Quantization Based on Frequency Domain Division and Similarity Data Reuse10
A Step toward Stateful HW-SW Migration: An Architecture-agnostic Checkpointing-rollback Toolchain9
Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture9
A Fast and Flexible FPGA-based Accelerator for Natural Language Processing Neural Networks9
BridgeGC: An Efficient Cross-Level Garbage Collector for Big Data Frameworks9
NEM-GNN: DAC/ADC-less, Scalable, Reconfigurable, Graph and Sparsity-Aware Near-Memory Accelerator for Graph Neural Networks9
CLAP: Cross-Layer Adaptive Pipelining Inference Scheduling for Resource-Efficient Edge-Cloud Vision Systems9
EXPERTISE: An Effective Software-level Redundant Multithreading Scheme against Hardware Faults9
Advancing Direct Convolution Using Convolution Slicing Optimization and ISA Extensions9
Optimizing Attention for Large Language Model Inference on the MT-3000 Many-Core Processor9
RT-GNN: Accelerating Sparse Graph Neural Networks by Tensor-CUDA Kernel Fusion8
Towards High Performance QNNs via Distribution-Based CNOT Gate Reduction8
Multi-objective Hardware-aware Neural Architecture Search with Pareto Rank-preserving Surrogate Models8
PctoDL: Adaptive GPU Throughput Optimization for Deep Learning Inference with Power Constraints8
CML-PowF: Data Clustering Matching Based Low-overhead Multiple CPU Real-time Power Forecasting8
Efficient Cross-platform Multiplexing of Hardware Performance Counters via Adaptive Grouping8
Environmental Condition Aware Super-Resolution Acceleration Framework in Server-Client Hierarchies8
HEngine: A High Performance Optimization Framework on a GPU for Homomorphic Encryption8
A Decoupled Analytical Model for Tile Size Selection in Affine Programs8
HyGain: High-performance, Energy-efficient Hybrid Gain Cell-based Cache Hierarchy8
TPRepair: Tree-based Pipelined Repair in Clustered Storage Systems8
WSGraph: A Framework for Tackling Redundant and Irregular Data Access in Streaming Graph Processing8
Enabling Low-Latency, GPU-Efficient Serverless Inference with Model Swapping7
DTAP: Accelerating Strongly-Typed Programs with Data Type-Aware Hardware Prefetching7
Mobile-3DCNN: An Acceleration Framework for Ultra-Real-Time Execution of Large 3D CNNs on Mobile Devices7
PowerMorph: QoS-Aware Server Power Reshaping for Data Center Regulation Service7
PyramidFFT: Rearchitecting FFT with Matrix-Aligned Nested-Radix for Hierarchical Scratchpad Memory on AI Accelerators7
RACER: Avoiding End-to-End Slowdowns in Accelerated Chip Multi-Processors7
RaNAS: Resource-Aware Neural Architecture Search for Edge Computing7
A Stable Idle Time Detection Platform for Real I/O Workloads7
SimTrace: Exploiting Spatial and Temporal Sampling for Large-Scale Performance Analysis7
HiSo: Co-optimizing the Intra-layer and Inter-layer Scheduling Schemes with the Hybrid Data Flow for PIM Architectures6
Lightweight Code Outlining for Android Applications6
FlexHM: A Practical System for Heterogeneous Memory with Flexible and Efficient Performance Optimizations6
x Meta : SSD-HDD-hybrid Optimization for Metadata Maintenance of Cloud-scale Object Storage6
Enabling Efficient Vector Processing: A Heterogeneous Vector Architecture with in-SRAM Computing6
gECC: A GPU-based high-throughput framework for Elliptic Curve Cryptography6
Orchard: Heterogeneous Parallelism and Fine-grained Fusion for Complex Tree Traversals6
MemoriaNova: Optimizing Memory-Aware Model Inference for Edge Computing6
Stripe-schedule Aware Repair in Erasure-coded Clusters with Heterogeneous Star Networks6
BLR-Krylov: A Single-GPU Iterative SpMM Framework with Communication Avoidance and Block Low-Rank Optimization6
Accelerating the Simulation of Parallel Workloads using Loop-Bounded Checkpoints6
PaTGen: Temporal Similarity-Driven Proxy Benchmark Generation Method for Cloud Workloads6
MoonPoly : Bridging Code Generation and Adaptive Execution via Micro-Kernel Polymerization for Optimizing Dynamic-Shape Tensor Operators6
Towards Optimizing Learned Index for High Performance, Memory Efficiency and NUMA Awareness6
EDAS: Enabling Fast Data Loading for GPU Serverless Computing6
OptiFX: Automatic Optimization for Convolutional Neural Networks with Aggressive Operator Fusion on GPUs6
Exploring Data Layout for Sparse Tensor Times Dense Matrix on GPUs6
Performance Prediction of Concurrent DNN Training Tasks in GPU Spatial Sharing Environments6
Toward Comprehensive Design Space Exploration on Heterogeneous Multi-core Processors6
A Memory-Aware Sparse Matrix-Matrix Multiplication on Multicore Architectures6
Pac-PIM: A Parallel Communication Framework for Commodity Processing-in-memory Systems6
CGCGraph: Efficient CPU-GPU Co-execution for Concurrent Dynamic Graph Processing5
GraphTune: An Efficient Dependency-Aware Substrate to Alleviate Irregularity in Concurrent Graph Processing5
Improving Utilization of Dataflow Unit for Multi-Batch Processing5
RaKV: A Write-Optimized LSM Store for Cloud Block Storage with Robust SLA5
BullsEye : Scalable and Accurate Approximation Framework for Cache Miss Calculation5
Koala: Efficient Pipeline Training through Automated Schedule Searching on Domain-Specific Language5
LLMSGHD: Co-Designing Large Language Model Software and Hardware for Efficient Inference5
Accelerating Convolutional Neural Network by Exploiting Sparsity on GPUs5
JiuJITsu: Removing Gadgets with Safe Register Allocation for JIT Code Generation5
Capability-Based Efficient Data Transmission Mechanism for Serverless Computing5
Architecting Optically Controlled Phase Change Memory5
RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory5
WIPE: A Write-Optimized Learned Index for Persistent Memory5
Efficient and Scalable Hybrid Parallelization of Unstructured Computational Fluid Dynamics with Geometric Multigrid5
Shift-CIM: In-SRAM Alignment To Support General-Purpose Bit-level Sparsity Exploration in SRAM Multiplication5
MetaEC: An Efficient and Resilient Erasure-Coded KV Store on Disaggregated Memory5
CoolDC: A Cost-Effective Immersion-Cooled Datacenter with Workload-Aware Temperature Scaling5
Diamond Tiling for Periodic Stencil Loop Nests by Means of Transitive Closure-based Extraction of Overlapping Iteration Spaces4
Consequence-based Clustered Architecture4
Scale-out Systolic Arrays4
BLG-Tuning: Benchmark-Based Low-Cost General-Purpose I/O Modeling and Tuning4
Efficient Flexible Edge Inference for Mixed-Precision Quantized DNN using Customized RISC-V Core4
Fragment: Efficient DNN Checkpoint with Relaxed Model Consistency4
High Performance Singular Value Decomposition on GPU Architectures4
FlowPix: Accelerating Image Processing Pipelines on an FPGA Overlay using a Domain Specific Compiler4
CoNST: Code Generator for Sparse Tensor Networks4
3D GNLM: Efficient 3D Non-Local Means Kernel with Nested Reuse Strategies for Embedded GPUs4
An Example of Parallel Merkle Tree Traversal: Post-Quantum Leighton-Micali Signature on the GPU4
Tetrahedrangel: An Energy-Efficient Coalescing Temporal Prefetcher4
Architectural Support for Sharing, Isolating and Virtualizing FPGA Resources4
SplitZNS: Towards an Efficient LSM-Tree on Zoned Namespace SSDs4
TSN Cache: Exploiting Data Localities in Graph Computing Applications4
Abakus: Accelerating k -mer Counting with Storage Technology4
GNΩSIS: Lessons Learned in Generating a High-Level Synthesis Dataset4
HeapKV: Enabling Efficient Garbage Collection for KV-Separated LSM Stores on Modern SSDs4
MLIR Dialects for DAE-based Modeling Languages4
Matrix: Multi-Cipher Structures Dataflow for Parallel and Pipelined TFHE Accelerator4
Protocol and Software Co-optimization: Overcoming the PCIe Transfer Bottleneck in dGPU Accelerated In-kernel ML4
Address/Data Instruction Steering in Clustered General Purpose Processors4
Analytical Modeling of Set-Associative Caches for Optimizing Tensor Operations4
Rethinking Variable-Length Encoding: Exploiting Bit Sparsity for Parallel Decoding in LLM Accelerators4
Iterating Pointers: Enabling Static Analysis for Loop-based Pointers4
SAL: Optimizing the Dataflow of Spin-based Architectures for Lightweight Neural Networks4
MicroProf : Code-level Attribution of Unnecessary Data Transfer in Microservice Applications4
Optimizing OpenCL Barrier Synchronization and Memory Efficiency on Multi-Core DSPs4
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