OOIR: Observatory of International Research

Papers

(The TQCC of ACM Transactions on Architecture and Code Optimization is 4. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-11-01 to 2024-11-01.)

Article	Citations
SMAUG	39
IR2V EC	39
Domain-Specific Multi-Level IR Rewriting for GPU	25
A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures	25
Grus	23
PERI	21
SLO-Aware Inference Scheduler for Heterogeneous Processors in Edge Platforms	21
A Black-box Monitoring Approach to Measure Microservices Runtime Performance	20
Compiler Support for Sparse Tensor Computations in MLIR	20
LLOV	19
A Case For Intra-rack Resource Disaggregation in HPC	18
Configurable Multi-directional Systolic Array Architecture for Convolutional Neural Networks	18
Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications	18
PAVER	17
Marvel: A Data-Centric Approach for Mapping Deep Learning Operators on Spatial Accelerators	15
Efficient Auto-Tuning of Parallel Programs with Interdependent Tuning Parameters via Auto-Tuning Framework (ATF)	15
PolyDL	13
Low I/O Intensity-aware Partial GC Scheduling to Reduce Long-tail Latency in SSDs	13
Gem5-X	13
PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM	12
KernelFaRer	12
A Simple Model for Portable and Fast Prediction of Execution Time and Power Consumption of GPU Kernels	12
An Accelerator for Sparse Convolutional Neural Networks Leveraging Systolic General Matrix-matrix Multiplication	12
CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems	12
Architecting Optically Controlled Phase Change Memory	11

Exploiting Parallelism Opportunities with Deep Learning Frameworks	11
On the Anatomy of Predictive Models for Accelerating GPU Convolution Kernels and Beyond	10
Scale-out Systolic Arrays	10
Polyhedral Specification and Code Generation of Sparse Tensor Contraction with Co-iteration	9
Performance Evaluation of Intel Optane Memory for Managed Workloads	9
Low-precision Logarithmic Number Systems	9
GEVO	9
ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes	9
Autotuning Convolutions Is Easier Than You Think	9
GRAM	9
Register-Pressure-Aware Instruction Scheduling Using Ant Colony Optimization	8
ReuseTracker : Fast Yet Accurate Multicore Reuse Distance Analyzer	8
Understanding Cache Compression	8
Bayesian Optimization for Efficient Accelerator Synthesis	8
Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators	7
Optimizing Small-Sample Disk Fault Detection Based on LSTM-GAN Model	7
GraphPEG	7
A Reusable Characterization of the Memory System Behavior of SPEC2017 and SPEC2006	6
FastPath_MP	6
High-performance Deterministic Concurrency Using Lingua Franca	6
Performance and Power Prediction for Concurrent Execution on GPUs	6
HeapCheck: Low-cost Hardware Support for Memory Safety	6
LargeGraph	6
Task-RM: A Resource Manager for Energy Reduction in Task-Parallel Applications under Quality of Service Constraints	6
Spiking Neural Networks in Spintronic Computational RAM	5
E-BATCH: Energy-Efficient and High-Throughput RNN Batching	5
A Fast and Flexible FPGA-based Accelerator for Natural Language Processing Neural Networks	5
SplitZNS: Towards an Efficient LSM-Tree on Zoned Namespace SSDs	5
Refresh Triggered Computation	5
MemSZ	5
MemHC: An Optimized GPU Memory Management Framework for Accelerating Many-body Correlation	5
Multi-objective Hardware-aware Neural Architecture Search with Pareto Rank-preserving Surrogate Models	5
WaFFLe	5
Monolithically Integrating Non-Volatile Main Memory over the Last-Level Cache	5
Gretch	5
Energy-efficient In-Memory Address Calculation	5
Practical Software-Based Shadow Stacks on x86-64	5
MC-DeF	5
GraphAttack	5
GPU Domain Specialization via Composable On-Package Architecture	5
GiantVM: A Novel Distributed Hypervisor for Resource Aggregation with DSM-aware Optimizations	4
An FPGA Overlay for CNN Inference with Fine-grained Flexible Parallelism	4
ULEEN: A Novel Architecture for Ultra-low-energy Edge Neural Networks	4
Design and Evaluation of an Ultra Low-power Human-quality Speech Recognition System	4
YaConv: Convolution with Low Cache Footprint	4
SPX64	4
An FPGA-based Approach to Evaluate Thermal and Resource Management Strategies of Many-core Processors	4
Preserving Addressability Upon GC-Triggered Data Movements on Non-Volatile Memory	4
On Architectural Support for Instruction Set Randomization	4