ACM Transactions on Architecture and Code Optimization

Papers
(The TQCC of ACM Transactions on Architecture and Code Optimization is 3. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-05-01 to 2025-05-01.)
ArticleCitations
An Accelerator for Sparse Convolutional Neural Networks Leveraging Systolic General Matrix-matrix Multiplication37
Object Intersection Captures on Interactive Apps to Drive a Crowd-sourced Replay-based Compiler Optimization32
Spiking Neural Networks in Spintronic Computational RAM31
ASM: An Adaptive Secure Multicore for Co-located Mutually Distrusting Processes30
TNT: A Modular Approach to Traversing Physically Heterogeneous NOCs at Bare-wire Latency29
TransCL: An Automatic CUDA-to-OpenCL Programs Transformation Framework25
An Intelligent Scheduling Approach on Mobile OS for Optimizing UI Smoothness and Power23
Highly Efficient Self-checking Matrix Multiplication on Tiled AMX Accelerators18
ModNEF : An Open Source Modular Neuromorphic Emulator for FPGA for Low-Power In-Edge Artificial Intelligence17
DCMA: Accelerating Parallel DMA Transfers with a Multi-Port Direct Cached Memory Access in a Massive-Parallel Vector Processor16
Building a Fast and Efficient LSM-tree Store by Integrating Local Storage with Cloud Storage16
SIMD-Matcher: A SIMD-based Arbitrary Matching Framework15
Source Matching and Rewriting for MLIR Using String-Based Automata15
COER: A Network Interface Offloading Architecture for RDMA and Congestion Control Protocol Codesign14
Fast Convolution Meets Low Precision: Exploring Efficient Quantized Winograd Convolution on Modern CPUs14
Tiaozhuan: A General and Efficient Indirect Branch Optimization for Binary Translation14
A Concise Concurrent B + -Tree for Persistent Memory13
Locality-Aware CTA Scheduling for Gaming Applications13
Mentor: A Memory-Efficient Sparse-dense Matrix Multiplication Accelerator Based on Column-Wise Product12
DeepZoning: Re-accelerate CNN Inference with Zoning Graph for Heterogeneous Edge Cluster12
Accelerating Video Captioning on Heterogeneous System Architectures12
Domain-Specific Multi-Level IR Rewriting for GPU12
A NUMA-Aware Version of an Adaptive Self-Scheduling Loop Scheduler11
iSwap: A New Memory Page Swap Mechanism for Reducing Ineffective I/O Operations in Cloud Environments11
COX : Exposing CUDA Warp-level Functions to CPUs10
GraphSER: Distance-Aware Stream-Based Edge Repartition for Many-Core Systems10
Quantifying Resource Contention of Co-located Workloads with the System-level Entropy10
AG-SpTRSV: An Automatic Framework to Optimize Sparse Triangular Solve on GPUs10
Accelerating Nearest Neighbor Search in 3D Point Cloud Registration on GPUs9
ODGS: Dependency-Aware Scheduling for High-Level Synthesis with Graph Neural Network and Reinforcement Learning9
Flexible and Effective Object Tiering for Heterogeneous Memory Systems9
SnsBooster: Enhancing Sampling-Based \mu Arch Evaluation Efficiency through Online Performance Sensitivity Analysis8
Joint Program and Layout Transformations to Enable Convolutional Operators on Specialized Hardware Based on Constraint Programming8
An FPGA Overlay for CNN Inference with Fine-grained Flexible Parallelism8
EXPERTISE: An Effective Software-level Redundant Multithreading Scheme against Hardware Faults7
BridgeGC: An Efficient Cross-Level Garbage Collector for Big Data Frameworks7
Efficient Cross-platform Multiplexing of Hardware Performance Counters via Adaptive Grouping7
A Fast and Flexible FPGA-based Accelerator for Natural Language Processing Neural Networks6
Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture6
Advancing Direct Convolution Using Convolution Slicing Optimization and ISA Extensions6
NEM-GNN: DAC/ADC-less, Scalable, Reconfigurable, Graph and Sparsity-Aware Near-Memory Accelerator for Graph Neural Networks6
RT-GNN: Accelerating Sparse Graph Neural Networks by Tensor-CUDA Kernel Fusion6
Understanding Cache Compression6
TPRepair: Tree-based Pipelined Repair in Clustered Storage Systems6
HEngine: A High Performance Optimization Framework on a GPU for Homomorphic Encryption5
DTAP: Accelerating Strongly-Typed Programs with Data Type-Aware Hardware Prefetching5
Environmental Condition Aware Super-Resolution Acceleration Framework in Server-Client Hierarchies5
PowerMorph: QoS-Aware Server Power Reshaping for Data Center Regulation Service5
Orchard: Heterogeneous Parallelism and Fine-grained Fusion for Complex Tree Traversals5
Low-power Near-data Instruction Execution Leveraging Opcode-based Timing Analysis5
Towards High Performance QNNs via Distribution-Based CNOT Gate Reduction5
Low I/O Intensity-aware Partial GC Scheduling to Reduce Long-tail Latency in SSDs5
System-level Early-stage Modeling and Evaluation of IVR-assisted Processor Power Delivery System5
RaNAS: Resource-Aware Neural Architecture Search for Edge Computing5
HyGain: High-performance, Energy-efficient Hybrid Gain Cell-based Cache Hierarchy5
Multi-objective Hardware-aware Neural Architecture Search with Pareto Rank-preserving Surrogate Models5
Sniper: Exploiting Spatial and Temporal Sampling for Large-Scale Performance Analysis4
FlexHM: A Practical System for Heterogeneous Memory with Flexible and Efficient Performance Optimizations4
x Meta : SSD-HDD-hybrid Optimization for Metadata Maintenance of Cloud-scale Object Storage4
Accelerating Convolutional Neural Network by Exploiting Sparsity on GPUs4
ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes4
Byte-Select Compression4
MemoriaNova: Optimizing Memory-Aware Model Inference for Edge Computing4
Stripe-schedule Aware Repair in Erasure-coded Clusters with Heterogeneous Star Networks4
GraphTune: An Efficient Dependency-Aware Substrate to Alleviate Irregularity in Concurrent Graph Processing4
A Stable Idle Time Detection Platform for Real I/O Workloads4
Exploring Data Layout for Sparse Tensor Times Dense Matrix on GPUs4
Improving Utilization of Dataflow Unit for Multi-Batch Processing4
OptiFX: Automatic Optimization for Convolutional Neural Networks with Aggressive Operator Fusion on GPUs4
Automatic Sublining for Efficient Sparse Memory Accesses3
All-gather Algorithms Resilient to Imbalanced Process Arrival Patterns3
FlowPix: Accelerating Image Processing Pipelines on an FPGA Overlay using a Domain Specific Compiler3
SplitZNS: Towards an Efficient LSM-Tree on Zoned Namespace SSDs3
JiuJITsu: Removing Gadgets with Safe Register Allocation for JIT Code Generation3
BullsEye : Scalable and Accurate Approximation Framework for Cache Miss Calculation3
Shift-CIM: In-SRAM Alignment To Support General-Purpose Bit-level Sparsity Exploration in SRAM Multiplication3
Architecting Optically Controlled Phase Change Memory3
Preserving Addressability Upon GC-Triggered Data Movements on Non-Volatile Memory3
Abakus: Accelerating k -mer Counting with Storage Technology3
WIPE: A Write-Optimized Learned Index for Persistent Memory3
CoolDC: A Cost-Effective Immersion-Cooled Datacenter with Workload-Aware Temperature Scaling3
Architectural Support for Sharing, Isolating and Virtualizing FPGA Resources3
Scale-out Systolic Arrays3
MicroProf : Code-level Attribution of Unnecessary Data Transfer in Microservice Applications3
CoNST: Code Generator for Sparse Tensor Networks3
Koala: Efficient Pipeline Training through Automated Schedule Searching on Domain-Specific Language3
Monolithically Integrating Non-Volatile Main Memory over the Last-Level Cache3
CASHT: Contention Analysis in Shared Hierarchies with Thefts3
TSN Cache: Exploiting Data Localities in Graph Computing Applications3
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