ACM Transactions on Architecture and Code Optimization

Papers
(The TQCC of ACM Transactions on Architecture and Code Optimization is 3. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-06-01 to 2025-06-01.)
ArticleCitations
Object Intersection Captures on Interactive Apps to Drive a Crowd-sourced Replay-based Compiler Optimization37
Spiking Neural Networks in Spintronic Computational RAM32
TNT: A Modular Approach to Traversing Physically Heterogeneous NOCs at Bare-wire Latency32
ASM: An Adaptive Secure Multicore for Co-located Mutually Distrusting Processes32
TransCL: An Automatic CUDA-to-OpenCL Programs Transformation Framework29
An Intelligent Scheduling Approach on Mobile OS for Optimizing UI Smoothness and Power25
Highly Efficient Self-checking Matrix Multiplication on Tiled AMX Accelerators23
An Accelerator for Sparse Convolutional Neural Networks Leveraging Systolic General Matrix-matrix Multiplication18
Performance, Energy and NVM Lifetime-Aware Data Structure Refinement and Placement for Heterogeneous Memory Systems18
DCMA: Accelerating Parallel DMA Transfers with a Multi-Port Direct Cached Memory Access in a Massive-Parallel Vector Processor18
ModNEF : An Open Source Modular Neuromorphic Emulator for FPGA for Low-Power In-Edge Artificial Intelligence18
SIMD-Matcher: A SIMD-based Arbitrary Matching Framework17
A Concise Concurrent B + -Tree for Persistent Memory17
COER: A Network Interface Offloading Architecture for RDMA and Congestion Control Protocol Codesign16
Source Matching and Rewriting for MLIR Using String-Based Automata16
Tiaozhuan: A General and Efficient Indirect Branch Optimization for Binary Translation15
Building a Fast and Efficient LSM-tree Store by Integrating Local Storage with Cloud Storage14
Locality-Aware CTA Scheduling for Gaming Applications13
Fast Convolution Meets Low Precision: Exploring Efficient Quantized Winograd Convolution on Modern CPUs13
Accelerating Video Captioning on Heterogeneous System Architectures12
A NUMA-Aware Version of an Adaptive Self-Scheduling Loop Scheduler12
DeepZoning: Re-accelerate CNN Inference with Zoning Graph for Heterogeneous Edge Cluster12
Quantifying Resource Contention of Co-located Workloads with the System-level Entropy12
Mentor: A Memory-Efficient Sparse-dense Matrix Multiplication Accelerator Based on Column-Wise Product12
iSwap: A New Memory Page Swap Mechanism for Reducing Ineffective I/O Operations in Cloud Environments12
Domain-Specific Multi-Level IR Rewriting for GPU12
AG-SpTRSV: An Automatic Framework to Optimize Sparse Triangular Solve on GPUs10
COX : Exposing CUDA Warp-level Functions to CPUs10
GraphSER: Distance-Aware Stream-Based Edge Repartition for Many-Core Systems10
Flexible and Effective Object Tiering for Heterogeneous Memory Systems9
SnsBooster: Enhancing Sampling-Based \mu Arch Evaluation Efficiency through Online Performance Sensitivity Analysis8
An FPGA Overlay for CNN Inference with Fine-grained Flexible Parallelism8
ODGS: Dependency-Aware Scheduling for High-Level Synthesis with Graph Neural Network and Reinforcement Learning8
Accelerating Nearest Neighbor Search in 3D Point Cloud Registration on GPUs8
Efficient Cross-platform Multiplexing of Hardware Performance Counters via Adaptive Grouping7
Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture7
EXPERTISE: An Effective Software-level Redundant Multithreading Scheme against Hardware Faults7
NEM-GNN: DAC/ADC-less, Scalable, Reconfigurable, Graph and Sparsity-Aware Near-Memory Accelerator for Graph Neural Networks7
Joint Program and Layout Transformations to Enable Convolutional Operators on Specialized Hardware Based on Constraint Programming7
Understanding Cache Compression7
Advancing Direct Convolution Using Convolution Slicing Optimization and ISA Extensions6
A Fast and Flexible FPGA-based Accelerator for Natural Language Processing Neural Networks6
RaNAS: Resource-Aware Neural Architecture Search for Edge Computing6
BridgeGC: An Efficient Cross-Level Garbage Collector for Big Data Frameworks6
Low-power Near-data Instruction Execution Leveraging Opcode-based Timing Analysis6
HyGain: High-performance, Energy-efficient Hybrid Gain Cell-based Cache Hierarchy6
RT-GNN: Accelerating Sparse Graph Neural Networks by Tensor-CUDA Kernel Fusion6
TPRepair: Tree-based Pipelined Repair in Clustered Storage Systems6
Environmental Condition Aware Super-Resolution Acceleration Framework in Server-Client Hierarchies6
Multi-objective Hardware-aware Neural Architecture Search with Pareto Rank-preserving Surrogate Models5
Orchard: Heterogeneous Parallelism and Fine-grained Fusion for Complex Tree Traversals5
Sniper: Exploiting Spatial and Temporal Sampling for Large-Scale Performance Analysis5
Towards High Performance QNNs via Distribution-Based CNOT Gate Reduction5
PowerMorph: QoS-Aware Server Power Reshaping for Data Center Regulation Service5
DTAP: Accelerating Strongly-Typed Programs with Data Type-Aware Hardware Prefetching5
HEngine: A High Performance Optimization Framework on a GPU for Homomorphic Encryption5
System-level Early-stage Modeling and Evaluation of IVR-assisted Processor Power Delivery System5
Low I/O Intensity-aware Partial GC Scheduling to Reduce Long-tail Latency in SSDs5
A Stable Idle Time Detection Platform for Real I/O Workloads5
OptiFX: Automatic Optimization for Convolutional Neural Networks with Aggressive Operator Fusion on GPUs4
Exploring Data Layout for Sparse Tensor Times Dense Matrix on GPUs4
JiuJITsu: Removing Gadgets with Safe Register Allocation for JIT Code Generation4
GraphTune: An Efficient Dependency-Aware Substrate to Alleviate Irregularity in Concurrent Graph Processing4
gECC: A GPU-based high-throughput framework for Elliptic Curve Cryptography4
x Meta : SSD-HDD-hybrid Optimization for Metadata Maintenance of Cloud-scale Object Storage4
Improving Utilization of Dataflow Unit for Multi-Batch Processing4
WIPE: A Write-Optimized Learned Index for Persistent Memory4
CASHT: Contention Analysis in Shared Hierarchies with Thefts4
MemoriaNova: Optimizing Memory-Aware Model Inference for Edge Computing4
Byte-Select Compression4
Stripe-schedule Aware Repair in Erasure-coded Clusters with Heterogeneous Star Networks4
Accelerating Convolutional Neural Network by Exploiting Sparsity on GPUs4
Koala: Efficient Pipeline Training through Automated Schedule Searching on Domain-Specific Language4
BullsEye : Scalable and Accurate Approximation Framework for Cache Miss Calculation4
ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes4
FlexHM: A Practical System for Heterogeneous Memory with Flexible and Efficient Performance Optimizations4
All-gather Algorithms Resilient to Imbalanced Process Arrival Patterns3
SplitZNS: Towards an Efficient LSM-Tree on Zoned Namespace SSDs3
Abakus: Accelerating k -mer Counting with Storage Technology3
Towards Enhanced System Efficiency while Mitigating Row Hammer3
MicroProf : Code-level Attribution of Unnecessary Data Transfer in Microservice Applications3
Architecting Optically Controlled Phase Change Memory3
Shift-CIM: In-SRAM Alignment To Support General-Purpose Bit-level Sparsity Exploration in SRAM Multiplication3
Architectural Support for Sharing, Isolating and Virtualizing FPGA Resources3
Monolithically Integrating Non-Volatile Main Memory over the Last-Level Cache3
CoNST: Code Generator for Sparse Tensor Networks3
Consequence-based Clustered Architecture3
Scale-out Systolic Arrays3
TSN Cache: Exploiting Data Localities in Graph Computing Applications3
FlowPix: Accelerating Image Processing Pipelines on an FPGA Overlay using a Domain Specific Compiler3
CoolDC: A Cost-Effective Immersion-Cooled Datacenter with Workload-Aware Temperature Scaling3
TLB-pilot: Mitigating TLB Contention Attack on GPUs with Microarchitecture-Aware Scheduling3
Iterating Pointers: Enabling Static Analysis for Loop-based Pointers3
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