ACM Transactions on Architecture and Code Optimization

Article	Citations
Orchard: Heterogeneous Parallelism and Fine-grained Fusion for Complex Tree Traversals	25
The Droplet Search Algorithm for Kernel Scheduling	23
Decreasing the Miss Rate and Eliminating the Performance Penalty of a Data Filter Cache	23
Highly Efficient Self-checking Matrix Multiplication on Tiled AMX Accelerators	23
The Impact of Page Size and Microarchitecture on Instruction Address Translation Overhead	22
ASM: An Adaptive Secure Multicore for Co-located Mutually Distrusting Processes	21
SMT-Based Contention-Free Task Mapping and Scheduling on 2D/3D SMART NoC with Mixed Dimension-Order Routing	20
Mapi-Pro: An Energy Efficient Memory Mapping Technique for Intermittent Computing	18
Fastensor: Optimise the Tensor I/O Path from SSD to GPU for Deep Learning Training	18
Multiply-and-Fire: An Event-Driven Sparse Neural Network Accelerator	15
PETRA	13
Puppeteer: A Random Forest Based Manager for Hardware Prefetchers Across the Memory Hierarchy	13
Object Intersection Captures on Interactive Apps to Drive a Crowd-sourced Replay-based Compiler Optimization	13
MemoriaNova: Optimizing Memory-Aware Model Inference for Edge Computing	12
MUA-Router: Maximizing the Utility-of-Allocation for On-chip Pipelining Routers	12
An Intelligent Scheduling Approach on Mobile OS for Optimizing UI Smoothness and Power	12
The Forward Slice Core: A High-Performance, Yet Low-Complexity Microarchitecture	12
FlexPointer: Fast Address Translation Based on Range TLB and Tagged Pointers	11
ASA: A ccelerating S parse A ccumulation in Column-wise SpGEMM	10
ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes	10
Spiking Neural Networks in Spintronic Computational RAM	9
MasterPlan: A Reinforcement Learning Based Scheduler for Archive Storage	9
Performance Evaluation of Intel Optane Memory for Managed Workloads	9
An Application-oblivious Memory Scheduling System for DNN Accelerators	9
TNT: A Modular Approach to Traversing Physically Heterogeneous NOCs at Bare-wire Latency	8

An Accelerator for Sparse Convolutional Neural Networks Leveraging Systolic General Matrix-matrix Multiplication	8
D 2 Comp: Efficient Offload of LSM-tree Compaction with Data Processing Units on Disaggregated Storage	8
A Survey of General-purpose Polyhedral Compilers	7
XEngine: Optimal Tensor Rematerialization for Neural Networks in Heterogeneous Environments	7
MemHC: An Optimized GPU Memory Management Framework for Accelerating Many-body Correlation	7
Data Deduplication Based on Content Locality of Transactions to Enhance Blockchain Scalability	7
PIMSAB: A Processing-In-Memory System with Spatially-Aware Communication and Bit-Serial-Aware Computation	6
RACE: An Efficient Redundancy-aware Accelerator for Dynamic Graph Neural Network	6
An Optimized GPU Implementation for GIST Descriptor	6
A Stable Idle Time Detection Platform for Real I/O Workloads	6
Potamoi: Accelerating Neural Rendering via a Unified Streaming Architecture	6
GraphTune: An Efficient Dependency-Aware Substrate to Alleviate Irregularity in Concurrent Graph Processing	6
Improving Utilization of Dataflow Unit for Multi-Batch Processing	5
Accelerating Convolutional Neural Network by Exploiting Sparsity on GPUs	5
QuCloud+: A Holistic Qubit Mapping Scheme for Single/Multi-programming on 2D/3D NISQ Quantum Computers	5
Byte-Select Compression	5
WA-Zone: Wear-Aware Zone Management Optimization for LSM-Tree on ZNS SSDs	5
Exploring Data Layout for Sparse Tensor Times Dense Matrix on GPUs	5
KernelFaRer	5
GRAM	5
Source Matching and Rewriting for MLIR Using String-Based Automata	5
SSD-SGD: Communication Sparsification for Distributed Deep Learning Training	5
Fast Key-Value Lookups with Node Tracker	5
RegCPython: A Register-based Python Interpreter for Better Performance	5
Delay-on-Squash: Stopping Microarchitectural Replay Attacks in Their Tracks	5
TEA+ : A Novel Temporal Graph Random Walk Engine with Hybrid Storage Architecture	4
gHyPart: GPU-friendly End-to-End Hypergraph Partitioner	4
Energy-efficient In-Memory Address Calculation	4
KINDRED: Heterogeneous Split-Lock Architecture for Safe Autonomous Machines	4
Enhancing High-Throughput GPU Random Walks Through Multi-Task Concurrency Orchestration	4
x Meta : SSD-HDD-hybrid Optimization for Metadata Maintenance of Cloud-scale Object Storage	4
Fast Convolution Meets Low Precision: Exploring Efficient Quantized Winograd Convolution on Modern CPUs	4
Building a Fast and Efficient LSM-tree Store by Integrating Local Storage with Cloud Storage	3
ReuseTracker : Fast Yet Accurate Multicore Reuse Distance Analyzer	3
Hierarchical Model Parallelism for Optimizing Inference on Many-core Processor via Decoupled 3D-CNN Structure	3
Leveraging the Hardware Resources to Accelerate cryo-EM Reconstruction of RELION on the New Sunway Supercomputer	3
PARADISE: Criticality-Aware Instruction Reordering for Power Attack Resistance	3
CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems	3
A Concise Concurrent B + -Tree for Persistent Memory	3
SLAP: Segmented Reuse-Time-Label Based Admission Policy for Content Delivery Network Caching	3
LiteCON : An All-photonic Neuromorphic Accelerator for Energy-efficient Deep Learning	3
Tiaozhuan: A General and Efficient Indirect Branch Optimization for Binary Translation	3
SAC: An Ultra-Efficient Spin-based Architecture for Compressed DNNs	3
DAG-Order: An Order-Based Dynamic DAG Scheduling for Real-Time Networks-on-Chip	3
SpecTerminator: Blocking Speculative Side Channels Based on Instruction Classes on RISC-V	3
FlexHM: A Practical System for Heterogeneous Memory with Flexible and Efficient Performance Optimizations	3
SIMD-Matcher: A SIMD-based Arbitrary Matching Framework	3
Conflict Management in Vector Register Files	3
Optimization of Sparse Matrix Computation for Algebraic Multigrid on GPUs	3
PICO	2

Architecting Optically Controlled Phase Change Memory	2
Pac-Sim: Simulation of Multi-threaded Workloads using Intelligent, Live Sampling	2
Access Characteristic-Guided Remote Swapping Across Mobile Devices	2
AIS: An Active Idleness I/O Scheduler to Reduce Buffer-Exhausted Degradation of Solid-State Drives	2
ReSA: Reconfigurable Systolic Array for Multiple Tiny DNN Tensors	2
LO-SpMM: Low-cost Search for High-performance SpMM Kernels on GPUs	2
Phronesis: Efficient Performance Modeling for High-dimensional Configuration Tuning	2
Extension VM: Interleaved Data Layout in Vector Memory	2
SuccinctKV: a CPU-efficient LSM-tree Based KV Store with Scan-based Compaction	2
HAIR: Halving the Area of the Integer Register File with Odd/Even Banking	2
PMGraph: Accelerating Concurrent Graph Queries over Streaming Graphs	2
WIPE: A Write-Optimized Learned Index for Persistent Memory	2
DELTA: Memory-Efficient Training via Dynamic Fine-Grained Recomputation and Swapping	2
Stripe-schedule Aware Repair in Erasure-coded Clusters with Heterogeneous Star Networks	2
COER: A Network Interface Offloading Architecture for RDMA and Congestion Control Protocol Codesign	2
Bubble-Swap Flow Control	2
GPU Domain Specialization via Composable On-Package Architecture	2
Mentor: A Memory-Efficient Sparse-dense Matrix Multiplication Accelerator Based on Column-Wise Product	2
At the Locus of Performance: Quantifying the Effects of Copious 3D-Stacked Cache on HPC Workloads	2
Domain-Specific Multi-Level IR Rewriting for GPU	2
A 2 : Towards Accelerator Level Parallelism for Autonomous Micromobility Systems	2
PRAGA: A Priority-Aware Hardware/Software Co-design for High-Throughput Graph Processing Acceleration	2
Fixed-point Encoding and Architecture Exploration for Residue Number Systems	2
Characterizing and Optimizing LDPC Performance on 3D NAND Flash Memories	2
Achieving Tunable Erasure Coding with Cluster-Aware Redundancy Transitioning	2
exZNS: Extending Zoned Namespace to Support Byte-loggable Zones	2
Early Address Prediction	2
Understanding Silent Data Corruption in Processors for Mitigating its Effects	2
ShieldCXL: A Practical Obliviousness Support with Sealed CXL Memory	1
Automatic Sublining for Efficient Sparse Memory Accesses	1
Approx-RM: Reducing Energy on Heterogeneous Multicore Processors under Accuracy and Timing Constraints	1
ReIPE: Recycling Idle PEs in CNN Accelerator for Vulnerable Filters Soft-Error Detection	1
Smart-DNN+: A Memory-efficient Neural Networks Compression Framework for the Model Inference	1
JiuJITsu: Removing Gadgets with Safe Register Allocation for JIT Code Generation	1
Locality-Aware CTA Scheduling for Gaming Applications	1
MPU: Memory-centric SIMT Processor via In-DRAM Near-bank Computing	1
Lavender: An Efficient Resource Partitioning Framework for Large-Scale Job Colocation	1
Maximizing Data and Hardware Reuse for HLS with Early-Stage Symbolic Partitioning	1
A NUMA-Aware Version of an Adaptive Self-Scheduling Loop Scheduler	1
DLAS: A Conceptual Model for Across-Stack Deep Learning Acceleration	1
Towards Enhanced System Efficiency while Mitigating Row Hammer	1
ULEEN: A Novel Architecture for Ultra-low-energy Edge Neural Networks	1
Scale-out Systolic Arrays	1
DeepZoning: Re-accelerate CNN Inference with Zoning Graph for Heterogeneous Edge Cluster	1
Dedicated Hardware Accelerators for Processing of Sparse Matrices and Vectors: A Survey	1
Cerberus: Triple Mode Acceleration of Sparse Matrix and Vector Multiplication	1
Reducing Minor Page Fault Overheads through Enhanced Page Walker	1
Knowledge-Augmented Mutation-Based Bug Localization for Hardware Design Code	1
SplitZNS: Towards an Efficient LSM-Tree on Zoned Namespace SSDs	1
Compiler Support for Sparse Tensor Computations in MLIR	1
CASHT: Contention Analysis in Shared Hierarchies with Thefts	1
An Efficient ReRAM-based Accelerator for Asynchronous Iterative Graph Processing	1
GraphSER: Distance-Aware Stream-Based Edge Repartition for Many-Core Systems	1
Taming Flexible Job Packing in Deep Learning Training Clusters	1
LargeGraph	1
Gretch	1
iSwap: A New Memory Page Swap Mechanism for Reducing Ineffective I/O Operations in Cloud Environments	1
GraphAttack	1
SPIRIT: Scalable and Persistent In-Memory Indices for Real-Time Search	1
Architectural Support for Sharing, Isolating and Virtualizing FPGA Resources	1
CoolDC: A Cost-Effective Immersion-Cooled Datacenter with Workload-Aware Temperature Scaling	1
Task-RM: A Resource Manager for Energy Reduction in Task-Parallel Applications under Quality of Service Constraints	1
BullsEye : Scalable and Accurate Approximation Framework for Cache Miss Calculation	1
ATP: Achieving Throughput Peak for DNN Training via Smart GPU Memory Management	1
Accelerating Video Captioning on Heterogeneous System Architectures	1
An Optimized Framework for Matrix Factorization on the New Sunway Many-core Platform	1
Online Application Guidance for Heterogeneous Memory Systems	1
Monolithically Integrating Non-Volatile Main Memory over the Last-Level Cache	1
Just-In-Time Compilation on ARM—A Closer Look at Call-Site Code Consistency	1
MST: Topology-Aware Message Aggregation for Exascale Graph Processing of Traversal-Centric Algorithms	1
Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications	1
Performance and Power Prediction for Concurrent Execution on GPUs	1
Intermediate Address Space: virtual memory optimization of heterogeneous architectures for cache-resident workloads	1
QoS-pro: A QoS-enhanced Transaction Processing Framework for Shared SSDs	1
High-performance Deterministic Concurrency Using Lingua Franca	0
Agile C-states: A Core C-state Architecture for Latency Critical Applications Optimizing both Transition and Cold-Start Latency	0
Critical Data Backup with Hybrid Flash-Based Consumer Devices	0
Configurable Multi-directional Systolic Array Architecture for Convolutional Neural Networks	0
PARALiA: A Performance Aware Runtime for Auto-tuning Linear Algebra on Heterogeneous Systems	0
GiantVM: A Novel Distributed Hypervisor for Resource Aggregation with DSM-aware Optimizations	0

PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM	0
A Fast and Flexible FPGA-based Accelerator for Natural Language Processing Neural Networks	0
HyGain: High-performance, Energy-efficient Hybrid Gain Cell-based Cache Hierarchy	0
Symbolic Analysis for Data Plane Programs Specialization	0
Using Barrier Elision to Improve Transactional Code Generation	0
Device Hopping	0
HeapCheck: Low-cost Hardware Support for Memory Safety	0
SAL: Optimizing the Dataflow of Spin-based Architectures for Lightweight Neural Networks	0
All-gather Algorithms Resilient to Imbalanced Process Arrival Patterns	0
A Reusable Characterization of the Memory System Behavior of SPEC2017 and SPEC2006	0
FASA-DRAM: Reducing DRAM Latency with Destructive Activation and Delayed Restoration	0
Cost-aware Service Placement and Scheduling in the Edge-Cloud Continuum	0
RaNAS: Resource-Aware Neural Architecture Search for Edge Computing	0
Steered Bubble: An Interposer-based Deadlock Recovery Algorithm for Multi-chiplet Systems	0
Occam: Optimal Data Reuse for Convolutional Neural Networks	0
ApSpGEMM: Accelerating Large-scale SpGEMM with Heterogeneous Collaboration and Adaptive Panel	0
Towards High Performance QNNs via Distribution-Based CNOT Gate Reduction	0
SecNVM: An Efficient and Write-Friendly Metadata Crash Consistency Scheme for Secure NVM	0
IBing: An Efficient Interleaved Bidirectional Ring All-Reduce Algorithm for Gradient Synchronization	0
A Case For Intra-rack Resource Disaggregation in HPC	0
On Predictable Reconfigurable System Design	0
Cross-core Data Sharing for Energy-efficient GPUs	0
Cooperative Slack Management: Saving Energy of Multicore Processors by Trading Performance Slack Between QoS-Constrained Applications	0
MicroProf : Code-level Attribution of Unnecessary Data Transfer in Microservice Applications	0
Optimizing Garbage Collection for ZNS SSDs via In-storage Data Migration and Address Remapping	0
Weaving Synchronous Reactions into the Fabric of SSA-form Compilers	0
Improving Computation and Memory Efficiency for Real-world Transformer Inference on GPUs	0
GraphService: Topology-aware Constructor for Large-scale Graph Applications	0
GraphPEG	0
Environmental Condition Aware Super-Resolution Acceleration Framework in Server-Client Hierarchies	0
User-driven Online Kernel Fusion for SYCL	0
Multiple Function Merging for Code Size Reduction	0
Design and Implementation for Nonblocking Execution in GraphBLAS: Tradeoffs and Performance	0
Multi-objective Hardware-aware Neural Architecture Search with Pareto Rank-preserving Surrogate Models	0
TLB-pilot: Mitigating TLB Contention Attack on GPUs with Microarchitecture-Aware Scheduling	0
Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators	0
EA4RCA: Efficient AIE accelerator design framework for regular Communication-Avoiding Algorithm	0
Unveiling and Evaluating Vulnerabilities in Branch Predictors via a Three-Step Modeling Methodology	0
Consequence-based Clustered Architecture	0
CIB-HIER	0
PRISM	0
Hyperion: A Highly Effective Page and PC Based Delta Prefetcher	0
An FPGA Overlay for CNN Inference with Fine-grained Flexible Parallelism	0
Camouflage: Utility-Aware Obfuscation for Accurate Simulation of Sensitive Program Traces	0
TPRepair: Tree-Based Pipelined Repair in Clustered Storage Systems	0
COWS for High Performance: Cost Aware Work Stealing for Irregular Parallel Loop	0
RT-GNN: Accelerating Sparse Graph Neural Networks by Tensor-CUDA Kernel Fusion	0
MAPPER: Managing Application Performance via Parallel Efficiency Regulation	0
Cache Programming for Scientific Loops Using Leases	0
ApHMM: Accelerating Profile Hidden Markov Models for Fast and Energy-efficient Genome Analysis	0
A Data-Loader Tunable Knob to Shorten GPU Idleness for Distributed Deep Learning	0
YaConv: Convolution with Low Cache Footprint	0
PERI	0
An Instruction Inflation Analyzing Framework for Dynamic Binary Translators	0
DTAP: Accelerating Strongly-Typed Programs with Data Type-Aware Hardware Prefetching	0
Time-Aware Spectrum-Based Bug Localization for Hardware Design Code with Data Purification	0
Fine-grain Quantitative Analysis of Demand Paging in Unified Virtual Memory	0
Tyche: An Efficient and General Prefetcher for Indirect Memory Accesses	0
Low-power Near-data Instruction Execution Leveraging Opcode-based Timing Analysis	0
Grus	0
Shining Light on the Inter-procedural Code Obfuscation: Keep Pace with Progress in Binary Diffing	0
PowerMorph: QoS-Aware Server Power Reshaping for Data Center Regulation Service	0
Asynchronous Memory Access Unit: Exploiting Massive Parallelism for Far Memory Access	0
Characterizing Multi-Chip GPU Data Sharing	0
MetaSys: A Practical Open-source Metadata Management System to Implement and Evaluate Cross-layer Optimizations	0
Marvel: A Data-Centric Approach for Mapping Deep Learning Operators on Spatial Accelerators	0
Constructing a Supplementary Benchmark Suite to Represent Android Applications with User Interactions by using Performance Counters	0
E-BATCH: Energy-Efficient and High-Throughput RNN Batching	0
Dependence-aware Slice Execution to Boost MLP in Slice-out-of-order Cores	0
An Example of Parallel Merkle Tree Traversal: Post-Quantum Leighton-Micali Signature on the GPU	0
Acceleration of Parallel-Blocked QR Decomposition of Tall-and-Skinny Matrices on FPGAs	0
System-level Early-stage Modeling and Evaluation of IVR-assisted Processor Power Delivery System	0
GCNTrain+: A Versatile and Efficient Accelerator for Graph Convolutional Neural Network Training	0
A Non-Intrusive Tool Chain to Optimize MPSoC End-to-End Systems	0
Turn-based Spatiotemporal Coherence for GPUs	0
Low-precision Logarithmic Number Systems	0
Optimization of Large-Scale Sparse Matrix-Vector Multiplication on Multi-GPU Systems	0
FASA-DRAM: Reducing DRAM Latency with Destructive Activation and Delayed Restoration	0
COVER: Alleviating Crash-Consistency Error Amplification in Secure Persistent Memory Systems	0
LIA: Latency-Improved Adaptive routing for Dragonfly networks	0
COX : Exposing CUDA Warp-level Functions to CPUs	0
Low I/O Intensity-aware Partial GC Scheduling to Reduce Long-tail Latency in SSDs	0
Scenario-Aware Program Specialization for Timing Predictability	0
Rcmp: Reconstructing RDMA-Based Memory Disaggregation via CXL	0
A High Scalability Memory NoC with Shared-Inside Hierarchical-Groupings for Triplet-Based Many-Core Architecture	0
Understanding Cache Compression	0
CacheInspector	0
Register-Pressure-Aware Instruction Scheduling Using Ant Colony Optimization	0
Preserving Addressability Upon GC-Triggered Data Movements on Non-Volatile Memory	0
Characterizing and Understanding HGNN Training on GPUs	0
A Pressure-Aware Policy for Contention Minimization on Multicore Systems	0
FlowPix: Accelerating Image Processing Pipelines on an FPGA Overlay using a Domain Specific Compiler	0
Polyhedral Specification and Code Generation of Sparse Tensor Contraction with Co-iteration	0
CARL: Compiler Assigned Reference Leasing	0
Iterative Compilation Optimization Based on Metric Learning and Collaborative Filtering	0