ACM Transactions on Architecture and Code Optimization

Article	Citations
SMAUG	39
IR2V EC	39
Domain-Specific Multi-Level IR Rewriting for GPU	25
A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures	25
Grus	23
PERI	21
SLO-Aware Inference Scheduler for Heterogeneous Processors in Edge Platforms	21
A Black-box Monitoring Approach to Measure Microservices Runtime Performance	20
Compiler Support for Sparse Tensor Computations in MLIR	20
LLOV	19
A Case For Intra-rack Resource Disaggregation in HPC	18
Configurable Multi-directional Systolic Array Architecture for Convolutional Neural Networks	18
Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications	18
PAVER	17
Marvel: A Data-Centric Approach for Mapping Deep Learning Operators on Spatial Accelerators	15
Efficient Auto-Tuning of Parallel Programs with Interdependent Tuning Parameters via Auto-Tuning Framework (ATF)	15
PolyDL	13
Low I/O Intensity-aware Partial GC Scheduling to Reduce Long-tail Latency in SSDs	13
Gem5-X	13
CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems	12
PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM	12
KernelFaRer	12
A Simple Model for Portable and Fast Prediction of Execution Time and Power Consumption of GPU Kernels	12
An Accelerator for Sparse Convolutional Neural Networks Leveraging Systolic General Matrix-matrix Multiplication	12
Exploiting Parallelism Opportunities with Deep Learning Frameworks	11

Architecting Optically Controlled Phase Change Memory	11
Scale-out Systolic Arrays	10
On the Anatomy of Predictive Models for Accelerating GPU Convolution Kernels and Beyond	10
GRAM	9
Polyhedral Specification and Code Generation of Sparse Tensor Contraction with Co-iteration	9
Performance Evaluation of Intel Optane Memory for Managed Workloads	9
Low-precision Logarithmic Number Systems	9
GEVO	9
ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes	9
Autotuning Convolutions Is Easier Than You Think	9
Register-Pressure-Aware Instruction Scheduling Using Ant Colony Optimization	8
ReuseTracker : Fast Yet Accurate Multicore Reuse Distance Analyzer	8
Understanding Cache Compression	8
Bayesian Optimization for Efficient Accelerator Synthesis	8
Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators	7
Optimizing Small-Sample Disk Fault Detection Based on LSTM-GAN Model	7
GraphPEG	7
A Reusable Characterization of the Memory System Behavior of SPEC2017 and SPEC2006	6
FastPath_MP	6
High-performance Deterministic Concurrency Using Lingua Franca	6
Performance and Power Prediction for Concurrent Execution on GPUs	6
HeapCheck: Low-cost Hardware Support for Memory Safety	6
LargeGraph	6
Task-RM: A Resource Manager for Energy Reduction in Task-Parallel Applications under Quality of Service Constraints	6
Practical Software-Based Shadow Stacks on x86-64	5
MC-DeF	5
GraphAttack	5
GPU Domain Specialization via Composable On-Package Architecture	5
Spiking Neural Networks in Spintronic Computational RAM	5
E-BATCH: Energy-Efficient and High-Throughput RNN Batching	5
A Fast and Flexible FPGA-based Accelerator for Natural Language Processing Neural Networks	5
SplitZNS: Towards an Efficient LSM-Tree on Zoned Namespace SSDs	5
Refresh Triggered Computation	5
MemSZ	5
MemHC: An Optimized GPU Memory Management Framework for Accelerating Many-body Correlation	5
Multi-objective Hardware-aware Neural Architecture Search with Pareto Rank-preserving Surrogate Models	5
WaFFLe	5
Monolithically Integrating Non-Volatile Main Memory over the Last-Level Cache	5
Gretch	5
Energy-efficient In-Memory Address Calculation	5
GiantVM: A Novel Distributed Hypervisor for Resource Aggregation with DSM-aware Optimizations	4
An FPGA Overlay for CNN Inference with Fine-grained Flexible Parallelism	4
ULEEN: A Novel Architecture for Ultra-low-energy Edge Neural Networks	4
Design and Evaluation of an Ultra Low-power Human-quality Speech Recognition System	4
YaConv: Convolution with Low Cache Footprint	4
SPX64	4
An FPGA-based Approach to Evaluate Thermal and Resource Management Strategies of Many-core Processors	4
Preserving Addressability Upon GC-Triggered Data Movements on Non-Volatile Memory	4
On Architectural Support for Instruction Set Randomization	4
Irregular Register Allocation for Translation of Test-pattern Programs	3

Just-In-Time Compilation on ARM—A Closer Look at Call-Site Code Consistency	3
PowerMorph: QoS-Aware Server Power Reshaping for Data Center Regulation Service	3
Early Address Prediction	3
Accelerating Convolutional Neural Network by Exploiting Sparsity on GPUs	3
Solving Sparse Assignment Problems on FPGAs	3
SecNVM: An Efficient and Write-Friendly Metadata Crash Consistency Scheme for Secure NVM	3
Automatic Sublining for Efficient Sparse Memory Accesses	3
Efficient Nearest-Neighbor Data Sharing in GPUs	3
At the Locus of Performance: Quantifying the Effects of Copious 3D-Stacked Cache on HPC Workloads	3
WA-Zone: Wear-Aware Zone Management Optimization for LSM-Tree on ZNS SSDs	3
COX : Exposing CUDA Warp-level Functions to CPUs	3
On Predictable Reconfigurable System Design	3
A Pressure-Aware Policy for Contention Minimization on Multicore Systems	3
CASHT: Contention Analysis in Shared Hierarchies with Thefts	3
SortCache	3
Systems-on-Chip with Strong Ordering	3
ASA: A ccelerating S parse A ccumulation in Column-wise SpGEMM	3
Locality-Aware CTA Scheduling for Gaming Applications	2
DAG-Order: An Order-Based Dynamic DAG Scheduling for Real-Time Networks-on-Chip	2
SpecTerminator: Blocking Speculative Side Channels Based on Instruction Classes on RISC-V	2
NNBench-X	2
MFFT: A GPU Accelerated Highly Efficient Mixed-Precision Large-Scale FFT Framework	2
PRISM	2
An Efficient Hybrid Deep Learning Accelerator for Compact and Heterogeneous CNNs	2
Lock-Free High-performance Hashing for Persistent Memory via PM-aware Holistic Optimization	2
gPPM: A Generalized Matrix Operation and Parallel Algorithm to Accelerate the Encoding/Decoding Process of Erasure Codes	2
Cryptographic Software IP Protection without Compromising Performance or Timing Side-channel Leakage	2
Dedicated Hardware Accelerators for Processing of Sparse Matrices and Vectors: A Survey	2
PICO	2
FlexHM: A Practical System for Heterogeneous Memory with Flexible and Efficient Performance Optimizations	2
RegCPython: A Register-based Python Interpreter for Better Performance	2
Puppeteer: A Random Forest Based Manager for Hardware Prefetchers Across the Memory Hierarchy	2
User-driven Online Kernel Fusion for SYCL	2
Scenario-Aware Program Specialization for Timing Predictability	2
Triangle Dropping: An Occluded-geometry Predictor for Energy-efficient Mobile GPUs	2
Leveraging Value Equality Prediction for Value Speculation	2
TokenSmart: Distributed, Scalable Power Management in the Many-core Era	2
TLB-pilot: Mitigating TLB Contention Attack on GPUs with Microarchitecture-Aware Scheduling	2
Reducing Minor Page Fault Overheads through Enhanced Page Walker	2
SAC: An Ultra-Efficient Spin-based Architecture for Compressed DNNs	2
LiteCON : An All-photonic Neuromorphic Accelerator for Energy-efficient Deep Learning	2
Source Matching and Rewriting for MLIR Using String-Based Automata	2
Iterative Compilation Optimization Based on Metric Learning and Collaborative Filtering	2
MetaSys: A Practical Open-source Metadata Management System to Implement and Evaluate Cross-layer Optimizations	2
Cost-aware Service Placement and Scheduling in the Edge-Cloud Continuum	2
Advancing Direct Convolution Using Convolution Slicing Optimization and ISA Extensions	2
Memory-Aware Functional IR for Higher-Level Synthesis of Accelerators	2
Assessing the Impact of Compiler Optimizations on GPUs Reliability	2
A Distributed Hardware Monitoring System for Runtime Verification on Multi-Tile MPSoCs	2
Asynchronous Memory Access Unit: Exploiting Massive Parallelism for Far Memory Access	1
QuCloud+: A Holistic Qubit Mapping Scheme for Single/Multi-programming on 2D/3D NISQ Quantum Computers	1
CARL: Compiler Assigned Reference Leasing	1
XEngine: Optimal Tensor Rematerialization for Neural Networks in Heterogeneous Environments	1
ISP Agent: A Generalized In-storage-processing Workload Offloading Framework by Providing Multiple Optimization Opportunities	1
SG XL	1
Autovesk: Automatic Vectorized Code Generation from Unstructured Static Kernels Using Graph Transformations	1
The Impact of Page Size and Microarchitecture on Instruction Address Translation Overhead	1
Cache Programming for Scientific Loops Using Leases	1
Reliability-aware Garbage Collection for Hybrid HBM-DRAM Memories	1
Improving Computation and Memory Efficiency for Real-world Transformer Inference on GPUs	1
Architectural Support for Sharing, Isolating and Virtualizing FPGA Resources	1
Low-power Near-data Instruction Execution Leveraging Opcode-based Timing Analysis	1
Accelerating Video Captioning on Heterogeneous System Architectures	1
MAPPER: Managing Application Performance via Parallel Efficiency Regulation	1
SIMD-Matcher: A SIMD-based Arbitrary Matching Framework	1
Acceleration of Parallel-Blocked QR Decomposition of Tall-and-Skinny Matrices on FPGAs	1
Building a Fast and Efficient LSM-tree Store by Integrating Local Storage with Cloud Storage	1
Hardware-hardened Sandbox Enclaves for Trusted Serverless Computing	1
Delay-on-Squash: Stopping Microarchitectural Replay Attacks in Their Tracks	1
rNdN: Fast Query Compilation for NVIDIA GPUs	1
TNT: A Modular Approach to Traversing Physically Heterogeneous NOCs at Bare-wire Latency	1
Fast One-Sided RDMA-Based State Machine Replication for Disaggregated Memory	1
PETRA	1
DxPU: Large-scale Disaggregated GPU Pools in the Datacenter	1
Highly Efficient Self-checking Matrix Multiplication on Tiled AMX Accelerators	1
ACTION: Adaptive Cache Block Migration in Distributed Cache Architectures	1
Winols: A Large-Tiling Sparse Winograd CNN Accelerator on FPGAs	1
Towards Enhanced System Efficiency while Mitigating Row Hammer	1
QoS-pro: A QoS-enhanced Transaction Processing Framework for Shared SSDs	1
Performance-Energy Trade-off in Modern CMPs	1

Online Application Guidance for Heterogeneous Memory Systems	1
FASA-DRAM: Reducing DRAM Latency with Destructive Activation and Delayed Restoration	1
Hierarchical Model Parallelism for Optimizing Inference on Many-core Processor via Decoupled 3D-CNN Structure	1
CIB-HIER	1
SLAP: Segmented Reuse-Time-Label Based Admission Policy for Content Delivery Network Caching	1
COWS for High Performance: Cost Aware Work Stealing for Irregular Parallel Loop	1
RACE: An Efficient Redundancy-aware Accelerator for Dynamic Graph Neural Network	1
EXPERTISE: An Effective Software-level Redundant Multithreading Scheme against Hardware Faults	1
An Application-oblivious Memory Scheduling System for DNN Accelerators	1
Rcmp: Reconstructing RDMA-Based Memory Disaggregation via CXL	1
SMT-Based Contention-Free Task Mapping and Scheduling on 2D/3D SMART NoC with Mixed Dimension-Order Routing	1
Occam: Optimal Data Reuse for Convolutional Neural Networks	1
Cooperative Slack Management: Saving Energy of Multicore Processors by Trading Performance Slack Between QoS-Constrained Applications	1
Abakus: Accelerating k -mer Counting with Storage Technology	1
Cerberus: Triple Mode Acceleration of Sparse Matrix and Vector Multiplication	1
ApHMM: Accelerating Profile Hidden Markov Models for Fast and Energy-efficient Genome Analysis	1
BullsEye : Scalable and Accurate Approximation Framework for Cache Miss Calculation	1
Design and Implementation for Nonblocking Execution in GraphBLAS: Tradeoffs and Performance	1
WIPE: A Write-Optimized Learned Index for Persistent Memory	1
Weaving Synchronous Reactions into the Fabric of SSA-form Compilers	1
A Concise Concurrent B + -Tree for Persistent Memory	1