ACM Transactions on Architecture and Code Optimization

Article	Citations
SMAUG	36
IR2V EC	35
Domain-Specific Multi-Level IR Rewriting for GPU	25
A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures	23
Grus	21
PERI	19
A Black-box Monitoring Approach to Measure Microservices Runtime Performance	19
Compiler Support for Sparse Tensor Computations in MLIR	19
LLOV	18
PAVER	17
SLO-Aware Inference Scheduler for Heterogeneous Processors in Edge Platforms	17
A Case For Intra-rack Resource Disaggregation in HPC	16
Configurable Multi-directional Systolic Array Architecture for Convolutional Neural Networks	14
Efficient Auto-Tuning of Parallel Programs with Interdependent Tuning Parameters via Auto-Tuning Framework (ATF)	13
Inter-kernel Reuse-aware Thread Block Scheduling	13
Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications	12
KernelFaRer	12
Marvel: A Data-Centric Approach for Mapping Deep Learning Operators on Spatial Accelerators	12
Securing Branch Predictors with Two-Level Encryption	11
A Simple Model for Portable and Fast Prediction of Execution Time and Power Consumption of GPU Kernels	11
OD-SGD	10
AsynGraph	10
PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM	10
Exploiting Parallelism Opportunities with Deep Learning Frameworks	10
Low I/O Intensity-aware Partial GC Scheduling to Reduce Long-tail Latency in SSDs	10

EchoBay	10
On the Anatomy of Predictive Models for Accelerating GPU Convolution Kernels and Beyond	10
An Accelerator for Sparse Convolutional Neural Networks Leveraging Systolic General Matrix-matrix Multiplication	10
PolyDL	10
Gem5-X	10
Low-precision Logarithmic Number Systems	9
GRAM	9
GEVO	9
CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems	9
Bayesian Optimization for Efficient Accelerator Synthesis	8
GPU Fast Convolution via the Overlap-and-Save Method in Shared Memory	8
Schedule Synthesis for Halide Pipelines on GPUs	8
ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes	8
Architecting Optically Controlled Phase Change Memory	8
Performance Evaluation of Intel Optane Memory for Managed Workloads	8
Register-Pressure-Aware Instruction Scheduling Using Ant Colony Optimization	7
Polyhedral Specification and Code Generation of Sparse Tensor Contraction with Co-iteration	7
Autotuning Convolutions Is Easier Than You Think	7
A Reusable Characterization of the Memory System Behavior of SPEC2017 and SPEC2006	6
Scale-out Systolic Arrays	6
Understanding Cache Compression	6
Task-RM: A Resource Manager for Energy Reduction in Task-Parallel Applications under Quality of Service Constraints	6
Optimizing Small-Sample Disk Fault Detection Based on LSTM-GAN Model	6
ReuseTracker : Fast Yet Accurate Multicore Reuse Distance Analyzer	6
Effective Loop Fusion in Polyhedral Compilation Using Fusion Conflict Graphs	5
Energy-efficient In-Memory Address Calculation	5
Practical Software-Based Shadow Stacks on x86-64	5
Gretch	5
Refresh Triggered Computation	5
MemSZ	5
E-BATCH: Energy-Efficient and High-Throughput RNN Batching	5
GraphPEG	5
FastPath_MP	5
LargeGraph	5
Cooperative Software-hardware Acceleration of K-means on a Tightly Coupled CPU-FPGA System	5
HeapCheck: Low-cost Hardware Support for Memory Safety	5
MC-DeF	5
High-performance Deterministic Concurrency Using Lingua Franca	4
An FPGA-based Approach to Evaluate Thermal and Resource Management Strategies of Many-core Processors	4
Monolithically Integrating Non-Volatile Main Memory over the Last-Level Cache	4
GraphAttack	4
On Architectural Support for Instruction Set Randomization	4
A Fast and Flexible FPGA-based Accelerator for Natural Language Processing Neural Networks	4
Zeroploit	4
Performance and Power Prediction for Concurrent Execution on GPUs	4
SPX64	4
Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators	4
Preserving Addressability Upon GC-Triggered Data Movements on Non-Volatile Memory	4
GPU Domain Specialization via Composable On-Package Architecture	4
MemHC: An Optimized GPU Memory Management Framework for Accelerating Many-body Correlation	4

Just-In-Time Compilation on ARM—A Closer Look at Call-Site Code Consistency	3
SecNVM: An Efficient and Write-Friendly Metadata Crash Consistency Scheme for Secure NVM	3
Automatic Sublining for Efficient Sparse Memory Accesses	3
Accelerating Convolutional Neural Network by Exploiting Sparsity on GPUs	3
PowerMorph: QoS-Aware Server Power Reshaping for Data Center Regulation Service	3
Irregular Register Allocation for Translation of Test-pattern Programs	3
YaConv: Convolution with Low Cache Footprint	3
Early Address Prediction	3
Systems-on-Chip with Strong Ordering	3
A Pressure-Aware Policy for Contention Minimization on Multicore Systems	3
Solving Sparse Assignment Problems on FPGAs	3
On Predictable Reconfigurable System Design	3
WaFFLe	3
CASHT: Contention Analysis in Shared Hierarchies with Thefts	3
Spiking Neural Networks in Spintronic Computational RAM	3
Multi-objective Hardware-aware Neural Architecture Search with Pareto Rank-preserving Surrogate Models	3
Memory-Aware Functional IR for Higher-Level Synthesis of Accelerators	2
SortCache	2
Rcmp: Reconstructing RDMA-Based Memory Disaggregation via CXL	2
Reducing Minor Page Fault Overheads through Enhanced Page Walker	2
PICO	2
SpecTerminator: Blocking Speculative Side Channels Based on Instruction Classes on RISC-V	2
RegCPython: A Register-based Python Interpreter for Better Performance	2
ASA: A ccelerating S parse A ccumulation in Column-wise SpGEMM	2
Iterative Compilation Optimization Based on Metric Learning and Collaborative Filtering	2
MetaSys: A Practical Open-source Metadata Management System to Implement and Evaluate Cross-layer Optimizations	2
Triangle Dropping: An Occluded-geometry Predictor for Energy-efficient Mobile GPUs	2
Lock-Free High-performance Hashing for Persistent Memory via PM-aware Holistic Optimization	2
Design and Evaluation of an Ultra Low-power Human-quality Speech Recognition System	2
An FPGA Overlay for CNN Inference with Fine-grained Flexible Parallelism	2
SplitZNS: Towards an Efficient LSM-Tree on Zoned Namespace SSDs	2
Locality-Aware CTA Scheduling for Gaming Applications	2
FlexHM: A Practical System for Heterogeneous Memory with Flexible and Efficient Performance Optimizations	2
NNBench-X	2
Scenario-Aware Program Specialization for Timing Predictability	2
User-driven Online Kernel Fusion for SYCL	2
DisGCo	2
Leveraging Value Equality Prediction for Value Speculation	2
Cryptographic Software IP Protection without Compromising Performance or Timing Side-channel Leakage	2
COX : Exposing CUDA Warp-level Functions to CPUs	2
A Distributed Hardware Monitoring System for Runtime Verification on Multi-Tile MPSoCs	2
ECO TLB	2
Source Matching and Rewriting for MLIR Using String-Based Automata	2
Puppeteer: A Random Forest Based Manager for Hardware Prefetchers Across the Memory Hierarchy	2
GiantVM: A Novel Distributed Hypervisor for Resource Aggregation with DSM-aware Optimizations	2
Low-power Near-data Instruction Execution Leveraging Opcode-based Timing Analysis	2
TokenSmart: Distributed, Scalable Power Management in the Many-core Era	1
Reliability-aware Garbage Collection for Hybrid HBM-DRAM Memories	1
Towards Enhanced System Efficiency while Mitigating Row Hammer	1
Online Application Guidance for Heterogeneous Memory Systems	1
WA-Zone: Wear-Aware Zone Management Optimization for LSM-Tree on ZNS SSDs	1
Weaving Synchronous Reactions into the Fabric of SSA-form Compilers	1
SHASTA	1
PRISM	1
An Application-oblivious Memory Scheduling System for DNN Accelerators	1
FASA-DRAM: Reducing DRAM Latency with Destructive Activation and Delayed Restoration	1
PETRA	1
Cost-aware Service Placement and Scheduling in the Edge-Cloud Continuum	1
CARL: Compiler Assigned Reference Leasing	1
Cache Programming for Scientific Loops Using Leases	1
Cooperative Slack Management: Saving Energy of Multicore Processors by Trading Performance Slack Between QoS-Constrained Applications	1
Occam: Optimal Data Reuse for Convolutional Neural Networks	1
BullsEye : Scalable and Accurate Approximation Framework for Cache Miss Calculation	1
Accelerating Video Captioning on Heterogeneous System Architectures	1
Building a Fast and Efficient LSM-tree Store by Integrating Local Storage with Cloud Storage	1
Acceleration of Parallel-Blocked QR Decomposition of Tall-and-Skinny Matrices on FPGAs	1
SAC: An Ultra-Efficient Spin-based Architecture for Compressed DNNs	1
Efficient Nearest-Neighbor Data Sharing in GPUs	1
TNT: A Modular Approach to Traversing Physically Heterogeneous NOCs at Bare-wire Latency	1
Design and Implementation for Nonblocking Execution in GraphBLAS: Tradeoffs and Performance	1
SMT-Based Contention-Free Task Mapping and Scheduling on 2D/3D SMART NoC with Mixed Dimension-Order Routing	1
Fast One-Sided RDMA-Based State Machine Replication for Disaggregated Memory	1
EXPERTISE: An Effective Software-level Redundant Multithreading Scheme against Hardware Faults	1
gPPM: A Generalized Matrix Operation and Parallel Algorithm to Accelerate the Encoding/Decoding Process of Erasure Codes	1
ACTION: Adaptive Cache Block Migration in Distributed Cache Architectures	1
TLB-pilot: Mitigating TLB Contention Attack on GPUs with Microarchitecture-Aware Scheduling	1
At the Locus of Performance: Quantifying the Effects of Copious 3D-Stacked Cache on HPC Workloads	1
ULEEN: A Novel Architecture for Ultra-low-energy Edge Neural Networks	1
Performance-Energy Trade-off in Modern CMPs	1
Hierarchical Model Parallelism for Optimizing Inference on Many-core Processor via Decoupled 3D-CNN Structure	1

MAPPER: Managing Application Performance via Parallel Efficiency Regulation	1
Delay-on-Squash: Stopping Microarchitectural Replay Attacks in Their Tracks	1
FPD etect	1
SG XL	1
CIB-HIER	1
The Impact of Page Size and Microarchitecture on Instruction Address Translation Overhead	1
rNdN: Fast Query Compilation for NVIDIA GPUs	1
Advancing Direct Convolution Using Convolution Slicing Optimization and ISA Extensions	1