ACM Transactions on Architecture and Code Optimization

Papers
(The median citation count of ACM Transactions on Architecture and Code Optimization is 1. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-09-01 to 2025-09-01.)
ArticleCitations
ASM: An Adaptive Secure Multicore for Co-located Mutually Distrusting Processes39
Spiking Neural Networks in Spintronic Computational RAM39
Object Intersection Captures on Interactive Apps to Drive a Crowd-sourced Replay-based Compiler Optimization35
An Intelligent Scheduling Approach on Mobile OS for Optimizing UI Smoothness and Power29
Highly Efficient Self-checking Matrix Multiplication on Tiled AMX Accelerators23
TNT: A Modular Approach to Traversing Physically Heterogeneous NOCs at Bare-wire Latency23
ModNEF : An Open Source Modular Neuromorphic Emulator for FPGA for Low-Power In-Edge Artificial Intelligence22
TransCL: An Automatic CUDA-to-OpenCL Programs Transformation Framework20
Performance, Energy and NVM Lifetime-Aware Data Structure Refinement and Placement for Heterogeneous Memory Systems19
ESMPC: An Efficient Neural Network Training Framework for Secure Two- and Three-Party Computation16
An Accelerator for Sparse Convolutional Neural Networks Leveraging Systolic General Matrix-matrix Multiplication16
Building a Fast and Efficient LSM-tree Store by Integrating Local Storage with Cloud Storage15
Fast Convolution Meets Low Precision: Exploring Efficient Quantized Winograd Convolution on Modern CPUs15
DCMA: Accelerating Parallel DMA Transfers with a Multi-Port Direct Cached Memory Access in a Massive-Parallel Vector Processor15
A Concise Concurrent B + -Tree for Persistent Memory13
COER: A Network Interface Offloading Architecture for RDMA and Congestion Control Protocol Codesign13
SIMD-Matcher: A SIMD-based Arbitrary Matching Framework13
Tiaozhuan: A General and Efficient Indirect Branch Optimization for Binary Translation12
DeepZoning: Re-accelerate CNN Inference with Zoning Graph for Heterogeneous Edge Cluster12
Source Matching and Rewriting for MLIR Using String-Based Automata12
Mentor: A Memory-Efficient Sparse-dense Matrix Multiplication Accelerator Based on Column-Wise Product11
Accelerating Video Captioning on Heterogeneous System Architectures10
Locality-Aware CTA Scheduling for Gaming Applications10
Domain-Specific Multi-Level IR Rewriting for GPU10
iSwap: A New Memory Page Swap Mechanism for Reducing Ineffective I/O Operations in Cloud Environments10
A NUMA-Aware Version of an Adaptive Self-Scheduling Loop Scheduler10
Quantifying Resource Contention of Co-located Workloads with the System-level Entropy9
GraphSER: Distance-Aware Stream-Based Edge Repartition for Many-Core Systems9
Flexible and Effective Object Tiering for Heterogeneous Memory Systems9
AG-SpTRSV: An Automatic Framework to Optimize Sparse Triangular Solve on GPUs9
BridgeGC: An Efficient Cross-Level Garbage Collector for Big Data Frameworks8
An FPGA Overlay for CNN Inference with Fine-grained Flexible Parallelism8
COX : Exposing CUDA Warp-level Functions to CPUs8
ODGS: Dependency-Aware Scheduling for High-Level Synthesis with Graph Neural Network and Reinforcement Learning8
Accelerating Nearest Neighbor Search in 3D Point Cloud Registration on GPUs8
SnsBooster: Enhancing Sampling-based μ Arch Evaluation Efficiency through Online Performance Sensitivity Analysis8
Joint Program and Layout Transformations to Enable Convolutional Operators on Specialized Hardware Based on Constraint Programming7
Accelerating Parallel Structures in DNNs via Parallel Fusion and Operator Co-Optimization7
Efficient Cross-platform Multiplexing of Hardware Performance Counters via Adaptive Grouping7
Advancing Direct Convolution Using Convolution Slicing Optimization and ISA Extensions7
NEM-GNN: DAC/ADC-less, Scalable, Reconfigurable, Graph and Sparsity-Aware Near-Memory Accelerator for Graph Neural Networks7
Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture7
EXPERTISE: An Effective Software-level Redundant Multithreading Scheme against Hardware Faults7
HEngine: A High Performance Optimization Framework on a GPU for Homomorphic Encryption6
A Fast and Flexible FPGA-based Accelerator for Natural Language Processing Neural Networks6
HyGain: High-performance, Energy-efficient Hybrid Gain Cell-based Cache Hierarchy6
PowerMorph: QoS-Aware Server Power Reshaping for Data Center Regulation Service6
RT-GNN: Accelerating Sparse Graph Neural Networks by Tensor-CUDA Kernel Fusion6
Towards High Performance QNNs via Distribution-Based CNOT Gate Reduction6
Multi-objective Hardware-aware Neural Architecture Search with Pareto Rank-preserving Surrogate Models6
System-level Early-stage Modeling and Evaluation of IVR-assisted Processor Power Delivery System6
RaNAS: Resource-Aware Neural Architecture Search for Edge Computing6
DTAP: Accelerating Strongly-Typed Programs with Data Type-Aware Hardware Prefetching6
Low-power Near-data Instruction Execution Leveraging Opcode-based Timing Analysis6
Environmental Condition Aware Super-Resolution Acceleration Framework in Server-Client Hierarchies6
TPRepair: Tree-based Pipelined Repair in Clustered Storage Systems6
Mobile-3DCNN: An Acceleration Framework for Ultra-Real-Time Execution of Large 3D CNNs on Mobile Devices5
SimTrace: Exploiting Spatial and Temporal Sampling for Large-Scale Performance Analysis5
gECC: A GPU-based high-throughput framework for Elliptic Curve Cryptography5
Orchard: Heterogeneous Parallelism and Fine-grained Fusion for Complex Tree Traversals5
MemoriaNova: Optimizing Memory-Aware Model Inference for Edge Computing5
EDAS: Enabling Fast Data Loading for GPU Serverless Computing5
CGCGraph: Efficient CPU-GPU Co-execution for Concurrent Dynamic Graph Processing5
RACER: Avoiding End-to-End Slowdowns in Accelerated Chip Multi-Processors5
A Stable Idle Time Detection Platform for Real I/O Workloads5
Towards Optimizing Learned Index for High Performance, Memory Efficiency and NUMA Awareness5
ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes5
Accelerating Convolutional Neural Network by Exploiting Sparsity on GPUs4
Stripe-schedule Aware Repair in Erasure-coded Clusters with Heterogeneous Star Networks4
Architecting Optically Controlled Phase Change Memory4
GraphTune: An Efficient Dependency-Aware Substrate to Alleviate Irregularity in Concurrent Graph Processing4
OptiFX: Automatic Optimization for Convolutional Neural Networks with Aggressive Operator Fusion on GPUs4
WIPE: A Write-Optimized Learned Index for Persistent Memory4
x Meta : SSD-HDD-hybrid Optimization for Metadata Maintenance of Cloud-scale Object Storage4
CoolDC: A Cost-Effective Immersion-Cooled Datacenter with Workload-Aware Temperature Scaling4
Byte-Select Compression4
FlexHM: A Practical System for Heterogeneous Memory with Flexible and Efficient Performance Optimizations4
Exploring Data Layout for Sparse Tensor Times Dense Matrix on GPUs4
CASHT: Contention Analysis in Shared Hierarchies with Thefts4
JiuJITsu: Removing Gadgets with Safe Register Allocation for JIT Code Generation4
Improving Utilization of Dataflow Unit for Multi-Batch Processing4
MetaEC: An Efficient and Resilient Erasure-Coded KV Store on Disaggregated Memory3
Asynchronous Memory Access Unit: Exploiting Massive Parallelism for Far Memory Access3
Memory-Aware Functional IR for Higher-Level Synthesis of Accelerators3
SplitZNS: Towards an Efficient LSM-Tree on Zoned Namespace SSDs3
Optimizing OpenCL Barrier Synchronization and Memory Efficiency on Multi-Core DSPs3
BullsEye : Scalable and Accurate Approximation Framework for Cache Miss Calculation3
Preserving Addressability Upon GC-Triggered Data Movements on Non-Volatile Memory3
Shift-CIM: In-SRAM Alignment To Support General-Purpose Bit-level Sparsity Exploration in SRAM Multiplication3
Matrix: Multi-Cipher Structures Dataflow for Parallel and Pipelined TFHE Accelerator3
Capability-Based Efficient Data Transmission Mechanism for Serverless Computing3
An Example of Parallel Merkle Tree Traversal: Post-Quantum Leighton-Micali Signature on the GPU3
High-performance Deterministic Concurrency Using Lingua Franca3
TLB-pilot: Mitigating TLB Contention Attack on GPUs with Microarchitecture-Aware Scheduling3
Scale-out Systolic Arrays3
Jointly Optimizing Job Assignment and Resource Partitioning for Improving System Throughput in Cloud Datacenters3
Architectural Support for Sharing, Isolating and Virtualizing FPGA Resources3
3D GNLM: Efficient 3D Non-Local Means Kernel with Nested Reuse Strategies for Embedded GPUs3
Koala: Efficient Pipeline Training through Automated Schedule Searching on Domain-Specific Language3
Consequence-based Clustered Architecture3
Iterating Pointers: Enabling Static Analysis for Loop-based Pointers3
An FPGA-based Approach to Evaluate Thermal and Resource Management Strategies of Many-core Processors3
MicroProf : Code-level Attribution of Unnecessary Data Transfer in Microservice Applications3
Address/Data Instruction Steering in Clustered General Purpose Processors3
FlowPix: Accelerating Image Processing Pipelines on an FPGA Overlay using a Domain Specific Compiler3
TSN Cache: Exploiting Data Localities in Graph Computing Applications3
CoNST: Code Generator for Sparse Tensor Networks3
Abakus: Accelerating k -mer Counting with Storage Technology3
Optimization of Sparse Matrix Computation for Algebraic Multigrid on GPUs2
HAIR: Halving the Area of the Integer Register File with Odd/Even Banking2
GraphAttack2
SpecTerminator: Blocking Speculative Side Channels Based on Instruction Classes on RISC-V2
Conflict Management in Vector Register Files2
Data Deduplication Based on Content Locality of Transactions to Enhance Blockchain Scalability2
SSD-SGD: Communication Sparsification for Distributed Deep Learning Training2
A Case For Intra-rack Resource Disaggregation in HPC2
Supporting Dynamic Program Sizes in Deep Learning-Based Cost Models for Code Optimization2
GraphService: Topology-aware Constructor for Large-scale Graph Applications2
A Data-Loader Tunable Knob to Shorten GPU Idleness for Distributed Deep Learning2
PANDA: Adaptive Prefetching and Decentralized Scheduling for Dataflow Architectures2
Design and Implementation for Nonblocking Execution in GraphBLAS: Tradeoffs and Performance2
GenCNN: A Partition-Aware Multi-Objective Mapping Framework for CNN Accelerators Based on Genetic Algorithm2
Puppeteer: A Random Forest Based Manager for Hardware Prefetchers Across the Memory Hierarchy2
ReSA: Reconfigurable Systolic Array for Multiple Tiny DNN Tensors2
SAC: An Ultra-Efficient Spin-based Architecture for Compressed DNNs2
Bubble-Swap Flow Control2
MemHC: An Optimized GPU Memory Management Framework for Accelerating Many-body Correlation2
An Optimized GPU Implementation for GIST Descriptor2
Delay-on-Squash: Stopping Microarchitectural Replay Attacks in Their Tracks2
A Low-latency On-chip Cache Hierarchy for Load-to-use Stall Reduction in GPUs2
Register-Pressure-Aware Instruction Scheduling Using Ant Colony Optimization2
ApSpGEMM: Accelerating Large-scale SpGEMM with Heterogeneous Collaboration and Adaptive Panel2
SAL: Optimizing the Dataflow of Spin-based Architectures for Lightweight Neural Networks2
SMT-Based Contention-Free Task Mapping and Scheduling on 2D/3D SMART NoC with Mixed Dimension-Order Routing2
SuccinctKV: a CPU-efficient LSM-tree Based KV Store with Scan-based Compaction2
Cerberus: Triple Mode Acceleration of Sparse Matrix and Vector Multiplication2
QuCloud+: A Holistic Qubit Mapping Scheme for Single/Multi-programming on 2D/3D NISQ Quantum Computers2
SPIRIT: Scalable and Persistent In-Memory Indices for Real-Time Search2
E-BATCH: Energy-Efficient and High-Throughput RNN Batching2
PARADISE: Criticality-Aware Instruction Reordering for Power Attack Resistance2
PIMSAB: A Processing-In-Memory System with Spatially-Aware Communication and Bit-Serial-Aware Computation2
The Impact of Page Size and Microarchitecture on Instruction Address Translation Overhead2
A Pressure-Aware Policy for Contention Minimization on Multicore Systems2
PARALiA: A Performance Aware Runtime for Auto-tuning Linear Algebra on Heterogeneous Systems2
Cheetah: Accelerating Dynamic Graph Mining with Grouping Updates2
The Forward Slice Core: A High-Performance, Yet Low-Complexity Microarchitecture2
MetaSys: A Practical Open-source Metadata Management System to Implement and Evaluate Cross-layer Optimizations1
ShieldCXL: A Practical Obliviousness Support with Sealed CXL Memory1
ApHMM: Accelerating Profile Hidden Markov Models for Fast and Energy-efficient Genome Analysis1
Critical Data Backup with Hybrid Flash-Based Consumer Devices1
Symbolic Analysis for Data Plane Programs Specialization1
Turn-based Spatiotemporal Coherence for GPUs1
GPU Domain Specialization via Composable On-Package Architecture1
Partitioned Scheduling and Analysis for a Typed DAG Task on Heterogeneous Multi-Cores1
WaFFLe1
TianheGraph: Topology-aware Graph Processing1
Constructing a Supplementary Benchmark Suite to Represent Android Applications with User Interactions by using Performance Counters1
LitTLS: Lightweight Thread-Level Speculation on Little Cores1
HAKV: A Hotness-Aware Zone Management Approach to Optimizing Performance of LSM-tree-based Key-Value Stores1
A Lock-free RDMA-friendly Index in CPU-parsimonious Environments1
A Survey of General-purpose Polyhedral Compilers1
Assessing the Impact of Compiler Optimizations on GPUs Reliability1
FlexPointer: Fast Address Translation Based on Range TLB and Tagged Pointers1
ZNSFQ: An Efficient and High-Performance Fair Queue Scheduling Scheme for ZNS SSDs1
Understanding Silent Data Corruption in Processors for Mitigating its Effects1
The Droplet Search Algorithm for Kernel Scheduling1
Unveiling and Evaluating Vulnerabilities in Branch Predictors via a Three-Step Modeling Methodology1
IBing: An Efficient Interleaved Bidirectional Ring All-Reduce Algorithm for Gradient Synchronization1
Overlapping Aware Data Placement Optimizations for LSM Tree-Based Store on ZNS SSDs1
ReIPE: Recycling Idle PEs in CNN Accelerator for Vulnerable Filters Soft-Error Detection1
ShuffleInfer: Disaggregate LLM Inference for Mixed Downstream Workloads1
Solving Sparse Assignment Problems on FPGAs1
Hardware-hardened Sandbox Enclaves for Trusted Serverless Computing1
Dynamic Power Management Through Multi-agent Deep Reinforcement Learning for Heterogeneous Systems1
PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM1
Gator: Accelerating Graph Attention Networks by Jointly Optimizing Attention and Graph Processing1
Winols: A Large-Tiling Sparse Winograd CNN Accelerator on FPGAs1
MUA-Router: Maximizing the Utility-of-Allocation for On-chip Pipelining Routers1
HAVIT: An Efficient Hardware-Accelerator for Vision Transformer with Informative Patch Selection Techniques1
GiantVM: A Novel Distributed Hypervisor for Resource Aggregation with DSM-aware Optimizations1
Approx-RM: Reducing Energy on Heterogeneous Multicore Processors under Accuracy and Timing Constraints1
Compiler Support for Sparse Tensor Computations in MLIR1
Unleashing Parallelism with Elastic-Barriers1
Lock-Free High-performance Hashing for Persistent Memory via PM-aware Holistic Optimization1
CARL: Compiler Assigned Reference Leasing1
FASA-DRAM: Reducing DRAM Latency with Destructive Activation and Delayed Restoration1
A Sparsity-Aware Autonomous Path Planning Accelerator with HW/SW Co-Design and Multi-Level Dataflow Optimization1
DCSolver: Accelerating Sparse Iterative Solvers via Divide-and-Conquer on GPUs1
GOLDYLOC: Global Optimizations & Lightweight Dynamic Logic for Concurrency1
Optimizing Garbage Collection for ZNS SSDs via In-storage Data Migration and Address Remapping1
Fast One-Sided RDMA-Based State Machine Replication for Disaggregated Memory1
AOBO: A Fast-Switching Online Binary Optimizer on AArch641
Scheduling Language Chronology: Past, Present, and Future1
VersaTile: Flexible Tiled Architectures via Associative Processors1
At the Locus of Performance: Quantifying the Effects of Copious 3D-Stacked Cache on HPC Workloads1
Mapi-Pro: An Energy Efficient Memory Mapping Technique for Intermittent Computing1
In-SRAM Parallel Data Shuffle1
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