ACM Transactions on Architecture and Code Optimization

Papers
(The H4-Index of ACM Transactions on Architecture and Code Optimization is 18. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-08-01 to 2026-08-01.)
ArticleCitations
TNT: A Modular Approach to Traversing Physically Heterogeneous NOCs at Bare-wire Latency62
ASM: An Adaptive Secure Multicore for Co-located Mutually Distrusting Processes52
ESMPC: An Efficient Neural Network Training Framework for Secure Two- and Three-Party Computation38
Accelerating Verifiable Queries over Blockchain Database System Using Processing-in-memory33
Intra-request Lag-aware Cache Management to Enhance I/O Responsiveness of SSDs31
Highly Efficient Self-checking Matrix Multiplication on Tiled AMX Accelerators30
Supporting QoS Guarantee in Heterogeneous Object Storage System: A Spatio-Temporal Graph Data Processing Method30
An Intelligent Scheduling Approach on Mobile OS for Optimizing UI Smoothness and Power29
Performance, Energy and NVM Lifetime-Aware Data Structure Refinement and Placement for Heterogeneous Memory Systems29
HierMine: Accelerating Graph Pattern Mining via Hierarchical Sampling27
Characterizing Digital DRAM PIM through Modeling and Benchmarking26
ModNEF : An Open Source Modular Neuromorphic Emulator for FPGA for Low-Power In-Edge Artificial Intelligence25
TransCL: An Automatic CUDA-to-OpenCL Programs Transformation Framework25
Tiaozhuan: A General and Efficient Indirect Branch Optimization for Binary Translation22
A Concise Concurrent B + -Tree for Persistent Memory20
COER: A Network Interface Offloading Architecture for RDMA and Congestion Control Protocol Codesign18
Source Matching and Rewriting for MLIR Using String-Based Automata18
DCMA: Accelerating Parallel DMA Transfers with a Multi-Port Direct Cached Memory Access in a Massive-Parallel Vector Processor18
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