ACM Transactions on Embedded Computing Systems

Papers
(The median citation count of ACM Transactions on Embedded Computing Systems is 1. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-04-01 to 2024-04-01.)
ArticleCitations
Toward a Lingua Franca for Deterministic Concurrent Systems36
Edge-AI-Driven Framework with Efficient Mobile Network Design for Facial Expression Recognition29
MARS: mmWave-based Assistive Rehabilitation System for Smart Healthcare28
Game-Based Task Offloading of Multiple Mobile Devices with QoS in Mobile Edge Computing Systems of Limited Computation Capacity26
TensorRT-Based Framework and Optimization Methodology for Deep Learning Inference on Jetson Boards26
Heuristic Computation Offloading Algorithms for Mobile Users in Fog Computing26
SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks24
Verifying the Safety of Autonomous Systems with Neural Network Controllers23
Deep Ensemble Learning for Human Activity Recognition Using Wearable Sensors via Filter Activation22
Side-channel Analysis of Lattice-based Post-quantum Cryptography: Exploiting Polynomial Multiplication22
Intermittent-Aware Neural Architecture Search19
Distributed Task Offloading and Resource Purchasing in NOMA-Enabled Mobile Edge Computing: Hierarchical Game Theoretical Approaches18
LATTE: L STM Self- Att ention based Anomaly Detection in E mbedded Automotive Platforms18
Edge Intelligence: Concepts, Architectures, Applications, and Future Directions17
Algorithm-hardware Co-design of Attention Mechanism on FPGA Devices16
Edge-SLAM: Edge-Assisted Visual Simultaneous Localization and Mapping16
ROBIN: A Robust Optical Binary Neural Network Accelerator16
Reliability-aware Scheduling and Routing for Messages in Time-sensitive Networking16
HMDS: A Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems15
MHDeep: Mental Health Disorder Detection System Based on Wearable Sensors and Artificial Neural Networks15
SLAQA15
SNR: S queezing N umerical R ange Defuses Bit Error Vulnerability Surface in Deep Neural Networks15
Predictive Monitoring with Logic-Calibrated Uncertainty for Cyber-Physical Systems15
Camaroptera: A Long-range Image Sensor with Local Inference for Remote Sensing Applications14
Design Space Exploration for Ultra-Low-Energy and Secure IoT MCUs14
Improving Performance-Power-Programmability in Space Avionics with Edge Devices: VBN on Myriad2 SoC14
TAMA14
A Survey of Blockchain Data Management Systems14
Improving Power of DSP and CNN Hardware Accelerators Using Approximate Floating-point Multipliers13
SAGE: A Split-Architecture Methodology for Efficient End-to-End Autonomous Vehicle Control13
Hardware Performance Counter-Based Fine-Grained Malware Detection13
AppAxO : Designing App lication-specific A ppro x imate O 13
CAN Bus Intrusion Detection Based on Auxiliary Classifier GAN and Out-of-distribution Detection13
Event-B Hybridation12
CICERO: A Domain-Specific Architecture for Efficient Regular Expression Matching11
Learning Nondeterministic Real-Time Automata11
EC-ECC: Accelerating Elliptic Curve Cryptography for Edge Computing on Embedded GPU TX211
DEEPEYE11
An Interpretable Machine Learning Model Enhanced Integrated CPU-GPU DVFS Governor11
Compositional Learning and Verification of Neural Network Controllers11
Improving Variational Autoencoder based Out-of-Distribution Detection for Embedded Real-time Applications11
FELIX: A Ferroelectric FET Based Low Power Mixed-Signal In-Memory Architecture for DNN Acceleration10
CEDR: A Compiler-integrated, Extensible DSSoC Runtime10
Post-Quantum Signatures on RISC-V with Hardware Acceleration10
Dealing with Uncertainty in pWCET Estimations10
DFSynthesizer: Dataflow-based Synthesis of Spiking Neural Networks to Neuromorphic Hardware10
Horizontal Side-Channel Vulnerabilities of Post-Quantum Key Exchange and Encapsulation Protocols10
Real-time Attack-recovery for Cyber-physical Systems Using Linear-quadratic Regulator10
DynO: Dynamic Onloading of Deep Neural Networks from Cloud to Device9
Demystifying Energy Consumption Dynamics in Transiently powered Computers9
Design Space Exploration for Secure IoT Devices and Cyber-Physical Systems9
AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers9
Towards an Integrated Vehicle Management System in DriveOS9
Thermal-aware Adaptive Platform Management for Heterogeneous Embedded Systems9
Learning to Train CNNs on Faulty ReRAM-based Manycore Accelerators9
Golden Chip-Free Trojan Detection Leveraging Trojan Trigger’s Side-Channel Fingerprinting9
A Composable Monitoring System for Heterogeneous Embedded Platforms9
Heterogeneity-aware Multicore Synchronization for Intermittent Systems8
Horizontal Auto-Scaling for Multi-Access Edge Computing Using Safe Reinforcement Learning8
Design-Technology Co-Optimization for NVM-Based Neuromorphic Processing Elements8
SEAMS8
FLASH: F ast Neura l A rchitecture S earch with H ardware8
Online Learning for Orchestration of Inference in Multi-user End-edge-cloud Networks8
Determinism8
Synergistically Exploiting CNN Pruning and HLS Versioning for Adaptive Inference on Multi-FPGAs at the Edge8
Reducing Energy in GPGPUs through Approximate Trivial Bypassing8
MAGNETO8
Fast and Energy-Efficient State Checkpointing for Intermittent Computing8
Software-Managed Read and Write Wear-Leveling for Non-Volatile Main Memory8
Two Birds With One Stone: Boosting Both Search and Write Performance for Tree Indices on Persistent Memory8
RT-ZooKeeper: Taming the Recovery Latency of a Coordination Service8
An Energy-Efficient DRAM Cache Architecture for Mobile Platforms With PCM-Based Main Memory8
DNN Is Not All You Need: Parallelizing Non-neural ML Algorithms on Ultra-low-power IoT Processors8
Winograd Convolution for Deep Neural Networks: Efficient Point Selection7
MemFHE: End-to-end Computing with Fully Homomorphic Encryption in Memory7
LAMBDA7
Domain-specific Hybrid Mapping for Energy-efficient Baseband Processing in Wireless Networks7
Block Walsh–Hadamard Transform-based Binary Layers in Deep Neural Networks7
MaxTracker: Continuously Tracking the Maximum Computation Progress for Energy Harvesting ReRAM-based CNN Accelerators7
Virtualizing a Post-Moore’s Law Analog Mesh Processor: The Case of a Photonic PDE Accelerator7
Rtkaller: State-aware Task Generation for RTOS Fuzzing7
Side-channel and Fault-injection attacks over Lattice-based Post-quantum Schemes (Kyber, Dilithium): Survey and New Results7
SPECTRUM7
Energy-efficient Real-time Scheduling on Multicores6
EncoDeep6
Tolerating Defects in Low-Power Neural Network Accelerators Via Retraining-Free Weight Approximation6
Efficient Realization of Decision Trees for Real-Time Inference6
QUAREM: Maximising QoE Through Adaptive Resource Management in Mobile MPSoC Platforms6
A TCAM-based Caching Architecture Framework for Packet Classification6
A Distributed Real-time Scheduling System for Industrial Wireless Networks6
Improving the Performance of Hybrid Caches Using Partitioned Victim Caching6
Trustworthy Autonomous System Development6
Generalized Weakly Hard Schedulability Analysis for Real-Time Periodic Tasks6
Chauffeur: Benchmark Suite for Design and End-to-End Analysis of Self-Driving Vehicles on Embedded Systems6
Crab-tree6
RiSA: A Reinforced Systolic Array for Depthwise Convolutions and Embedded Tensor Reshaping6
Temporal Robustness of Temporal Logic Specifications: Analysis and Control Design6
Software Hint-Driven Data Management for Hybrid Memory in Mobile Systems6
Sense Your Power6
PhiNets: A Scalable Backbone for Low-power AI at the Edge6
Human Activity Recognition on Microcontrollers with Quantized and Adaptive Deep Neural Networks6
Domain-Specific Architectures: Research Problems and Promising Approaches6
Reliability Assessment and Safety Arguments for Machine Learning Components in System Assurance5
Probabilistic Estimation of Threat Intrusion in Embedded Systems for Runtime Detection5
DSTL5
Quantized Sparse Training: A Unified Trainable Framework for Joint Pruning and Quantization in DNNs5
A Configurable CRYSTALS-Kyber Hardware Implementation with Side-Channel Protection5
Facilitating Human Activity Data Annotation via Context-Aware Change Detection on Smartwatches5
??????: Utilizing Hyperdimensional Computing for a More Robust and Efficient Machine Learning System5
Synaptic Activity and Hardware Footprint of Spiking Neural Networks in Digital Neuromorphic Systems5
Approximate Cache in GPGPUs5
Accelerating Attention Mechanism on FPGAs based on Efficient Reconfigurable Systolic Array5
GMAI5
Hardware Trojan Detection Using Machine Learning: A Tutorial5
Optimus: An Operator Fusion Framework for Deep Neural Networks5
DIAC5
Application-centric Network Management - Addressing Safety and Real-time in V2X Applications5
Energy-efficient and Reliable Inference in Nonvolatile Memory under Extreme Operating Conditions5
Toward Adversary-aware Non-iterative Model Pruning through D ynamic N etwork R ewiring of DNNs5
Hardware Acceleration for Embedded Keyword Spotting: Tutorial and Survey5
UBAR5
Optimization of Signal Processing Applications Using Parameterized Error Models for Approximate Adders5
Skills Gaps in the Industry5
Beyond Cache Attacks5
Adaptive Computation Reuse for Energy-Efficient Training of Deep Neural Networks5
Test Generation for Hardware Trojan Detection Using Correlation Analysis and Genetic Algorithm5
More Is Less: Model Augmentation for Intermittent Deep Inference5
Adaptive Task Allocation and Scheduling on NoC-based Multicore Platforms with Multitasking Processors5
HW-FlowQ: A Multi-Abstraction Level HW-CNN Co-design Quantization Methodology5
Contention Grading and Adaptive Model Selection for Machine Vision in Embedded Systems5
Synthesis-guided Adversarial Scenario Generation for Gray-box Feedback Control Systems with Sensing Imperfections4
On-device Prior Knowledge Incorporated Learning for Personalized Atrial Fibrillation Detection4
High-performance Reconfigurable DNN Accelerator on a Bandwidth-limited Embedded System4
ETAP: Energy-aware Timing Analysis of Intermittent Programs4
Early DSE and Automatic Generation of Coarse-grained Merged Accelerators4
Minimizing Stack Memory for Partitioned Mixed-criticality Scheduling on Multiprocessor Platforms4
Scheduling in Real-Time Mobile Systems4
Reliable and Secure Design-Space-Exploration for Cyber-Physical Systems4
Survey of Control-flow Integrity Techniques for Real-time Embedded Systems4
DL-RSIM: A Reliability and Deployment Strategy Simulation Framework for ReRAM-based CNN Accelerators4
Microarchitectural Exploration of STT-MRAM Last-level Cache Parameters for Energy-efficient Devices4
Comparative Analysis and Enhancement of CFG-based Hardware-Assisted CFI Schemes4
REPAIR: Control Flow Protection based on Register Pairing Updates for SW-Implemented HW Fault Tolerance4
Exploiting Activation Sparsity for Fast CNN Inference on Mobile GPUs4
LPWAN in the TV White Spaces4
MSYNC: A Generalized Formal Design Pattern for Virtually Synchronous Multirate Cyber-physical Systems4
Applying Multiple Level Cell to Non-volatile FPGAs4
TAB: Unified and Optimized Ternary, Binary, and Mixed-precision Neural Network Inference on the Edge4
AdaTest: Reinforcement Learning and Adaptive Sampling for On-chip Hardware Trojan Detection4
FARSI: An Early-stage Design Space Exploration Framework to Tame the Domain-specific System-on-chip Complexity4
Cache Interference-aware Task Partitioning for Non-preemptive Real-time Multi-core Systems4
A Vector-Length Agnostic Compiler for the Connex-S Accelerator with Scratchpad Memory4
Vector Extensions in COTS Processors to Increase Guaranteed Performance in Real-Time Systems4
On the RTL Implementation of FINN Matrix Vector Unit4
SG-Float: Achieving Memory Access and Computing Power Reduction Using Self-Gating Float in CNNs3
Structured Proofs for Adversarial Cyber-Physical Systems3
Does SoC Hardware Development Become Agile by Saying So: A Literature Review and Mapping Study3
CODEBench: A Neural Architecture and Hardware Accelerator Co-Design Framework3
Probabilistic Risk-Aware Scheduling with Deadline Constraint for Heterogeneous SoCs3
A proven translation from a UML state machine subset to timed automata3
Experimental Demonstration of STT-MRAM-based Nonvolatile Instantly On/Off System for IoT Applications: Case Studies3
Optimizing Tensor Contractions for Embedded Devices with Racetrack and DRAM Memories3
Compositional Timing Analysis of Asynchronized Distributed Cause-effect Chains3
Cross-Layer Adaptation with Safety-Assured Proactive Task Job Skipping3
Efficient-Grad: Efficient Training Deep Convolutional Neural Networks on Edge Devices with Grad ient Optimizations3
A Framework for Neural Network Architecture and Compile Co-optimization3
Exploring Efficient Architectures on Remote In-Memory NVM over RDMA3
An Efficient CNN Accelerator for Low-Cost Edge Systems3
Agile Acceleration of Stateful Hash-based Signatures in Hardware3
TrustFlow-X3
Risk of Stochastic Systems for Temporal Logic Specifications3
Tutorial: Toward Robust Deep Learning against Poisoning Attacks3
Reconfigurable System-on-Chip Architectures for Robust Visual SLAM on Humanoid Robots3
Federated Self-training for Semi-supervised Audio Recognition3
IoT-Fog-Cloud Centric Earthquake Monitoring and Prediction3
Prediction Modeling for Application-Specific Communication Architecture Design of Optical NoC3
Attack-resilient Fusion of Sensor Data with Uncertain Delays3
How Flexible is Your Computing System?3
Introduction to the Special Issue on Memory and Storage Systems for Embedded and IoT Applications3
SIKE in 32-bit ARM Processors Based on Redundant Number System for NIST Level-II3
Performance and Power Estimation of STT-MRAM Main Memory with Reliable System-level Simulation3
SensorGAN: A Novel Data Recovery Approach for Wearable Human Activity Recognition3
Holistic Resource Allocation Under Federated Scheduling for Parallel Real-time Tasks3
Secure and Lightweight Blockchain-based Truthful Data Trading for Real-Time Vehicular Crowdsensing3
Prepare: P owe r -Awar e A p proximate Re a l3
DASS: Differentiable Architecture Search for Sparse Neural Networks3
Scenario Based Run-Time Switching for Adaptive CNN-Based Applications at the Edge3
Formally Verified Next-generation Airborne Collision Avoidance Games in ACAS X3
Resource-Efficient Continual Learning for Sensor-Based Human Activity Recognition2
TyBox: an automatic design and code-generation toolbox for TinyML incremental on-device learning2
HEART: H ybrid Memory and E nergy- A ware R eal- T 2
Mining Hyperproperties using Temporal Logics2
DirectNVM: Hardware-accelerated NVMe SSDs for High-performance Embedded Computing2
A review of abstraction methods towards verifying neural networks2
A Contrastive Plan Explanation Framework for Hybrid System Models2
Benchmarking and Configuring Security Levels in Intermittent Computing2
CABARRE: Request Response Arbitration for Shared Cache Management2
Multi-bit Data Flow Error Detection Method Based on SDC Vulnerability Analysis2
A Passive Online Technique for Learning Hybrid Automata from Input/Output Traces2
TinyNS: Platform-Aware Neurosymbolic Auto Tiny Machine Learning2
Online Processing of Vehicular Data on the Edge Through an Unsupervised TinyML Regression Technique2
PHiLIP on the HiL: Automated Multi-Platform OS Testing With External Reference Devices2
Cooperative Coevolution-based Design Space Exploration for Multi-mode Dataflow Mapping2
Efficient External Sorting for Memory-Constrained Embedded Devices with Flash Memory2
Resource-demand Estimation for Edge Tensor Processing Units2
Killing Processes or Killing Flash? Escaping from the Dilemma Using Lightweight, Compression-Aware Swap for Mobile Devices2
ARES: Persistently Secure Non-Volatile Memory with Processor-transparent and Hardware-friendly Integrity Verification and Metadata Recovery2
FedHIL: Heterogeneity Resilient Federated Learning for Robust Indoor Localization with Mobile Devices2
An Ultra-low-power Embedded AI Fire Detection and Crowd Counting System for Indoor Areas2
Automatic Generation of Resource and Accuracy Configurable Processing Elements2
Hardware-friendly User-specific Machine Learning for Edge Devices2
D y VED eep2
Formally Verified Loop-Invariant Code Motion and Assorted Optimizations2
Hierarchical Resource Orchestration Framework for Real-time Containers2
Code-size-aware Scheduling of Synchronous Dataflow Graphs on Multicore Systems2
L 2 C: Combining Lossy and Lossless Compression on Memory and I/O2
Firmness Analysis of Real-time Tasks2
A Framework for Calculating WCET Based on Execution Decision Diagrams2
Dataflow Driven Partitioning of Machine Learning Applications for Optimal Energy Use in Batteryless Systems2
Brain-inspired Cognition in Next-generation Racetrack Memories2
ViT4Mal: Lightweight Vision Transformer for Malware Detection on Edge Devices2
Supervisory Control for Dynamic Feature Configuration in Product Lines2
SHARP: An Adaptable, Energy-Efficient Accelerator for Recurrent Neural Networks2
Fine-grained Hardware Acceleration for Efficient Batteryless Intermittent Inference on the Edge2
Optimal Checkpointing Strategy for Real-time Systems with Both Logical and Timing Correctness2
Enhancing the Energy Efficiency and Robustness of tinyML Computer Vision Using Coarsely-Quantized Log-Gradient Input Images2
Regime Inference for Sound Floating-Point Optimizations2
Integrated Hardware Garbage Collection2
Interactive Programmatic Modeling2
Schedulability Analysis for Timed Automata With Tasks2
Verified Lustre Normalization with Node Subsampling2
Protecting Network-on-Chip Intellectual Property Using Timing Channel Fingerprinting2
Trireme: Exploration of Hierarchical Multi-level Parallelism for Hardware Acceleration2
Application of Logical Sub-networking in Congestion-aware Deadlock-free SDmesh Routing2
wfspan: Wait-free Dynamic Memory Management2
Creating Hardware Component Knowledge Bases with Training Data Generation and Multi-task Learning2
Energy-Efficient Approximate Edge Inference Systems2
ACDSE: A Design Space Exploration Method for CNN Accelerator based on Adaptive Compression Mechanism2
TCX: A RISC Style Tensor Computing Extension and a Programmable Tensor Processor1
A Hierarchical Hybrid Locking Protocol for Parallel Real-Time Tasks1
Verifying Stochastic Hybrid Systems with Temporal Logic Specifications via Model Reduction1
Hephaestus : Codesigning and Automating 3D Image Registration on Reconfigurable Architectures1
Hardware Performance Counters: Ready-Made vs Tailor-Made1
Challenges and Opportunities of Security-Aware EDA1
A Unified Programmable Edge Matrix Processor for Deep Neural Networks and Matrix Algebra1
Network-level Design Space Exploration of Resource-constrained Networks-of-Systems1
Analysis of EM Fault Injection on Bit-sliced Number Theoretic Transform Software in Dilithium1
XploreNAS : Explore Adversarially Robust and Hardware-efficient Neural Architectures for Non-ideal Xbars1
Toward Object-oriented Modeling in SCCharts1
An Intermediate-Centric Dataflow for Transposed Convolution Acceleration on FPGA1
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