OOIR: Observatory of International Research

Papers

(The TQCC of ACM Transactions on Design Automation of Electronic Systems is 3. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-03-01 to 2024-03-01.)

Article	Citations
Machine Learning for Electronic Design Automation: A Survey	100
Enable Deep Learning on Mobile Devices: Methods, Systems, and Applications	39
Security Assessment of Dynamically Obfuscated Scan Chain Against Oracle-guided Attacks	27
AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators	20
Reconfigurable Network-on-Chip Security Architecture	19
An Energy-aware Online Learning Framework for Resource Management in Heterogeneous Platforms	19
TAAL	18
MaxSense	16
SCRIPT	16
Adversarial Perturbation Attacks on ML-based CAD	16
Modular Neural Networks for Low-Power Image Classification on Embedded Devices	14
High-Level Synthesis of Key-Obfuscated RTL IP with Design Lockout and Camouflaging	13
A Comprehensive Survey of Attacks without Physical Access Targeting Hardware Vulnerabilities in IoT/IIoT Devices, and Their Detection Mechanisms	12
Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design	11
EF-Train: Enable Efficient On-device CNN Training on FPGA through Data Reshaping for Online Adaptation or Personalization	11
Voltage-Based Covert Channels Using FPGAs	10
A Hierarchical HVAC Control Scheme for Energy-aware Smart Building Automation	10
Strong Logic Obfuscation with Low Overhead against IC Reverse Engineering Attacks	10
Core Placement Optimization for Multi-chip Many-core Neural Network Systems with Reinforcement Learning	10
Machine Learning Assisted PUF Calibration for Trustworthy Proof of Sensor Data in IoT	10
PREASC	10
FTT-NAS: Discovering Fault-tolerant Convolutional Neural Architecture	10
A Robust Modulus-Based Matrix Splitting Iteration Method for Mixed-Cell-Height Circuit Legalization	9
Algorithmic Fault Detection for RRAM-based Matrix Operations	9
Runtime Identification of Hardware Trojans by Feature Analysis on Gate-Level Unstructured Data and Anomaly Detection	8

CeMux: Maximizing the Accuracy of Stochastic Mux Adders and an Application to Filter Design	8
A Survey on Security of Digital Microfluidic Biochips: Technology, Attack, and Defense	8
MNFTL	8
Directed Test Generation for Activation of Security Assertions in RTL Models	8
NoC Application Mapping Optimization Using Reinforcement Learning	7
Security Threat Analyses and Attack Models for Approximate Computing Systems	7
High-Level Synthesis Implementation of an Embedded Real-Time HEVC Intra Encoder on FPGA for Media Applications	7
Machine Learning for Congestion Management and Routability Prediction within FPGA Placement	7
FUBOCO: Structure Synthesis of Basic Op-Amps by FUnctional BlOck COmposition	7
TransNet	7
MeF-RAM: A New Non-Volatile Cache Memory Based on Magneto-Electric FET	7
Machine Learning Approach for Fast Electromigration Aware Aging Prediction in Incremental Design of Large Scale On-chip Power Grid Network	7
Learning from the Past: Efficient High-level Synthesis Design Space Exploration for FPGAs	6
A Tensor Network based Decision Diagram for Representation of Quantum Circuits	6
Towards Smarter Diagnosis	6
Design Flow and Methodology for Dynamic and Static Energy-constrained Scheduling Framework in Heterogeneous Multicore Embedded Devices	6
NeuPow	6
How Secure Is Split Manufacturing in Preventing Hardware Trojan?	6
A Deterministic-Path Routing Algorithm for Tolerating Many Faults on Very-Large-Scale Network-on-Chip	6
HeM3D	6
A Module-Linking Graph Assisted Hybrid Optimization Framework for Custom Analog and Mixed-Signal Circuit Parameter Synthesis	6
Mitigating Negative Impacts of Read Disturb in SSDs	5
Quantum Circuit Transformation: A Monte Carlo Tree Search Framework	5
Dataflow Model–based Software Synthesis Framework for Parallel and Distributed Embedded Systems	5
Implementation, Characterization and Application of Path Changing Switch based Arbiter PUF on FPGA as a lightweight Security Primitive for IoT	5
Multi-Fidelity Surrogate-Based Optimization for Electromagnetic Simulation Acceleration	4
Sherlock: A Multi-Objective Design Space Exploration Framework	4
Robust Multi-Target Sample Preparation on MEDA Biochips Obviating Waste Production	4
High-throughput Near-Memory Processing on CNNs with 3D HBM-like Memory	4
Machine Learning Approaches for Efficient Design Space Exploration of Application-Specific NoCs	4
ESPSim: An Efficient Scalable Power Grid Simulator Based on Parallel Algebraic Multigrid	4
SwitchX : Gmin-Gmax Switching for Energy-efficient and Robust Implementation of Binarized Neural Networks on ReRAM Xbars	4
Fine-grained Adaptive Testing Based on Quality Prediction	4
Graph Neural Networks for High-Level Synthesis Design Space Exploration	4
A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits	4
Machine Learning-based Defect Coverage Boosting of Analog Circuits under Measurement Variations	4
RASCv2: Enabling Remote Access to Side-Channels for Mission Critical and IoT Systems	4
A Runtime Reconfigurable Design of Compute-in-Memory–Based Hardware Accelerator for Deep Learning Inference	4
Design Space Optimization of Shared Memory Architecture in Accelerator-rich Systems	4
Architectural Design of Flow-Based Microfluidic Biochips for Multi-Target Dilution of Biochemical Fluids	4
Security of Microfluidic Biochip	4
Magnetic Core TSV-Inductor Design and Optimization for On-chip DC-DC Converter	4
Predicting Memory Compiler Performance Outputs Using Feed-forward Neural Networks	4
Efficient Layout Hotspot Detection via Neural Architecture Search	4
FastCFI: Real-time Control-Flow Integrity Using FPGA without Code Instrumentation	3
COPE	3
Leveraging Automatic High-Level Synthesis Resource Sharing to Maximize Dynamical Voltage Overscaling with Error Control	3
Energy-Efficient GPU L2 Cache Design Using Instruction-Level Data Locality Similarity	3
Machine Learning for Statistical Modeling	3
Wire Load Oriented Analog Routing with Matching Constraints	3

Toward Taming the Overhead Monster for Data-flow Integrity	3
Distance-aware Approximate Nanophotonic Interconnect	3
Automatic Mapping of the Best-Suited DNN Pruning Schemes for Real-Time Mobile Acceleration	3
Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration	3
A Comprehensive Survey on Electronic Design Automation and Graph Neural Networks: Theory and Applications	3
Software/Hardware Co-design of 3D NoC-based GPU Architectures for Accelerated Graph Computations	3
A Native SPICE Implementation of Memristor Models for Simulation of Neuromorphic Analog Signal Processing Circuits	3