ACM Transactions on Design Automation of Electronic Systems

Papers
(The TQCC of ACM Transactions on Design Automation of Electronic Systems is 3. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-11-01 to 2024-11-01.)
ArticleCitations
Machine Learning for Electronic Design Automation: A Survey136
Enable Deep Learning on Mobile Devices: Methods, Systems, and Applications51
Security Assessment of Dynamically Obfuscated Scan Chain Against Oracle-guided Attacks33
AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators31
TAAL21
MaxSense19
A Survey on Security of Digital Microfluidic Biochips: Technology, Attack, and Defense18
VeriGen: A Large Language Model for Verilog Code Generation16
A Comprehensive Survey of Attacks without Physical Access Targeting Hardware Vulnerabilities in IoT/IIoT Devices, and Their Detection Mechanisms15
EF-Train: Enable Efficient On-device CNN Training on FPGA through Data Reshaping for Online Adaptation or Personalization14
FTT-NAS: Discovering Fault-tolerant Convolutional Neural Architecture13
CeMux: Maximizing the Accuracy of Stochastic Mux Adders and an Application to Filter Design13
A Tensor Network based Decision Diagram for Representation of Quantum Circuits12
Voltage-Based Covert Channels Using FPGAs12
A Robust Modulus-Based Matrix Splitting Iteration Method for Mixed-Cell-Height Circuit Legalization12
Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design12
Directed Test Generation for Activation of Security Assertions in RTL Models11
A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits11
High-Level Synthesis Implementation of an Embedded Real-Time HEVC Intra Encoder on FPGA for Media Applications10
NoC Application Mapping Optimization Using Reinforcement Learning10
A Comprehensive Survey on Electronic Design Automation and Graph Neural Networks: Theory and Applications9
ESPSim: An Efficient Scalable Power Grid Simulator Based on Parallel Algebraic Multigrid9
MeF-RAM: A New Non-Volatile Cache Memory Based on Magneto-Electric FET9
Security Threat Analyses and Attack Models for Approximate Computing Systems9
Implementation, Characterization and Application of Path Changing Switch based Arbiter PUF on FPGA as a lightweight Security Primitive for IoT8
Graph Neural Networks for High-Level Synthesis Design Space Exploration8
FastCFI: Real-time Control-Flow Integrity Using FPGA without Code Instrumentation7
HeM3D7
FUBOCO: Structure Synthesis of Basic Op-Amps by FUnctional BlOck COmposition7
Learning from the Past: Efficient High-level Synthesis Design Space Exploration for FPGAs7
Dataflow Model–based Software Synthesis Framework for Parallel and Distributed Embedded Systems7
A Module-Linking Graph Assisted Hybrid Optimization Framework for Custom Analog and Mixed-Signal Circuit Parameter Synthesis7
Design Flow and Methodology for Dynamic and Static Energy-constrained Scheduling Framework in Heterogeneous Multicore Embedded Devices7
RASCv2: Enabling Remote Access to Side-Channels for Mission Critical and IoT Systems7
Sherlock: A Multi-Objective Design Space Exploration Framework7
A Survey and Perspective on Artificial Intelligence for Security-Aware Electronic Design Automation7
Security of Electrical, Optical, and Wireless On-chip Interconnects: A Survey6
Auto-tuning Fixed-point Precision with TVM on RISC-V Packed SIMD Extension6
A Runtime Reconfigurable Design of Compute-in-Memory–Based Hardware Accelerator for Deep Learning Inference6
Quantum Circuit Transformation: A Monte Carlo Tree Search Framework6
High-throughput Near-Memory Processing on CNNs with 3D HBM-like Memory6
SwitchX: Gmin-Gmax Switching for Energy-efficient and Robust Implementation of Binarized Neural Networks on ReRAM Xbars6
Hardware Security Risks and Threat Analyses in Advanced Manufacturing Industry5
Efficient Layout Hotspot Detection via Neural Architecture Search5
A Native SPICE Implementation of Memristor Models for Simulation of Neuromorphic Analog Signal Processing Circuits5
Fault-based Built-in Self-test and Evaluation of Phase Locked Loops5
MOEA/D vs. NSGA-II: A Comprehensive Comparison for Multi/Many Objective Analog/RF Circuit Optimization through a Generic Benchmark5
Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration5
CNN-Cap: Effective Convolutional Neural Network-based Capacitance Models for Interconnect Capacitance Extraction5
Ax-BxP: Approximate Blocked Computation for Precision-reconfigurable Deep Neural Network Acceleration4
Software/Hardware Co-design of 3D NoC-based GPU Architectures for Accelerated Graph Computations4
Design Space Optimization of Shared Memory Architecture in Accelerator-rich Systems4
Deep Reinforcement Learning-based Mining Task Offloading Scheme for Intelligent Connected Vehicles in UAV-aided MEC4
A Compact TRNG Design for FPGA Based on the Metastability of RO-driven Shift Registers4
DDAM: D ata D istribution- A ware M apping of CNNs on Processing-In-Memory S4
DeepFlow: A Cross-Stack Pathfinding Framework for Distributed AI Systems4
A Compact High-Dimensional Yield Analysis Method using Low-Rank Tensor Approximation4
Magnetic Core TSV-Inductor Design and Optimization for On-chip DC-DC Converter4
A Learning-based Methodology for Scenario-aware Mapping of Soft Real-time Applications onto Heterogeneous MPSoCs4
A Design Methodology for Energy-Aware Processing in Unmanned Aerial Vehicles4
Test Point Insertion for Multi-Cycle Power-On Self-Test4
Heterogeneous Integration Supply Chain Integrity Through Blockchain and CHSM4
MVP: An Efficient CNN Accelerator with Matrix, Vector, and Processing-Near-Memory Units3
Leveraging Automatic High-Level Synthesis Resource Sharing to Maximize Dynamical Voltage Overscaling with Error Control3
Toward Taming the Overhead Monster for Data-flow Integrity3
CRP2.0: A Fast and Robust Cooperation between Routing and Placement in Advanced Technology Nodes3
Automatic Mapping of the Best-Suited DNN Pruning Schemes for Real-Time Mobile Acceleration3
TMDS: Temperature-aware Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems3
COPE3
Multiterminal Pathfinding in Practical VLSI Systems with Deep Neural Networks3
SecureTVM: A TVM-based Compiler Framework for Selective Privacy-preserving Neural Inference3
A Low-power Programmable Machine Learning Hardware Accelerator Design for Intelligent Edge Devices3
NeuroCool: Dynamic Thermal Management of 3D DRAM for Deep Neural Networks through Customized Prefetching3
Accelerating Graph Computations on 3D NoC-Enabled PIM Architectures3
Demand-Driven Multi-Target Sample Preparation on Resource-Constrained Digital Microfluidic Biochips3
Multi-Objective Optimization for Safety-Related Available E/E Architectures Scoping Highly Automated Driving Vehicles3
Placement of Digital Microfluidic Biochips via a New Evolutionary Algorithm3
Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements3
On-chip ESD Protection Design Methodologies by CAD Simulation3
Machine Learning for Statistical Modeling3
Multi-objective Optimization of Mapping Dataflow Applications to MPSoCs Using a Hybrid Evaluation Combining Analytic Models and Measurements3
A Dynamic Huffman Coding Method for Reliable TLC NAND Flash Memory3
CBDC-PUF: A Novel Physical Unclonable Function Design Framework Utilizing Configurable Butterfly Delay Chain Against Modeling Attack3
Synthesizing Brain-network-inspired Interconnections for Large-scale Network-on-chips3
A Switching NMOS Based Single Ended Sense Amplifier for High Density SRAM Applications3
GraphPlanner: Floorplanning with Graph Neural Network3
Energy-Efficient LSTM Inference Accelerator for Real-Time Causal Prediction3
A Delay-Adjustable, Self-Testable Flip-Flop for Soft-Error Tolerability and Delay-Fault Testability3
ECO-GNN: Signoff Power Prediction Using Graph Neural Networks with Subgraph Approximation3
A High Throughput STR-based TRNG by Jitter Precise Quantization Superposing3
A Symbolic Approach to Detecting Hardware Trojans Triggered by Don’t Care Transitions3
A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route3
MEDUSA: A Multi-Resolution Machine Learning Congestion Estimation Method for 2D and 3D Global Routing3
Energy Efficient Boosting of GEMM Accelerators for DNN via Reuse3
TROP: TRust-aware OPportunistic Routing in NoC with Hardware Trojans3
Distance-aware Approximate Nanophotonic Interconnect3
0.29846096038818