ACM Transactions on Design Automation of Electronic Systems

Article	Citations
Layout Synthesis for Quantum Circuits Considering Toffoli Gate Decomposition	210
Reduced On-chip Storage of Seeds for Built-in Test Generation	50
Multi-Row Guiding Template Design for Lamellar Directed Self-Assembly with Self-Aligned Via Process	46
InterAxNN: Reconfigurable and Approximate in-Memory Processing Accelerator for Ultra-Low-Power Binary Neural Network Inference in Intermittently Powered Systems	43
Introduction to the Special Issue on Machine Learning for CAD, Part I	36
ARDiS: A Portable and Unified Resource Management Framework in Real Hardware Systems	32
DNA: DC Nodal Analysis Attack for Evaluation of Analog Obfuscation Techniques	30
Scalable Yield Analysis of SRAM and Analog Circuits Using Multi-Kernel Sparse Representation	27
IDeSyDe: Systematic Design Space Exploration via Design Space Identification	26
EnVector: Encoding using Pattern based Vectors for Energy Efficient Non-Volatile Main Memories	25
DyLDPC: A Dynamic LDPC Code with Variable Correction Capability to Improve Decoding Performance for 3D NAND Flash Memory	23
PAPlace: Performance-Driven Differentiable Analog Placement	22
Fast Area Optimization Approach for XNOR/OR-based Fixed Polarity Reed-Muller Logic Circuits based on Multi-strategy Wolf Pack Algorithm	21
Graph Neural Networks for High-Level Synthesis Design Space Exploration	20
A Problem-tailored Adversarial Deep Neural Network-Based Attack Model for Feed-Forward Physical Unclonable Functions	20
Exploring Large Language Models for Hierarchical Hardware Circuit and Testbench Generation	19
Inferencing on Edge Devices: A Time- and Space-aware Co-scheduling Approach	19
X-OCTANE: eXplainable On-Chip Telemetry-based Anomaly Notification Engine for Silicon Lifecycle Management	18
A High-Performance Accelerator for Real-Time Super-Resolution on Edge FPGAs	18
A Mixed-Criticality Traffic Scheduler with Mitigating Congestion for CAN-to-TSN Gateway	17
C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap	17
The Resistance Analysis Attack and Security Enhancement of the IMC LUT Based on the Complementary Resistive Switch Cells	17
Introduction to the Special Issue on Embedded System Software/Tools	16
DTGx2: Dual Target Diagnostic Test Generation	16
Towards Generalizable and Efficient Circuit Topology Design: A Graph-Transformer-based Surrogate Model with Curriculum Learning	15

SparGD: A Sparse GEMM Accelerator with Dynamic Dataflow	15
A Reliability-Aware Splitting Duty-Cycle Physical Unclonable Function Based on Trade-off Process, Voltage, and Temperature Variations	15
ParSCo: Performance-Driven Par titioning and S cheduling Co	15
Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs	15
Securing Network-on-Chips against Trojan-Induced Packet Duplication Attacks	15
Component Fault Diagnosability of Hierarchical Cubic Networks	15
STRIVE: Empowering a Low Power Tensor Processing Unit with Fault Detection and Error Resilience	14
Rethinking Logic Rewriting: Technology-Aware Subgraph Matching with Exact Synthesis	14
Type-Aware Heterogeneous Graph Network for Circuit Link Prediction	14
Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems	14
Scheduling Task Graph Applications on Preloaded Shared-Bus based Heterogeneous Platforms	14
ECO-GNN: Signoff Power Prediction Using Graph Neural Networks with Subgraph Approximation	13
Evaluating LLM-based Workflows for Switched-Mode Power Supply Design	13
EDA-Copilot: A RAG-Powered Intelligent Assistant for EDA Tools	13
Enhanced TransUNet Framework for Predicting Static IR Drop and Chip Routability	12
Context-aware Data Augmentation for Hardware Code Fault localization	12
Harnessing Machine Learning in Dynamic Thermal Management in Embedded CPU-GPU Platforms	12
Interactive Visual Performance Space Exploration of Operational Amplifiers with Differentiable Neural Network Surrogate Models	12
SGAP: A Scatter-Gather Processing-in-Memory Architecture with Fixed-Point Reconfiguration for Energy-Efficient DNNs	11
Enhanced Real-time Scheduling of AVB Flows in Time-Sensitive Networking	11
MCMC-Escape: Multi-Capacity Ordered Escape Routing Based on Monte-Carlo Tree Search	11
The Simply-V Framework: An Extensible RISC-V Reconfigurable Soft-SoC for Open Research and Fast Prototyping	11
Thermal Attack on RO-PUFs: The Cases of Bulk 65 nm and FDSOI 28 nm	11
MARVEL: Multi-Agent RTL Vulnerability Extraction using Large Language Models	10
Programmable In-memory Computing Circuit of Fast Hartley Transform	10
VeriGen: A Large Language Model for Verilog Code Generation	10
Optimal Pattern Retargeting in IEEE 1687 Networks: A SAT-based Upper-Bound Computation	10
Non-Preemptive Scheduling of Periodic Tasks with Data Dependencies in Heterogeneous Multiprocessor Embedded Systems	10
A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator	10
RedPIM: An Efficient PIM Accelerator Design with Reduced Analog-to-Digital Conversions	9
ChipletPart: Cost-Aware Partitioning for 2.5D Systems	9
Boosting VLSI Design Flow Parameter Tuning with Random Embedding and Multi-objective Trust-region Bayesian Optimization	9
You Only Need Non-Hotspot: An Unsupervised Training-Free Method for Layout Hotspot Detection	9
Dynamic Per-Flow Queues in Shared Buffer TSN Switches	9
A Survey of Machine Learning Approaches in Logic Synthesis	9
RADI: A High-Performance Reconfigurable Array-Based Accelerator for DNN Implementations	9
LLMsafe-Spectre: Efficient Spectre Attack Detection in LLM Environments using An Intelligent HPC events Selection Methodology	9
Optimal Model Partitioning with Low-Overhead Profiling on the PIM-based Platform for Deep Learning Inference	9
Corrigendum: A data-centric chip design agent framework for Verilog code generation	9
AiTPO: KAN-UNet Heterogeneous Network for Timing Prediction and Optimization at Global Routing	9
AI4DSE: Leveraging Dynamic Graph Neural Networks and Large Language Models for Optimizing High-Level Synthesis Design Space Exploration	9
Online Synthesis of MEDA Biochips with Area and Reliability-Aware Module Placement using Chamber-Less Virtual Topology	8
LHS: LLM Assisted Efficient High-level Synthesis of Deep Learning Tasks	8
A Canonical Test Representation for Verification of Shared-Memory Behavior in Multiprocessor Systems	8
Multicycle Tests with Compressed Primary Input Sequences and an Extended Primary Input Scan Chain	8
Poor Man’s Training on MCUs: A Memory-Efficient Quantized Back-Propagation-Free Approach	8
ThRIve: Thermally Robust CNN Inference via Low-Rank Adaptation in Heterogeneous PIM Architectures	8
Training PPA Models for Embedded Memories on a Low-data Diet	8
An Efficient Reinforcement Learning Based Framework for Exploring Logic Synthesis	8
Systemization of Knowledge: Robust Deep Learning using Hardware-software co-design in Centralized and Federated Settings	8

Detecting Adversarial Examples Utilizing Pixel Value Diversity	8
A Hybrid Reinforcement Learning Framework for Efficient Physical Design Parameter Tuning	7
MFIT : Multi-FIdelity Thermal Modeling for 2.5D and 3D Multi-Chiplet Architectures	7
A Heterogeneous Chiplet Architecture for Accelerating End-to-End Transformer Models	7
RL-MUL 2.0: Multiplier Design Optimization with Parallel Deep Reinforcement Learning and Space Reduction	7
ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction	7
DeepVerifier: Learning to Update Test Sequences for Coverage-Guided Verification	7
Multi-channel TRNG based on Scalable Cascaded Full Feedback Ring Oscillator	7
Real-time Blood Pressure Prediction on Wearables with Edge-Based DNNs: A Co-Design Approach	7
Mitigating Memory Wall Effects in CNN Engines with On-the-Fly Weights Generation	7
TriHOT: Triangular and Hexagonal Norm Based Timing-Driven Optical Routing with Wavelength Division Multiplexing	7
MapTune: Versatile ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning	7
FLAG: F inding L ine A nomalies (in RTL code) with	7
FPGA Routing Congestion Prediction via Graph Learning-Aided Conditional GAN	7
LLM-assisted Bug Identification and Correction for Verilog HDL	7
Design Automation Techniques for Microfluidic Fully Programmable Valve Array Biochips: A Systematic Survey	7
GANDSE: Generative Adversarial Network-based Design Space Exploration for Neural Network Accelerator Design	7
NeuroCool: Dynamic Thermal Management of 3D DRAM for Deep Neural Networks through Customized Prefetching	7
Optimal Mixed-Cell-Height Detailed Placement with Discrete Spacing Costs	7
Interpretable Cross-Corner Timing Prediction Based on XGBoost-SHAP Solution	6
GenPart 2.0: Enhanced Hypergraph Partitioning with Vertex Weight Handling using a Generative Model	6
An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators	6
Fault-Tolerant Cyclic Queuing and Forwarding with Fast ACK in Time-Sensitive Networking	6
A Single Bitline Highly Stable, Low Power With High Speed Half-Select Disturb Free 11T SRAM Cell	6
Learning-based Phase-aware Multi-core CPU Workload Forecasting	6
A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits	6
VelKoz: Generating Accelerators for Rigid-Flexible Robots through Domain Specific High-level Synthesis	6
PSCaps: High-Performance Pose-Sensitive Layout Hotspot Detector based on CapsNet	6
Runtime Fault Localization in Deep Neural Network Accelerators	6
Breaking The Buffer : Covert Channel Attacks by Overrunning Buffer and Countermeasures	6
A Scenario-Based DVFS-Aware Hybrid Application Mapping Methodology for MPSoCs	6
DPTM: An Adaptive Scheduler Design Utilizing Timeslot Matching and Release Methods for Concurrent and Multi-task Interleaved Pipelining-oriented CGRA	6
Efficient and Effective E-graph-based Logic Optimization	6
Deep Reinforcement Learning-Based Resource Allocation with Enhanced Perception and Low-Latency for Autonomous Driving in ISAC-aided VEC	6
Aging Aware Steepening of the Fault Coverage Curve of a Scan Based Transition Fault Test Set	5
Security Evaluation of State Space Obfuscation of Hardware IP through a Red Team-Blue Team Practice	5
GAN-Place: Advancing Open Source Placers to Commercial-quality Using Generative Adversarial Networks and Transfer Learning	5
Polling-Based Memory Interface	5
Sensor-Aware Data Imputation for Time-Series Machine Learning on Low-Power Wearable Devices	5
Structurally Secure Obfuscation: Assessing and Mitigating Structural Vulnerabilities in Circuits Obfuscation	5
MCMCF-Router: Multi-capacity Ordered Escape Routing Algorithms for Grid/Staggered Pin Array	5
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration	5
A General Layout Pattern Clustering Using Geometric Matching-based Clip Relocation and Lower-bound Aided Optimization	5
A High-performance Masking Design Approach for Saber against High-order Side-channel Attack	5
Efficient Timing Prediction and Optimization Using Derivable Gradient Boosting Machine Model at Placement Stage	5
Application Mapping and Control-system Design for Microfluidic Biochips with Distributed Channel Storage	5
DANCE: DAta-Network Co-optimization for Efficient Segmentation Model Training and Inference	5
Multi-Objective Optimization for Safety-Related Available E/E Architectures Scoping Highly Automated Driving Vehicles	5
A Soft-Error Mitigation Approach Using Pulse Quenching Enhancement at Detailed Placement for Combinational Circuits	5
Scan Chain Watermarking : A Graph Neural Network based approach	5
MOEA/D vs. NSGA-II: A Comprehensive Comparison for Multi/Many Objective Analog/RF Circuit Optimization through a Generic Benchmark	5
Semi-Permanent Stuck-At Fault injection attacks on Elephant and GIFT lightweight ciphers	5
Scalable and Accelerated Self-healing Control Circuit Using Evolvable Hardware	5
Support Vector Machine Aided Semi-intelligent Performance Enhancement of CMOS Gate-voltage Bootstrapped Sampling Switch	5
Ultrafast Generative AI by Ultradense 3D Integration: A Case Study on LLM-based Edge Inference	4
High-level Synthesis Directives Design Optimization via Large Language Model	4
MAB-BMC: A Formal Verification Enhancer by Harnessing Multiple BMC Engines Together	4
HAPE: Hardware-Aware LLM Pruning For Efficient On-Device Inference Optimization	4
Surrogate Lagrangian Relaxation: A Path to Retrain-Free Deep Neural Network Pruning	4
RSPP: Restricted Static Pseudo-Partitioning for Mitigation of Cross-Core Covert Channel Attacks	4
SensTDDP: A Timing Sensitivity Analysis Framework with Application to Timing-Driven Detailed Placement	4
Rescuing ReRAM-based Neural Computing Systems from Device Variation	4
Hardware-aware Quantization/Mapping Strategies for Compute-in-Memory Accelerators	4
Routability Optimization of Extreme Aspect Ratio Design through Non-uniform Placement Utilization and Selective Flip-flop Stacking	4
A Fast and Accurate Single-Event Transient Reliability Analysis of Logic Circuits Using Adaptive Importance Sampling Method	4
ChatDSE: A Zero-Shot Microarchitecture Design Space Explorer Powered by GPT4.0	4
Precise Learning-to-Rank Bug Localization Using Multi-Feature Fusion for Hardware Code	4
Empirical Guidelines for Deploying LLMs onto Resource-constrained Edge Devices	4
Bridging Hotspot Detection and Mask Optimization via Domain-Crossing Masked Layout Modeling	4
A Systematic Mapping Study on SystemC/TLM Modeling Capabilities in New Research Domains	4
A Power Optimization Approach for Large-scale RM-TB Dual Logic Circuits Based on an Adaptive Multi-Task Intelligent Algorithm	4
OneSyn: One-Pass Architectural Synthesis Algorithm for Fully Programmable Valve Array Biochips	4
Two-dimensional Search Space for Extracting Broadside Tests from Functional Test Sequences	4
ForgePattern: Flexible Layout Pattern Generation through Reinforcement Learning	4
Dynamic Adaptation Using Deep Reinforcement Learning for Digital Microfluidic Biochips	4
Efficient Test Chip Design via Smart Computation	4
LOFMPL: An Open-source Logic Optimization Framework with MFFC-based Hypergraph Partition and Reinforcement Learning for Large Circuits	4
Machine-learning-driven Architectural Selection of Adders and Multipliers in Logic Synthesis	4
Timing-driven Approximate Logic Synthesis Based on Cooperative Search	4
Efficient Attacks on Strong PUFs via Covariance and Boolean Modeling	4

A Cascaded ReRAM-based Crossbar Architecture for Transformer Neural Network Acceleration	4
Algorithm-Hardware Co-design for Accelerating Depthwise Separable CNNs	4
A Compact TRNG Design for FPGA Based on the Metastability of RO-driven Shift Registers	4
A Switching NMOS Based Single Ended Sense Amplifier for High Density SRAM Applications	4
Mathematical Framework for Optimizing Crossbar Allocation for ReRAM-based CNN Accelerators	4
SpiceFuzz: LLM-Based Fuzzing for Spice Circuit Simulator Tools Bug Detection	4
Introduction to the Special Issue on Machine Learning for CAD/EDA	4
Introduction to Special Issue on Large Language Models for Electronic System Design Automation	4
An Improved MCTS Algorithm for Ordered Escape Routing of Differential Pair	4
VHMP: A High-efficacy and Parallel Processing Approach for CGRCA Supporting Virtual Heterogeneous Multi-core and Intra-core Multitask Pipeline	4
A High Efficient and Scalable Obstacle-Avoiding VLSI Global Routing Flow	3
Resister: A Resilient Interposer Architecture for Chiplet to Mitigate Timing Side-Channel Attacks	3
Modeling Retention Errors of 3D NAND Flash for Optimizing Data Placement	3
Harmonic Estimation and Comparative Analysis of Ultra-High Speed Flip-Flop and Latch Topologies for Low Power and High Performance Future Generation Micro-/Nano Electronic Systems	3
CRP2.0: A Fast and Robust Cooperation between Routing and Placement in Advanced Technology Nodes	3
Enhancing Lifetime and Performance of MLC NVM Caches Using Embedded Trace Buffers	3
PriorMSM: An Efficient Acceleration Architecture for Multi-Scalar Multiplication	3
A CNN-Based Technique to Assist Layout-to-Generator Conversion for Analog Circuits	3
Estimating Power, Performance, and Area for On-Sensor Deployment of AR/VR Workloads Using an Analytical Framework	3
An Active Learning Framework for Analog Circuit Multi-objective Customization	3
Introduction to the Special Section on Energy-Efficient AI Chips	3
SWEEP: Gathering Hot Read/Write Data Together to Minimize Read Reclaims in SSDs	3
SafeTI: A Hardware Traffic Injector for Complex MPSoC Platform Validation and Characterization	3
PPD: A Portable and Highly Parallel Dispatching System for Deep Learning	3
TMDS: Temperature-aware Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems	3
A Brain-Inspired Hardware Architecture for Evolutionary Algorithms Based on Memristive Arrays	3
AutoSilicon: Scaling Up RTL Design Generation Capability of Large Language Models	3
Construction of All Multilayer Monolithic RSMTs and Its Application to Monolithic 3D IC Routing	3
Energy-aware Scheduling of Workflow Applications Towards Schedule Length Optimization in Heterogeneous Distributed Embedded Systems	3
Graphene-based interconnect exploration for FPGA design and optimization towards the end of the roadmap	3
Structured Dynamic Precision for Deep Neural Networks Quantization	3
A Survey on Transistor-Level Electrical Rule Checking of Integrated Circuits	3
OptoLink: Breaking Memory Bandwidth Bottlenecks in FHE Accelerators with Photonic Interconnects	3
Graph Neural Network based Initialization for Timing Driven Placement	3
HEANA : A Hybrid Time-Amplitude Analog Optical Accelerator with Flexible Dataflows for Energy-Efficient CNN Inference	3
LightSim: A Flexible, Fast Modeling Framework for Holistic Photonic Computing Systems	3
Introduction to the Special Issue on Design for Testability and Reliability of Security-aware Hardware	3
AIMCU-MESO: An In-Memory Computing Unit Constructed by MESO Device	3
A High Throughput STR-based TRNG by Jitter Precise Quantization Superposing	3
Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation	3
LASM: Extensible Competitive Scheduling Framework for VLIW Assembly Optimization	3
Datapath Combinational Equivalence Checking With Hybrid Sweeping Engines and Parallelization	3
On Enhancing the Security of Streaming Scan Network through Dual-Functional TDR	3
An Analytical Placement Framework for Advanced Hybrid-Row-Height Circuit Designs	3
Transfer Learning Enabled Modeling Paradigm for PVT-aware Circuit Performance Estimation	2
Enhanced PATRON: Fault Injection and Power-aware FSM Encoding Through Linear Programming	2
Scalable High-Fidelity Solver for Large-Scale ReRAM Crossbar Arrays Under I–V Nonlinearity	2
Towards LDPC Read Performance of 3D Flash Memories with Layer-induced Error Characteristics	2
Pareto Optimization of Analog Circuits Using Reinforcement Learning	2
Effective Concurrent Attack Detection Framework through Laser Fault Informed Balanced Optical Neural Network Observation	2
EasyMRC: Efficient Mask Rule Checking via Representative Edge Sampling	2
AGD: Analytic Gradient Descent for Discrete Optimization in EDA and its Use to Gate Sizing	2
DRC-SG 2.0: Efficient Design Rule Checking Script Generation via Key Information Extraction	2
ASAPatch- Automated, Scalable And Programmable Framework For Post-Silicon Security Remediation	2
PROTECTS: Progressive Rtl Obfuscation with ThrEshold Control Technique during architectural Synthesis	2
Sorting it out in Hardware: A State-of-the-Art Survey	2
GEMA+: A Hardware Accelerator for Exact Sequence Mapping Using Learned Indexing with Reduced Sensitivity to Read Length	2
Learning Interpretable Differentiable Logic Networks for Tabular Regression	2
LaMAGIC: Advanced Circuit Formulations for Language-Model-based Topology Generation for Analog Integrated Circuits	2
Unveiling Cross-checking Opportunities in Verilog Compilers	2
FixRTL: Auto-correction of Multiple RTL Bugs by a New Feature Burst Clustering Algorithm and Mutation	2
gem5-NVDLA: A Simulation Framework for Compiling, Scheduling, and Architecture Evaluation on AI System-on-Chips	2
Automatic Correction of Arithmetic Circuits in the Presence of Multiple Bugs by Groebner Basis Modification	2
Comparative Analysis of Dynamic Power Consumption of Parallel Prefix Adder	2
FV-LIDAC: Formally Verified Library of Input Data Aware Approximate Arithmetic Circuits	2
APEX: an Adaptive Photonic-Electronic Chiplet Interconnection Architecture for DNN Inference	2
FedTM: Federated ASIC Technology Mapping	2
Global Placement Exploiting Soft 2D Regularity	2
Layout Decomposition and Printing Time Optimization for Inkjet-Printed Electronics	2
iPO: Constant Liar Parameter Optimization for Placement with Representation and Transfer Learning	2
CuPBoP: Making CUDA a Portable Language	2
SHAREDD: Sharing of Test Data and Design-for-Testability Logic for Transition Fault Tests under Standard Scan	2
CB-EVO: Contextual Bandit Tuning with Evolutionary Search for Logic Synthesis	2
Task Modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems with Heterogeneous Resources	2
ZeroD-fender: A Resource-aware IoT Malware Detection Engine via Fine-grained Side-channel Analysis	2
G-kway: Multilevel GPU-Accelerated k-way Graph Partitioner using Task Graph Parallelism	2
Wages: The Worst Transistor Aging Analysis for Large-scale Analog Integrated Circuits via Domain Generalization	2
Towards Floating Point-Based AI Acceleration: Hybrid PIM with Non-Uniform Data Format and Reduced Multiplications	2
ProtFe: Low-Cost Secure Power Side-Channel Protection for General and Custom FeFET-Based Memories	2
Secure & Reliable 10T SRAM Cell during Read, Write and Hold Operations against Power Analysis Attack	2
Improving the Performance of CNN Accelerator Architecture under the Impact of Process Variations	2
Detecting Hardware Trojans in High-Level Synthesis-Generated RTL using Large Language Models	2
Corrigendum: RADI: A High-Performance Reconfigurable Array-Based Accelerator for DNN Implementations	2
Multi-Stream Scheduling of Inference Pipelines on Edge Devices - a DRL Approach	2
ICBPI: Accurate and Validated Fine-Grained Power Estimation with Application to Thermal Hardware Trojan Detection and Localization in SOCs	2
STCO: Enhancing Training Efficiency via Structured Sparse Tensor Compilation Optimization	2
NPU-Accelerated Imitation Learning for Thermal Optimization of QoS-Constrained Heterogeneous Multi-Cores	2
Application-level Validation of Accelerator Designs Using a Formal Software/Hardware Interface	2
GED-Net: A Multi-modal Reconstruction Network for CAD Parametric Models based on Grouped Entity Decoding	2
Mitigating Mode-switch through Run-time Computation of Response Time	2
Data Pruning-enabled High Performance and Reliable Graph Neural Network Training on ReRAM-based Processing-in-Memory Accelerators	2
A Self-Checking RRAM-Based PUF with Reliability-Quantified CRPs via Resistance-Delay Mapping	2
Massively Parallel In-Memory Computing via Frequency Multiplexing in Ferroelectric Capacitive Memory Arrays	2
Translating Test Responses to Images for Test-termination Prediction via Multiple Machine Learning Strategies	2
GoSteiner: Constructing Rectilinear Steiner Minimum Tree on Directed Graph	2