ACM Transactions on Design Automation of Electronic Systems

Papers
(The median citation count of ACM Transactions on Design Automation of Electronic Systems is 1. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-06-01 to 2025-06-01.)
ArticleCitations
A Module-Linking Graph Assisted Hybrid Optimization Framework for Custom Analog and Mixed-Signal Circuit Parameter Synthesis192
IDeSyDe: Systematic Design Space Exploration via Design Space Identification89
Reduced On-chip Storage of Seeds for Built-in Test Generation61
A Compact High-Dimensional Yield Analysis Method using Low-Rank Tensor Approximation48
A Problem-tailored Adversarial Deep Neural Network-Based Attack Model for Feed-Forward Physical Unclonable Functions25
Inferencing on Edge Devices: A Time- and Space-aware Co-scheduling Approach23
A High-Performance Accelerator for Real-Time Super-Resolution on Edge FPGAs22
C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap20
Graph Neural Networks for High-Level Synthesis Design Space Exploration20
Multi-Row Guiding Template Design for Lamellar Directed Self-Assembly with Self-Aligned Via Process20
A Mixed-Criticality Traffic Scheduler with Mitigating Congestion for CAN-to-TSN Gateway19
Machine Learning for Electronic Design Automation: A Survey17
Fast Area Optimization Approach for XNOR/OR-based Fixed Polarity Reed-Muller Logic Circuits based on Multi-strategy Wolf Pack Algorithm17
ECO-GNN: Signoff Power Prediction Using Graph Neural Networks with Subgraph Approximation16
SparGD: A Sparse GEMM Accelerator with Dynamic Dataflow16
DTGx2: Dual Target Diagnostic Test Generation15
Component Fault Diagnosability of Hierarchical Cubic Networks15
Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs13
Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems13
A Reliability-Aware Splitting Duty-Cycle Physical Unclonable Function Based on Trade-off Process, Voltage, and Temperature Variations12
Introduction to the Special Issue on Embedded System Software/Tools12
The Resistance Analysis Attack and Security Enhancement of the IMC LUT Based on the Complementary Resistive Switch Cells12
Towards Fine-Grained Online Adaptive Approximation Control for Dense SLAM on Embedded GPUs11
STRIVE: Empowering a Low Power Tensor Processing Unit with Fault Detection and Error Resilience11
Context-aware Data Augmentation for Hardware Code Fault localization11
A Tensor Network based Decision Diagram for Representation of Quantum Circuits11
Harnessing Machine Learning in Dynamic Thermal Management in Embedded CPU-GPU Platforms10
Non-Preemptive Scheduling of Periodic Tasks with Data Dependencies in Heterogeneous Multiprocessor Embedded Systems10
EDA-Copilot: A RAG-Powered Intelligent Assistant for EDA Tools10
Programmable In-memory Computing Circuit of Fast Hartley Transform9
Enhanced Real-time Scheduling of AVB Flows in Time-Sensitive Networking9
ParTBC: Faster Estimation of Top- k Betweenness Centrality Vertices on GPU9
VeriGen: A Large Language Model for Verilog Code Generation9
Optimal Pattern Retargeting in IEEE 1687 Networks: A SAT-based Upper-Bound Computation8
An Efficient Reinforcement Learning Based Framework for Exploring Logic Synthesis8
Optimal Model Partitioning with Low-Overhead Profiling on the PIM-based Platform for Deep Learning Inference8
A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator8
Dynamic Per-Flow Queues in Shared Buffer TSN Switches8
Training PPA Models for Embedded Memories on a Low-data Diet7
Improving LDPC Decoding Performance for 3D TLC NAND Flash by LLR Optimization Scheme for Hard and Soft Decision7
LHS: LLM Assisted Efficient High-level Synthesis of Deep Learning Tasks7
A Heterogeneous Chiplet Architecture for Accelerating End-to-End Transformer Models7
Real-time Blood Pressure Prediction on Wearables with Edge-Based DNNs: A Co-Design Approach7
AiTPO: KAN-UNet Heterogeneous Network for Timing Prediction and Optimization at Global Routing7
Systemization of Knowledge: Robust Deep Learning using Hardware-software co-design in Centralized and Federated Settings7
Detecting Adversarial Examples Utilizing Pixel Value Diversity7
Boosting VLSI Design Flow Parameter Tuning with Random Embedding and Multi-objective Trust-region Bayesian Optimization7
RL-MUL 2.0: Multiplier Design Optimization with Parallel Deep Reinforcement Learning and Space Reduction6
Demand-Driven Multi-Target Sample Preparation on Resource-Constrained Digital Microfluidic Biochips6
LLM-assisted Bug Identification and Correction for Verilog HDL6
An Efficient Execution Framework of Two-Part Execution Scenario Analysis6
A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits6
DeepVerifier: Learning to Update Test Sequences for Coverage-Guided Verification6
TriHOT: Triangular and Hexagonal Norm Based Timing-Driven Optical Routing with Wavelength Division Multiplexing6
GANDSE: Generative Adversarial Network-based Design Space Exploration for Neural Network Accelerator Design6
Mitigating Memory Wall Effects in CNN Engines with On-the-Fly Weights Generation6
NeuroCool: Dynamic Thermal Management of 3D DRAM for Deep Neural Networks through Customized Prefetching6
FLAG: F inding L ine A nomalies (in RTL code) with G enerative AI5
A Scenario-Based DVFS-Aware Hybrid Application Mapping Methodology for MPSoCs5
Fault-Tolerant Cyclic Queuing and Forwarding with Fast ACK in Time-Sensitive Networking5
An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators5
MCMCF-Router: Multi-capacity Ordered Escape Routing Algorithms for Grid/Staggered Pin Array5
GenPart 2.0: Enhanced Hypergraph Partitioning with Vertex Weight Handling using a Generative Model5
CeMux: Maximizing the Accuracy of Stochastic Mux Adders and an Application to Filter Design5
Learning-based Phase-aware Multi-core CPU Workload Forecasting5
A Single Bitline Highly Stable, Low Power With High Speed Half-Select Disturb Free 11T SRAM Cell5
GAN-Place: Advancing Open Source Placers to Commercial-quality Using Generative Adversarial Networks and Transfer Learning5
A Soft-Error Mitigation Approach Using Pulse Quenching Enhancement at Detailed Placement for Combinational Circuits5
Quantum Circuit Transformation: A Monte Carlo Tree Search Framework5
Optimal Mixed-Cell-Height Detailed Placement with Discrete Spacing Costs5
Deep Reinforcement Learning-Based Resource Allocation with Enhanced Perception and Low-Latency for Autonomous Driving in ISAC-aided VEC5
PSCaps: High-Performance Pose-Sensitive Layout Hotspot Detector based on CapsNet5
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration5
A High-performance Masking Design Approach for Saber against High-order Side-channel Attack5
MOEA/D vs. NSGA-II: A Comprehensive Comparison for Multi/Many Objective Analog/RF Circuit Optimization through a Generic Benchmark4
Polling-Based Memory Interface4
Surrogate Lagrangian Relaxation: A Path to Retrain-Free Deep Neural Network Pruning4
MAB-BMC: A Formal Verification Enhancer by Harnessing Multiple BMC Engines Together4
DANCE: DAta-Network Co-optimization for Efficient Segmentation Model Training and Inference4
Sensor-Aware Data Imputation for Time-Series Machine Learning on Low-Power Wearable Devices4
FUBOCO: Structure Synthesis of Basic Op-Amps by FUnctional BlOck COmposition4
Semi-Permanent Stuck-At Fault injection attacks on Elephant and GIFT lightweight ciphers4
Efficient Attacks on Strong PUFs via Covariance and Boolean Modeling4
Algorithm-Hardware Co-design for Accelerating Depthwise Separable CNNs4
Scalable and Accelerated Self-healing Control Circuit Using Evolvable Hardware4
Multi-Objective Optimization for Safety-Related Available E/E Architectures Scoping Highly Automated Driving Vehicles4
A General Layout Pattern Clustering Using Geometric Matching-based Clip Relocation and Lower-bound Aided Optimization4
Application Mapping and Control-system Design for Microfluidic Biochips with Distributed Channel Storage4
Machine-learning-driven Architectural Selection of Adders and Multipliers in Logic Synthesis4
Automatic Mapping of the Best-Suited DNN Pruning Schemes for Real-Time Mobile Acceleration4
Fault Localization Scheme for Missing Gate Faults in Reversible Circuits4
A Cascaded ReRAM-based Crossbar Architecture for Transformer Neural Network Acceleration4
Security Evaluation of State Space Obfuscation of Hardware IP through a Red Team-Blue Team Practice4
Hardware-aware Quantization/Mapping Strategies for Compute-in-Memory Accelerators3
Synthesis of Clock Networks with a Mode-Reconfigurable Topology3
ChatDSE: A Zero-Shot Microarchitecture Design Space Explorer Powered by GPT4.03
A Power Optimization Approach for Large-scale RM-TB Dual Logic Circuits Based on an Adaptive Multi-Task Intelligent Algorithm3
Bridging Hotspot Detection and Mask Optimization via Domain-Crossing Masked Layout Modeling3
A Switching NMOS Based Single Ended Sense Amplifier for High Density SRAM Applications3
RSPP: Restricted Static Pseudo-Partitioning for Mitigation of Cross-Core Covert Channel Attacks3
Two-dimensional Search Space for Extracting Broadside Tests from Functional Test Sequences3
Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation3
Efficient Test Chip Design via Smart Computation3
A Compact TRNG Design for FPGA Based on the Metastability of RO-driven Shift Registers3
A Systematic Mapping Study on SystemC/TLM Modeling Capabilities in New Research Domains3
Empirical Guidelines for Deploying LLMs onto Resource-constrained Edge Devices3
Dynamic Adaptation Using Deep Reinforcement Learning for Digital Microfluidic Biochips3
Estimating Power, Performance, and Area for On-Sensor Deployment of AR/VR Workloads Using an Analytical Framework3
Learning from the Past: Efficient High-level Synthesis Design Space Exploration for FPGAs3
Rescuing ReRAM-based Neural Computing Systems from Device Variation3
Introduction to the Special Issue on Machine Learning for CAD/EDA3
Routability Optimization of Extreme Aspect Ratio Design through Non-uniform Placement Utilization and Selective Flip-flop Stacking3
A Low-Overhead and High-Security Cryptographic Circuit Design Utilizing the TIGFET-Based Three-Phase Single-Rail Pulse Register against Side-Channel Attacks3
Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic Devices3
Ax-BxP: Approximate Blocked Computation for Precision-reconfigurable Deep Neural Network Acceleration3
Construction of All Multilayer Monolithic RSMTs and Its Application to Monolithic 3D IC Routing3
Mathematical Framework for Optimizing Crossbar Allocation for ReRAM-based CNN Accelerators3
PriorMSM: An Efficient Acceleration Architecture for Multi-Scalar Multiplication3
Structured Dynamic Precision for Deep Neural Networks Quantization3
HEANA : A Hybrid Time-Amplitude Analog Optical Accelerator with Flexible Dataflows for Energy-Efficient CNN Inference2
Task Modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems with Heterogeneous Resources2
Introduction to the Special Section on Energy-Efficient AI Chips2
Enhancing Lifetime and Performance of MLC NVM Caches Using Embedded Trace Buffers2
EF-Train: Enable Efficient On-device CNN Training on FPGA through Data Reshaping for Online Adaptation or Personalization2
Energy Efficient Boosting of GEMM Accelerators for DNN via Reuse2
Pareto Optimization of Analog Circuits Using Reinforcement Learning2
Layout Decomposition and Printing Time Optimization for Inkjet-Printed Electronics2
SafeTI: A Hardware Traffic Injector for Complex MPSoC Platform Validation and Characterization2
Modified Decoupled Sense Amplifier with Improved Sensing Speed for Low-Voltage Differential SRAM2
Sherlock: A Multi-Objective Design Space Exploration Framework2
Improving the Performance of CNN Accelerator Architecture under the Impact of Process Variations2
gem5-NVDLA: A Simulation Framework for Compiling, Scheduling, and Architecture Evaluation on AI System-on-Chips2
Memristive-based Mixed-signal CGRA for Accelerating Deep Neural Network Inference2
A High Throughput STR-based TRNG by Jitter Precise Quantization Superposing2
Distance-aware Approximate Nanophotonic Interconnect2
Unveiling Cross-checking Opportunities in Verilog Compilers2
An Adaptive Application Framework with Customizable Quality Metrics2
TMDS: Temperature-aware Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems2
Introduction to the Special Issue on Design for Testability and Reliability of Security-aware Hardware2
Advancing Hyperdimensional Computing Based on Trainable Encoding and Adaptive Training for Efficient and Accurate Learning2
A Conditionally Chaotic Physically Unclonable Function Design Framework with High Reliability2
Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design2
A Brain-Inspired Hardware Architecture for Evolutionary Algorithms Based on Memristive Arrays2
Multi-Stream Scheduling of Inference Pipelines on Edge Devices - a DRL Approach2
Secure & Reliable 10T SRAM Cell during Read, Write and Hold Operations against Power Analysis Attack2
CuPBoP: Making CUDA a Portable Language2
CRP2.0: A Fast and Robust Cooperation between Routing and Placement in Advanced Technology Nodes2
DRC-SG 2.0: Efficient Design Rule Checking Script Generation via Key Information Extraction2
Implementation, Characterization and Application of Path Changing Switch based Arbiter PUF on FPGA as a lightweight Security Primitive for IoT2
A Design Methodology for Energy-Aware Processing in Unmanned Aerial Vehicles2
Harmonic Estimation and Comparative Analysis of Ultra-High Speed Flip-Flop and Latch Topologies for Low Power and High Performance Future Generation Micro-/Nano Electronic Systems2
Application-level Validation of Accelerator Designs Using a Formal Software/Hardware Interface2
AutoSilicon: Scaling Up RTL Design Generation Capability of Large Language Models2
Modeling Retention Errors of 3D NAND Flash for Optimizing Data Placement2
Transfer Learning Enabled Modeling Paradigm for PVT-aware Circuit Performance Estimation2
HSG-RAG: Hierarchical Knowledge Base Construction for Embedded System Development2
Towards LDPC Read Performance of 3D Flash Memories with Layer-induced Error Characteristics2
Translating Test Responses to Images for Test-termination Prediction via Multiple Machine Learning Strategies2
NPU-Accelerated Imitation Learning for Thermal Optimization of QoS-Constrained Heterogeneous Multi-Cores2
Enhanced PATRON: Fault Injection and Power-aware FSM Encoding Through Linear Programming2
LOGIC: Logic Synthesis for Digital In-Memory Computing2
Comparative Analysis of Dynamic Power Consumption of Parallel Prefix Adder2
Adaptive Redistribution Layer Routing for Chiplet-Package Co-Design in 2.5D System2
G-kway: Multilevel GPU-Accelerated k-way Graph Partitioner using Task Graph Parallelism2
AIMCU-MESO: An In-Memory Computing Unit Constructed by MESO Device2
ARM-CO-UP: ARM COoperative Utilization of Processors2
Global Interconnect Optimization1
A Novel Hybrid Cache Coherence with Global Snooping for Many-core Architectures1
Mitigating Mode-switch through Run-time Computation of Response Time1
Deep Reinforcement Learning-based Mining Task Offloading Scheme for Intelligent Connected Vehicles in UAV-aided MEC1
PROTECTS: Progressive Rtl Obfuscation with ThrEshold Control Technique during architectural Synthesis1
Sorting it out in Hardware: A State-of-the-Art Survey1
A data-centric chip design agent framework for Verilog code generation1
STCO: Enhancing Training Efficiency via Structured Sparse Tensor Compilation Optimization1
A Case for Precise, Fine-Grained Pointer Synthesis in High-Level Synthesis1
ZeroD-fender: A Resource-aware IoT Malware Detection Engine via Fine-grained Side-channel Analysis1
Introduction to the Special Issue on Approximate Systems1
A Novel Approach to Reducing Testing Costs and Minimizing Defect Escapes Using Dynamic Neighborhood Range and Shapley Values1
HNM-CIM: An Algorithm-Hardware Co-designed SRAM-based CIM for Transformer Acceleration Exploiting Hybrid N:M Sparsity1
Voltage-Based Covert Channels Using FPGAs1
HLS-IRT: Hardware Trojan Insertion through Modification of Intermediate Representation During High-Level Synthesis1
H3D-Transformer: A Heterogeneous 3D (H3D) Computing Platform for Transformer Model Acceleration on Edge Devices1
Test Point Insertion for Multi-Cycle Power-On Self-Test1
A Framework for Validation of Synthesized MicroElectrode Dot Array Actuations for Digital Microfluidic Biochips1
Routability-driven Power/Ground Network Optimization Based on Machine Learning1
HyperPlace: Harnessing a Large Language Model for Efficient Hyperparameter Optimization in GPU-Accelerated VLSI Placement1
Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks1
An Efficient Method of DRC Violation Prediction with a Serial Deep Learning Model1
WCPNet: Jointly Predicting Wirelength, Congestion and Power for FPGA Using Multi-Task Learning1
Data Pruning-enabled High Performance and Reliable Graph Neural Network Training on ReRAM-based Processing-in-Memory Accelerators1
FixRTL: Auto-correction of Multiple RTL Bugs by a New Feature Burst Clustering Algorithm and Mutation1
CRM_BF:A Low-Overhead, High-Efficient and Reconfigurable Operation Unit Design Approach Using the Customized Reed-Muller Unit For Boolean Functions of Sequence Cipher Algorithms1
Global Placement Exploiting Soft 2D Regularity1
A Native SPICE Implementation of Memristor Models for Simulation of Neuromorphic Analog Signal Processing Circuits1
Wages: The Worst Transistor Aging Analysis for Large-scale Analog Integrated Circuits via Domain Generalization1
Hierarchical Scheduling of an SDF/L Graph onto Multiple Processors1
E2HRL: An Energy-efficient Hardware Accelerator for Hierarchical Deep Reinforcement Learning1
Magnetic Core TSV-Inductor Design and Optimization for On-chip DC-DC Converter1
Automatic Test Pattern Generation for Robust Quantum Circuit Testing1
SHAREDD: Sharing of Test Data and Design-for-Testability Logic for Transition Fault Tests under Standard Scan1
Fault Injection Attack Emulation Framework for Early Evaluation of IC Designs1
CmpCNN: CMP Modeling with Transfer Learning CNN Architecture1
Multi-target Fluid Mixing in MEDA Biochips: Theory and an Attempt toward Waste Minimization1
Accelerating Deformable Convolution Networks with Dynamic and Irregular Memory Accesses1
Enhancing the Effectiveness of STLs for GPUs via Bounded Model Checking1
Flip : Data-centric Edge CGRA Accelerator1
Enable Deep Learning on Mobile Devices: Methods, Systems, and Applications1
EasyMRC: Efficient Mask Rule Checking via Representative Edge Sampling1
A Bridge-based Algorithm for Simultaneous Primal and Dual Defects Compression on Topologically Quantum-error-corrected Circuits1
Automatic Correction of Arithmetic Circuits in the Presence of Multiple Bugs by Groebner Basis Modification1
Energy-Constrained Scheduling for Weakly Hard Real-Time Systems Using Standby-Sparing1
ProtFe: Low-Cost Secure Power Side-Channel Protection for General and Custom FeFET-Based Memories1
HDLdebugger: Streamlining HDL debugging with Large Language Models1
Survey of Machine Learning for Software-assisted Hardware Design Verification: Past, Present, and Prospect1
SIMTAM: Generation Diversity Test Programs for FPGA Simulation Tools Testing Via Timing Area Mutation1
Toward a Human-Readable State Machine Extraction1
Design Flow and Methodology for Dynamic and Static Energy-constrained Scheduling Framework in Heterogeneous Multicore Embedded Devices1
LithoExp: Explainable Two-stage CNN-based Lithographic Hotspot Detection with Layout Defect Localization1
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