ACM Transactions on Design Automation of Electronic Systems

Papers
(The median citation count of ACM Transactions on Design Automation of Electronic Systems is 1. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-04-01 to 2024-04-01.)
ArticleCitations
Machine Learning for Electronic Design Automation: A Survey105
Enable Deep Learning on Mobile Devices: Methods, Systems, and Applications44
Security Assessment of Dynamically Obfuscated Scan Chain Against Oracle-guided Attacks28
AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators24
Reconfigurable Network-on-Chip Security Architecture19
An Energy-aware Online Learning Framework for Resource Management in Heterogeneous Platforms19
TAAL18
Adversarial Perturbation Attacks on ML-based CAD17
SCRIPT17
MaxSense16
Modular Neural Networks for Low-Power Image Classification on Embedded Devices14
A Comprehensive Survey of Attacks without Physical Access Targeting Hardware Vulnerabilities in IoT/IIoT Devices, and Their Detection Mechanisms13
High-Level Synthesis of Key-Obfuscated RTL IP with Design Lockout and Camouflaging13
EF-Train: Enable Efficient On-device CNN Training on FPGA through Data Reshaping for Online Adaptation or Personalization12
FTT-NAS: Discovering Fault-tolerant Convolutional Neural Architecture11
CeMux: Maximizing the Accuracy of Stochastic Mux Adders and an Application to Filter Design11
Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design11
A Robust Modulus-Based Matrix Splitting Iteration Method for Mixed-Cell-Height Circuit Legalization10
Directed Test Generation for Activation of Security Assertions in RTL Models10
Voltage-Based Covert Channels Using FPGAs10
PREASC10
Core Placement Optimization for Multi-chip Many-core Neural Network Systems with Reinforcement Learning10
Machine Learning Assisted PUF Calibration for Trustworthy Proof of Sensor Data in IoT10
A Survey on Security of Digital Microfluidic Biochips: Technology, Attack, and Defense10
A Hierarchical HVAC Control Scheme for Energy-aware Smart Building Automation10
Strong Logic Obfuscation with Low Overhead against IC Reverse Engineering Attacks10
MNFTL9
Algorithmic Fault Detection for RRAM-based Matrix Operations9
Runtime Identification of Hardware Trojans by Feature Analysis on Gate-Level Unstructured Data and Anomaly Detection8
NoC Application Mapping Optimization Using Reinforcement Learning8
High-Level Synthesis Implementation of an Embedded Real-Time HEVC Intra Encoder on FPGA for Media Applications7
MeF-RAM: A New Non-Volatile Cache Memory Based on Magneto-Electric FET7
Machine Learning Approach for Fast Electromigration Aware Aging Prediction in Incremental Design of Large Scale On-chip Power Grid Network7
Machine Learning for Congestion Management and Routability Prediction within FPGA Placement7
Security Threat Analyses and Attack Models for Approximate Computing Systems7
Towards Smarter Diagnosis7
TransNet7
FUBOCO: Structure Synthesis of Basic Op-Amps by FUnctional BlOck COmposition7
A Deterministic-Path Routing Algorithm for Tolerating Many Faults on Very-Large-Scale Network-on-Chip6
NeuPow6
A Tensor Network based Decision Diagram for Representation of Quantum Circuits6
Design Flow and Methodology for Dynamic and Static Energy-constrained Scheduling Framework in Heterogeneous Multicore Embedded Devices6
HeM3D6
Graph Neural Networks for High-Level Synthesis Design Space Exploration6
Learning from the Past: Efficient High-level Synthesis Design Space Exploration for FPGAs6
Implementation, Characterization and Application of Path Changing Switch based Arbiter PUF on FPGA as a lightweight Security Primitive for IoT6
A Module-Linking Graph Assisted Hybrid Optimization Framework for Custom Analog and Mixed-Signal Circuit Parameter Synthesis6
Mitigating Negative Impacts of Read Disturb in SSDs5
ESPSim: An Efficient Scalable Power Grid Simulator Based on Parallel Algebraic Multigrid5
High-throughput Near-Memory Processing on CNNs with 3D HBM-like Memory5
A Comprehensive Survey on Electronic Design Automation and Graph Neural Networks: Theory and Applications5
Security of Microfluidic Biochip5
Predicting Memory Compiler Performance Outputs Using Feed-forward Neural Networks5
Dataflow Model–based Software Synthesis Framework for Parallel and Distributed Embedded Systems5
Quantum Circuit Transformation: A Monte Carlo Tree Search Framework5
Magnetic Core TSV-Inductor Design and Optimization for On-chip DC-DC Converter4
Machine Learning Approaches for Efficient Design Space Exploration of Application-Specific NoCs4
A Runtime Reconfigurable Design of Compute-in-Memory–Based Hardware Accelerator for Deep Learning Inference4
Design Space Optimization of Shared Memory Architecture in Accelerator-rich Systems4
A Survey and Perspective on Artificial Intelligence for Security-Aware Electronic Design Automation4
A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits4
Efficient Layout Hotspot Detection via Neural Architecture Search4
Multi-Fidelity Surrogate-Based Optimization for Electromagnetic Simulation Acceleration4
Sherlock: A Multi-Objective Design Space Exploration Framework4
Architectural Design of Flow-Based Microfluidic Biochips for Multi-Target Dilution of Biochemical Fluids4
Machine Learning-based Defect Coverage Boosting of Analog Circuits under Measurement Variations4
RASCv2: Enabling Remote Access to Side-Channels for Mission Critical and IoT Systems4
SwitchX : Gmin-Gmax Switching for Energy-efficient and Robust Implementation of Binarized Neural Networks on ReRAM Xbars4
Fine-grained Adaptive Testing Based on Quality Prediction4
Robust Multi-Target Sample Preparation on MEDA Biochips Obviating Waste Production4
FastCFI: Real-time Control-Flow Integrity Using FPGA without Code Instrumentation3
COPE3
Leveraging Automatic High-Level Synthesis Resource Sharing to Maximize Dynamical Voltage Overscaling with Error Control3
Energy-Efficient GPU L2 Cache Design Using Instruction-Level Data Locality Similarity3
Toward Taming the Overhead Monster for Data-flow Integrity3
Synthesizing Brain-network-inspired Interconnections for Large-scale Network-on-chips3
Software/Hardware Co-design of 3D NoC-based GPU Architectures for Accelerated Graph Computations3
A Native SPICE Implementation of Memristor Models for Simulation of Neuromorphic Analog Signal Processing Circuits3
Wire Load Oriented Analog Routing with Matching Constraints3
Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration3
Distance-aware Approximate Nanophotonic Interconnect3
Automatic Mapping of the Best-Suited DNN Pruning Schemes for Real-Time Mobile Acceleration3
Machine Learning for Statistical Modeling3
A Compact High-Dimensional Yield Analysis Method using Low-Rank Tensor Approximation2
Test Point Insertion for Multi-Cycle Power-On Self-Test2
Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems2
A Switching NMOS Based Single Ended Sense Amplifier for High Density SRAM Applications2
Energy-Efficient LSTM Inference Accelerator for Real-Time Causal Prediction2
Fault-based Built-in Self-test and Evaluation of Phase Locked Loops2
Multi-objective Optimization of Mapping Dataflow Applications to MPSoCs Using a Hybrid Evaluation Combining Analytic Models and Measurements2
A Dynamic Huffman Coding Method for Reliable TLC NAND Flash Memory2
MEDUSA: A Multi-Resolution Machine Learning Congestion Estimation Method for 2D and 3D Global Routing2
QuadSeal: Quadruple Balancing to Mitigate Power Analysis Attacks with Variability Effects and Electromagnetic Fault Injection Attacks2
A Design Methodology for Energy-Aware Processing in Unmanned Aerial Vehicles2
TMDS: Temperature-aware Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems2
Auto-tuning Fixed-point Precision with TVM on RISC-V Packed SIMD Extension2
Learning-based Phase-aware Multi-core CPU Workload Forecasting2
A Delay-Adjustable, Self-Testable Flip-Flop for Soft-Error Tolerability and Delay-Fault Testability2
Demand-Driven Multi-Target Sample Preparation on Resource-Constrained Digital Microfluidic Biochips2
CRP2.0: A Fast and Robust Cooperation between Routing and Placement in Advanced Technology Nodes2
Rescuing ReRAM-based Neural Computing Systems from Device Variation2
Placement of Digital Microfluidic Biochips via a New Evolutionary Algorithm2
Ax-BxP: Approximate Blocked Computation for Precision-reconfigurable Deep Neural Network Acceleration2
A Learning-based Methodology for Scenario-aware Mapping of Soft Real-time Applications onto Heterogeneous MPSoCs2
FPGAPRO: A Defense Framework Against Crosstalk-Induced Secret Leakage in FPGA2
Ising-FPGA2
Degraded Mode-benefited I/O Scheduling to Ensure I/O Responsiveness in RAID-enabled SSDs2
ECO-GNN: Signoff Power Prediction Using Graph Neural Networks with Subgraph Approximation2
Improving FPGA-Based Logic Emulation Systems through Machine Learning2
Soft-HaT2
Leakage-Aware Dynamic Thermal Management of 3D Memories2
Efficient Parasitic-aware g m / I D - 2
Security of Electrical, Optical, and Wireless On-chip Interconnects: A Survey2
FaultDroid2
Towards LDPC Read Performance of 3D Flash Memories with Layer-induced Error Characteristics2
A Locality Optimizer for Loop-dominated Applications Based on Reuse Distance Analysis2
SecureTVM: A TVM-based Compiler Framework for Selective Privacy-preserving Neural Inference2
Logic Diagnosis with Hybrid Fail Data2
Performance-driven Wire Sizing for Analog Integrated Circuits2
Design Automation for Tree-based Nearest Neighborhood–aware Placement of High-speed Cellular Automata on FPGA with Scan Path Insertion2
Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements2
SmartDR1
Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks1
Optimal Pattern Retargeting in IEEE 1687 Networks: A SAT-based Upper-Bound Computation1
A Problem-tailored Adversarial Deep Neural Network-Based Attack Model for Feed-Forward Physical Unclonable Functions1
Memory-Throughput Trade-off for CNN-Based Applications at the Edge1
Thermal Management for FPGA Nodes in HPC Systems1
Plasticine: A Cross-layer Approximation Methodology for Multi-kernel Applications through Minimally Biased, High-throughput, and Energy-efficient SIMD Soft Multiplier-divider1
A Reconfigurable 7T SRAM Bit Cell for High Speed, Power Saving and Low Voltage Application1
DRAGON: Dynamic Recurrent Accelerator for Graph Online Convolution1
A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts1
Uncertainty-aware Energy Harvest Prediction and Management for IoT Devices1
Low-energy Pipelined Hardware Design for Approximate Medium Filter1
Generating Representative Test Sequences from Real Workload for Minimizing DRAM Verification Overhead1
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration1
GANDSE: Generative Adversarial Network-based Design Space Exploration for Neural Network Accelerator Design1
On-chip ESD Protection Design Methodologies by CAD Simulation1
Hardware-aware Quantization/Mapping Strategies for Compute-in-Memory Accelerators1
Inferencing on Edge Devices: A Time- and Space-aware Co-scheduling Approach1
A Conditionally Chaotic Physically Unclonable Function Design Framework with High Reliability1
Approximate Learning and Fault-Tolerant Mapping for Energy-Efficient Neuromorphic Systems1
An Adaptive Application Framework with Customizable Quality Metrics1
CBDC-PUF: A Novel Physical Unclonable Function Design Framework Utilizing Configurable Butterfly Delay Chain Against Modeling Attack1
A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route1
Multiterminal Pathfinding in Practical VLSI Systems with Deep Neural Networks1
GraphPlanner: Floorplanning with Graph Neural Network1
E2HRL: An Energy-efficient Hardware Accelerator for Hierarchical Deep Reinforcement Learning1
VeriGen: A Large Language Model for Verilog Code Generation1
MVP: An Efficient CNN Accelerator with Matrix, Vector, and Processing-Near-Memory Units1
Component Fault Diagnosability of Hierarchical Cubic Networks1
Accuracy Configurable Adders with Negligible Delay Overhead in Exact Operating Mode1
An Energy-Efficient Inference Method in Convolutional Neural Networks Based on Dynamic Adjustment of the Pruning Level1
Structured Dynamic Precision for Deep Neural Networks Quantization1
Implication of Optimizing NPU Dataflows on Neural Architecture Search for Mobile Devices1
CNNFlow: Memory-driven Data Flow Optimization for Convolutional Neural Networks1
CNN-Cap: Effective Convolutional Neural Network-based Capacitance Models for Interconnect Capacitance Extraction1
A Symbolic Approach to Detecting Hardware Trojans Triggered by Don’t Care Transitions1
E 2 -VOR: An End-to-End En/Decoder Architecture for Efficient Video Object Recognition1
A Low-Overhead and High-Security Cryptographic Circuit Design Utilizing the TIGFET-Based Three-Phase Single-Rail Pulse Register against Side-Channel Attacks1
Machine-learning-driven Architectural Selection of Adders and Multipliers in Logic Synthesis1
An Efficient Ring Oscillator PUF Using Programmable Delay Units on FPGA1
A Low-power Programmable Machine Learning Hardware Accelerator Design for Intelligent Edge Devices1
Uncertainty Theory Based Partitioning for Cyber-Physical Systems with Uncertain Reliability Analysis1
MOEA/D vs. NSGA-II: A Comprehensive Comparison for Multi/Many Objective Analog/RF Circuit Optimization through a Generic Benchmark1
Automatic Synthesis of FSMs for Enforcing Non-functional Requirements on MPSoCs Using Multi-objective Evolutionary Algorithms1
Energy Efficient Boosting of GEMM Accelerators for DNN via Reuse1
A Framework for Validation of Synthesized MicroElectrode Dot Array Actuations for Digital Microfluidic Biochips1
NPU-Accelerated Imitation Learning for Thermal Optimization of QoS-Constrained Heterogeneous Multi-Cores1
Self Adaptive Logical Split Cache Techniques for Delayed Aging of NVM LLC1
Toward a Human-Readable State Machine Extraction1
BoA-PTA: A Bayesian Optimization Accelerated PTA Solver for SPICE Simulation1
Harmonic Estimation and Comparative Analysis of Ultra-High Speed Flip-Flop and Latch Topologies for Low Power and High Performance Future Generation Micro-/Nano Electronic Systems1
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