ACM Transactions on Design Automation of Electronic Systems

Article	Citations
Machine Learning for Electronic Design Automation: A Survey	100
Enable Deep Learning on Mobile Devices: Methods, Systems, and Applications	39
Security Assessment of Dynamically Obfuscated Scan Chain Against Oracle-guided Attacks	27
AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators	20
An Energy-aware Online Learning Framework for Resource Management in Heterogeneous Platforms	19
Reconfigurable Network-on-Chip Security Architecture	19
TAAL	18
SCRIPT	16
Adversarial Perturbation Attacks on ML-based CAD	16
MaxSense	16
Modular Neural Networks for Low-Power Image Classification on Embedded Devices	14
High-Level Synthesis of Key-Obfuscated RTL IP with Design Lockout and Camouflaging	13
A Comprehensive Survey of Attacks without Physical Access Targeting Hardware Vulnerabilities in IoT/IIoT Devices, and Their Detection Mechanisms	12
EF-Train: Enable Efficient On-device CNN Training on FPGA through Data Reshaping for Online Adaptation or Personalization	11
Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design	11
Strong Logic Obfuscation with Low Overhead against IC Reverse Engineering Attacks	10
Core Placement Optimization for Multi-chip Many-core Neural Network Systems with Reinforcement Learning	10
Machine Learning Assisted PUF Calibration for Trustworthy Proof of Sensor Data in IoT	10
PREASC	10
FTT-NAS: Discovering Fault-tolerant Convolutional Neural Architecture	10
Voltage-Based Covert Channels Using FPGAs	10
A Hierarchical HVAC Control Scheme for Energy-aware Smart Building Automation	10
Algorithmic Fault Detection for RRAM-based Matrix Operations	9
A Robust Modulus-Based Matrix Splitting Iteration Method for Mixed-Cell-Height Circuit Legalization	9
MNFTL	8

Directed Test Generation for Activation of Security Assertions in RTL Models	8
Runtime Identification of Hardware Trojans by Feature Analysis on Gate-Level Unstructured Data and Anomaly Detection	8
CeMux: Maximizing the Accuracy of Stochastic Mux Adders and an Application to Filter Design	8
A Survey on Security of Digital Microfluidic Biochips: Technology, Attack, and Defense	8
High-Level Synthesis Implementation of an Embedded Real-Time HEVC Intra Encoder on FPGA for Media Applications	7
Machine Learning for Congestion Management and Routability Prediction within FPGA Placement	7
FUBOCO: Structure Synthesis of Basic Op-Amps by FUnctional BlOck COmposition	7
TransNet	7
MeF-RAM: A New Non-Volatile Cache Memory Based on Magneto-Electric FET	7
Machine Learning Approach for Fast Electromigration Aware Aging Prediction in Incremental Design of Large Scale On-chip Power Grid Network	7
NoC Application Mapping Optimization Using Reinforcement Learning	7
Security Threat Analyses and Attack Models for Approximate Computing Systems	7
Design Flow and Methodology for Dynamic and Static Energy-constrained Scheduling Framework in Heterogeneous Multicore Embedded Devices	6
NeuPow	6
How Secure Is Split Manufacturing in Preventing Hardware Trojan?	6
A Deterministic-Path Routing Algorithm for Tolerating Many Faults on Very-Large-Scale Network-on-Chip	6
HeM3D	6
A Module-Linking Graph Assisted Hybrid Optimization Framework for Custom Analog and Mixed-Signal Circuit Parameter Synthesis	6
Learning from the Past: Efficient High-level Synthesis Design Space Exploration for FPGAs	6
A Tensor Network based Decision Diagram for Representation of Quantum Circuits	6
Towards Smarter Diagnosis	6
Dataflow Model–based Software Synthesis Framework for Parallel and Distributed Embedded Systems	5
Implementation, Characterization and Application of Path Changing Switch based Arbiter PUF on FPGA as a lightweight Security Primitive for IoT	5
Mitigating Negative Impacts of Read Disturb in SSDs	5
Quantum Circuit Transformation: A Monte Carlo Tree Search Framework	5
Fine-grained Adaptive Testing Based on Quality Prediction	4
Graph Neural Networks for High-Level Synthesis Design Space Exploration	4
A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits	4
Machine Learning-based Defect Coverage Boosting of Analog Circuits under Measurement Variations	4
RASCv2: Enabling Remote Access to Side-Channels for Mission Critical and IoT Systems	4
A Runtime Reconfigurable Design of Compute-in-Memory–Based Hardware Accelerator for Deep Learning Inference	4
Design Space Optimization of Shared Memory Architecture in Accelerator-rich Systems	4
Architectural Design of Flow-Based Microfluidic Biochips for Multi-Target Dilution of Biochemical Fluids	4
Security of Microfluidic Biochip	4
Magnetic Core TSV-Inductor Design and Optimization for On-chip DC-DC Converter	4
Predicting Memory Compiler Performance Outputs Using Feed-forward Neural Networks	4
Efficient Layout Hotspot Detection via Neural Architecture Search	4
Multi-Fidelity Surrogate-Based Optimization for Electromagnetic Simulation Acceleration	4
Sherlock: A Multi-Objective Design Space Exploration Framework	4
Robust Multi-Target Sample Preparation on MEDA Biochips Obviating Waste Production	4
High-throughput Near-Memory Processing on CNNs with 3D HBM-like Memory	4
Machine Learning Approaches for Efficient Design Space Exploration of Application-Specific NoCs	4
ESPSim: An Efficient Scalable Power Grid Simulator Based on Parallel Algebraic Multigrid	4
SwitchX : Gmin-Gmax Switching for Energy-efficient and Robust Implementation of Binarized Neural Networks on ReRAM Xbars	4
Wire Load Oriented Analog Routing with Matching Constraints	3
Toward Taming the Overhead Monster for Data-flow Integrity	3
Distance-aware Approximate Nanophotonic Interconnect	3
Automatic Mapping of the Best-Suited DNN Pruning Schemes for Real-Time Mobile Acceleration	3
Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration	3
A Comprehensive Survey on Electronic Design Automation and Graph Neural Networks: Theory and Applications	3

Software/Hardware Co-design of 3D NoC-based GPU Architectures for Accelerated Graph Computations	3
A Native SPICE Implementation of Memristor Models for Simulation of Neuromorphic Analog Signal Processing Circuits	3
FastCFI: Real-time Control-Flow Integrity Using FPGA without Code Instrumentation	3
COPE	3
Leveraging Automatic High-Level Synthesis Resource Sharing to Maximize Dynamical Voltage Overscaling with Error Control	3
Energy-Efficient GPU L2 Cache Design Using Instruction-Level Data Locality Similarity	3
Machine Learning for Statistical Modeling	3
Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems	2
Improving FPGA-Based Logic Emulation Systems through Machine Learning	2
Rescuing ReRAM-based Neural Computing Systems from Device Variation	2
A Switching NMOS Based Single Ended Sense Amplifier for High Density SRAM Applications	2
FaultDroid	2
A Locality Optimizer for Loop-dominated Applications Based on Reuse Distance Analysis	2
SecureTVM: A TVM-based Compiler Framework for Selective Privacy-preserving Neural Inference	2
Synthesizing Brain-network-inspired Interconnections for Large-scale Network-on-chips	2
A Design Methodology for Energy-Aware Processing in Unmanned Aerial Vehicles	2
A Delay-Adjustable, Self-Testable Flip-Flop for Soft-Error Tolerability and Delay-Fault Testability	2
CRP2.0: A Fast and Robust Cooperation between Routing and Placement in Advanced Technology Nodes	2
Learning-based Phase-aware Multi-core CPU Workload Forecasting	2
Demand-Driven Multi-Target Sample Preparation on Resource-Constrained Digital Microfluidic Biochips	2
Energy-Efficient LSTM Inference Accelerator for Real-Time Causal Prediction	2
Fault-based Built-in Self-test and Evaluation of Phase Locked Loops	2
A Dynamic Huffman Coding Method for Reliable TLC NAND Flash Memory	2
Ising-FPGA	2
Degraded Mode-benefited I/O Scheduling to Ensure I/O Responsiveness in RAID-enabled SSDs	2
QuadSeal: Quadruple Balancing to Mitigate Power Analysis Attacks with Variability Effects and Electromagnetic Fault Injection Attacks	2
Leakage-Aware Dynamic Thermal Management of 3D Memories	2
A Survey and Perspective on Artificial Intelligence for Security-Aware Electronic Design Automation	2
Efficient Parasitic-aware g m / I D -	2
Placement of Digital Microfluidic Biochips via a New Evolutionary Algorithm	2
Ax-BxP: Approximate Blocked Computation for Precision-reconfigurable Deep Neural Network Acceleration	2
FPGAPRO: A Defense Framework Against Crosstalk-Induced Secret Leakage in FPGA	2
MEDUSA: A Multi-Resolution Machine Learning Congestion Estimation Method for 2D and 3D Global Routing	2
Logic Diagnosis with Hybrid Fail Data	2
Soft-HaT	2
A Symbolic Approach to Detecting Hardware Trojans Triggered by Don’t Care Transitions	1
Design Automation for Tree-based Nearest Neighborhood–aware Placement of High-speed Cellular Automata on FPGA with Scan Path Insertion	1
A Learning-based Methodology for Scenario-aware Mapping of Soft Real-time Applications onto Heterogeneous MPSoCs	1
Memory-Throughput Trade-off for CNN-Based Applications at the Edge	1
Thermal Management for FPGA Nodes in HPC Systems	1
Plasticine: A Cross-layer Approximation Methodology for Multi-kernel Applications through Minimally Biased, High-throughput, and Energy-efficient SIMD Soft Multiplier-divider	1
GraphPlanner: Floorplanning with Graph Neural Network	1
Low-energy Pipelined Hardware Design for Approximate Medium Filter	1
Accuracy Configurable Adders with Negligible Delay Overhead in Exact Operating Mode	1
Implication of Optimizing NPU Dataflows on Neural Architecture Search for Mobile Devices	1
E2HRL: An Energy-efficient Hardware Accelerator for Hierarchical Deep Reinforcement Learning	1
Auto-tuning Fixed-point Precision with TVM on RISC-V Packed SIMD Extension	1
A Framework for Validation of Synthesized MicroElectrode Dot Array Actuations for Digital Microfluidic Biochips	1
Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements	1
SmartDR	1
E 2 -VOR: An End-to-End En/Decoder Architecture for Efficient Video Object Recognition	1
Optimal Pattern Retargeting in IEEE 1687 Networks: A SAT-based Upper-Bound Computation	1
Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks	1
Multi-objective Optimization of Mapping Dataflow Applications to MPSoCs Using a Hybrid Evaluation Combining Analytic Models and Measurements	1
CBDC-PUF: A Novel Physical Unclonable Function Design Framework Utilizing Configurable Butterfly Delay Chain Against Modeling Attack	1
A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route	1
Multiterminal Pathfinding in Practical VLSI Systems with Deep Neural Networks	1
A Reconfigurable 7T SRAM Bit Cell for High Speed, Power Saving and Low Voltage Application	1
Toward a Human-Readable State Machine Extraction	1
MVP: An Efficient CNN Accelerator with Matrix, Vector, and Processing-Near-Memory Units	1
An Energy-Efficient Inference Method in Convolutional Neural Networks Based on Dynamic Adjustment of the Pruning Level	1
Generating Representative Test Sequences from Real Workload for Minimizing DRAM Verification Overhead	1
Test Point Insertion for Multi-Cycle Power-On Self-Test	1
DRAGON: Dynamic Recurrent Accelerator for Graph Online Convolution	1
Harmonic Estimation and Comparative Analysis of Ultra-High Speed Flip-Flop and Latch Topologies for Low Power and High Performance Future Generation Micro-/Nano Electronic Systems	1
A Conditionally Chaotic Physically Unclonable Function Design Framework with High Reliability	1
Approximate Learning and Fault-Tolerant Mapping for Energy-Efficient Neuromorphic Systems	1
An Adaptive Application Framework with Customizable Quality Metrics	1
A Compact High-Dimensional Yield Analysis Method using Low-Rank Tensor Approximation	1
A Low-Overhead and High-Security Cryptographic Circuit Design Utilizing the TIGFET-Based Three-Phase Single-Rail Pulse Register against Side-Channel Attacks	1
Machine-learning-driven Architectural Selection of Adders and Multipliers in Logic Synthesis	1
An Efficient Ring Oscillator PUF Using Programmable Delay Units on FPGA	1
MOEA/D vs. NSGA-II: A Comprehensive Comparison for Multi/Many Objective Analog/RF Circuit Optimization through a Generic Benchmark	1
Energy Efficient Boosting of GEMM Accelerators for DNN via Reuse	1
Automatic Synthesis of FSMs for Enforcing Non-functional Requirements on MPSoCs Using Multi-objective Evolutionary Algorithms	1
On-chip ESD Protection Design Methodologies by CAD Simulation	1
Uncertainty-aware Energy Harvest Prediction and Management for IoT Devices	1
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration	1
GANDSE: Generative Adversarial Network-based Design Space Exploration for Neural Network Accelerator Design	1
ECO-GNN: Signoff Power Prediction Using Graph Neural Networks with Subgraph Approximation	1

Security of Electrical, Optical, and Wireless On-chip Interconnects: A Survey	1
A Problem-tailored Adversarial Deep Neural Network-Based Attack Model for Feed-Forward Physical Unclonable Functions	1