ACM Transactions on Design Automation of Electronic Systems

Article	Citations
Machine Learning for Electronic Design Automation: A Survey	136
Enable Deep Learning on Mobile Devices: Methods, Systems, and Applications	51
Security Assessment of Dynamically Obfuscated Scan Chain Against Oracle-guided Attacks	33
AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators	31
TAAL	21
MaxSense	19
A Survey on Security of Digital Microfluidic Biochips: Technology, Attack, and Defense	18
VeriGen: A Large Language Model for Verilog Code Generation	16
A Comprehensive Survey of Attacks without Physical Access Targeting Hardware Vulnerabilities in IoT/IIoT Devices, and Their Detection Mechanisms	15
EF-Train: Enable Efficient On-device CNN Training on FPGA through Data Reshaping for Online Adaptation or Personalization	14
CeMux: Maximizing the Accuracy of Stochastic Mux Adders and an Application to Filter Design	13
FTT-NAS: Discovering Fault-tolerant Convolutional Neural Architecture	13
Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design	12
A Tensor Network based Decision Diagram for Representation of Quantum Circuits	12
Voltage-Based Covert Channels Using FPGAs	12
A Robust Modulus-Based Matrix Splitting Iteration Method for Mixed-Cell-Height Circuit Legalization	12
Directed Test Generation for Activation of Security Assertions in RTL Models	11
A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits	11
High-Level Synthesis Implementation of an Embedded Real-Time HEVC Intra Encoder on FPGA for Media Applications	10
NoC Application Mapping Optimization Using Reinforcement Learning	10
A Comprehensive Survey on Electronic Design Automation and Graph Neural Networks: Theory and Applications	9
ESPSim: An Efficient Scalable Power Grid Simulator Based on Parallel Algebraic Multigrid	9
MeF-RAM: A New Non-Volatile Cache Memory Based on Magneto-Electric FET	9
Security Threat Analyses and Attack Models for Approximate Computing Systems	9
Implementation, Characterization and Application of Path Changing Switch based Arbiter PUF on FPGA as a lightweight Security Primitive for IoT	8

Graph Neural Networks for High-Level Synthesis Design Space Exploration	8
FastCFI: Real-time Control-Flow Integrity Using FPGA without Code Instrumentation	7
HeM3D	7
FUBOCO: Structure Synthesis of Basic Op-Amps by FUnctional BlOck COmposition	7
Learning from the Past: Efficient High-level Synthesis Design Space Exploration for FPGAs	7
Dataflow Model–based Software Synthesis Framework for Parallel and Distributed Embedded Systems	7
A Module-Linking Graph Assisted Hybrid Optimization Framework for Custom Analog and Mixed-Signal Circuit Parameter Synthesis	7
Design Flow and Methodology for Dynamic and Static Energy-constrained Scheduling Framework in Heterogeneous Multicore Embedded Devices	7
RASCv2: Enabling Remote Access to Side-Channels for Mission Critical and IoT Systems	7
Sherlock: A Multi-Objective Design Space Exploration Framework	7
A Survey and Perspective on Artificial Intelligence for Security-Aware Electronic Design Automation	7
Security of Electrical, Optical, and Wireless On-chip Interconnects: A Survey	6
Auto-tuning Fixed-point Precision with TVM on RISC-V Packed SIMD Extension	6
A Runtime Reconfigurable Design of Compute-in-Memory–Based Hardware Accelerator for Deep Learning Inference	6
Quantum Circuit Transformation: A Monte Carlo Tree Search Framework	6
High-throughput Near-Memory Processing on CNNs with 3D HBM-like Memory	6
SwitchX: Gmin-Gmax Switching for Energy-efficient and Robust Implementation of Binarized Neural Networks on ReRAM Xbars	6
Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration	5
CNN-Cap: Effective Convolutional Neural Network-based Capacitance Models for Interconnect Capacitance Extraction	5
Hardware Security Risks and Threat Analyses in Advanced Manufacturing Industry	5
Efficient Layout Hotspot Detection via Neural Architecture Search	5
A Native SPICE Implementation of Memristor Models for Simulation of Neuromorphic Analog Signal Processing Circuits	5
Fault-based Built-in Self-test and Evaluation of Phase Locked Loops	5
MOEA/D vs. NSGA-II: A Comprehensive Comparison for Multi/Many Objective Analog/RF Circuit Optimization through a Generic Benchmark	5
Ax-BxP: Approximate Blocked Computation for Precision-reconfigurable Deep Neural Network Acceleration	4
Software/Hardware Co-design of 3D NoC-based GPU Architectures for Accelerated Graph Computations	4
Design Space Optimization of Shared Memory Architecture in Accelerator-rich Systems	4
Deep Reinforcement Learning-based Mining Task Offloading Scheme for Intelligent Connected Vehicles in UAV-aided MEC	4
A Compact TRNG Design for FPGA Based on the Metastability of RO-driven Shift Registers	4
DDAM: D ata D istribution- A ware M apping of CNNs on Processing-In-Memory S	4
DeepFlow: A Cross-Stack Pathfinding Framework for Distributed AI Systems	4
A Compact High-Dimensional Yield Analysis Method using Low-Rank Tensor Approximation	4
Magnetic Core TSV-Inductor Design and Optimization for On-chip DC-DC Converter	4
A Learning-based Methodology for Scenario-aware Mapping of Soft Real-time Applications onto Heterogeneous MPSoCs	4
A Design Methodology for Energy-Aware Processing in Unmanned Aerial Vehicles	4
Test Point Insertion for Multi-Cycle Power-On Self-Test	4
Heterogeneous Integration Supply Chain Integrity Through Blockchain and CHSM	4
Energy-Efficient LSTM Inference Accelerator for Real-Time Causal Prediction	3
Energy Efficient Boosting of GEMM Accelerators for DNN via Reuse	3
Distance-aware Approximate Nanophotonic Interconnect	3
Leveraging Automatic High-Level Synthesis Resource Sharing to Maximize Dynamical Voltage Overscaling with Error Control	3
CRP2.0: A Fast and Robust Cooperation between Routing and Placement in Advanced Technology Nodes	3
Automatic Mapping of the Best-Suited DNN Pruning Schemes for Real-Time Mobile Acceleration	3
TMDS: Temperature-aware Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems	3
COPE	3
TROP: TRust-aware OPportunistic Routing in NoC with Hardware Trojans	3
Multiterminal Pathfinding in Practical VLSI Systems with Deep Neural Networks	3
MVP: An Efficient CNN Accelerator with Matrix, Vector, and Processing-Near-Memory Units	3
SecureTVM: A TVM-based Compiler Framework for Selective Privacy-preserving Neural Inference	3
Toward Taming the Overhead Monster for Data-flow Integrity	3

A Low-power Programmable Machine Learning Hardware Accelerator Design for Intelligent Edge Devices	3
Accelerating Graph Computations on 3D NoC-Enabled PIM Architectures	3
Multi-Objective Optimization for Safety-Related Available E/E Architectures Scoping Highly Automated Driving Vehicles	3
Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements	3
On-chip ESD Protection Design Methodologies by CAD Simulation	3
Machine Learning for Statistical Modeling	3
Multi-objective Optimization of Mapping Dataflow Applications to MPSoCs Using a Hybrid Evaluation Combining Analytic Models and Measurements	3
NeuroCool: Dynamic Thermal Management of 3D DRAM for Deep Neural Networks through Customized Prefetching	3
A Dynamic Huffman Coding Method for Reliable TLC NAND Flash Memory	3
Demand-Driven Multi-Target Sample Preparation on Resource-Constrained Digital Microfluidic Biochips	3
CBDC-PUF: A Novel Physical Unclonable Function Design Framework Utilizing Configurable Butterfly Delay Chain Against Modeling Attack	3
Placement of Digital Microfluidic Biochips via a New Evolutionary Algorithm	3
Synthesizing Brain-network-inspired Interconnections for Large-scale Network-on-chips	3
GraphPlanner: Floorplanning with Graph Neural Network	3
A Delay-Adjustable, Self-Testable Flip-Flop for Soft-Error Tolerability and Delay-Fault Testability	3
ECO-GNN: Signoff Power Prediction Using Graph Neural Networks with Subgraph Approximation	3
A High Throughput STR-based TRNG by Jitter Precise Quantization Superposing	3
A Symbolic Approach to Detecting Hardware Trojans Triggered by Don’t Care Transitions	3
A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route	3
A Switching NMOS Based Single Ended Sense Amplifier for High Density SRAM Applications	3
MEDUSA: A Multi-Resolution Machine Learning Congestion Estimation Method for 2D and 3D Global Routing	3
Hardware-aware Quantization/Mapping Strategies for Compute-in-Memory Accelerators	2
DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs	2
FPGAPRO: A Defense Framework Against Crosstalk-Induced Secret Leakage in FPGA	2
Modified Decoupled Sense Amplifier with Improved Sensing Speed for Low-Voltage Differential SRAM	2
Degraded Mode-benefited I/O Scheduling to Ensure I/O Responsiveness in RAID-enabled SSDs	2
NPU-Accelerated Imitation Learning for Thermal Optimization of QoS-Constrained Heterogeneous Multi-Cores	2
Toward a Human-Readable State Machine Extraction	2
A Mixed-Criticality Traffic Scheduler with Mitigating Congestion for CAN-to-TSN Gateway	2
H3D-Transformer: A Heterogeneous 3D (H3D) Computing Platform for Transformer Model Acceleration on Edge Devices	2
IDeSyDe: Systematic Design Space Exploration via Design Space Identification	2
RSPP: Restricted Static Pseudo-Partitioning for Mitigation of Cross-Core Covert Channel Attacks	2
Uncertainty-aware Energy Harvest Prediction and Management for IoT Devices	2
A Low-Overhead and High-Security Cryptographic Circuit Design Utilizing the TIGFET-Based Three-Phase Single-Rail Pulse Register against Side-Channel Attacks	2
Memory-Throughput Trade-off for CNN-Based Applications at the Edge	2
Towards LDPC Read Performance of 3D Flash Memories with Layer-induced Error Characteristics	2
Memristive-based Mixed-signal CGRA for Accelerating Deep Neural Network Inference	2
Performance-driven Wire Sizing for Analog Integrated Circuits	2
Implication of Optimizing NPU Dataflows on Neural Architecture Search for Mobile Devices	2
Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems	2
Design Automation for Tree-based Nearest Neighborhood–aware Placement of High-speed Cellular Automata on FPGA with Scan Path Insertion	2
Structured Dynamic Precision for Deep Neural Networks Quantization	2
Design of Enhanced Reversible 9T SRAM Design for the Reduction in Sub-threshold Leakage Current with14nm FinFET Technology	2
Rescuing ReRAM-based Neural Computing Systems from Device Variation	2
DRAGON: Dynamic Recurrent Accelerator for Graph Online Convolution	2
An Efficient Ring Oscillator PUF Using Programmable Delay Units on FPGA	2
Machine-learning-driven Architectural Selection of Adders and Multipliers in Logic Synthesis	2
Plasticine: A Cross-layer Approximation Methodology for Multi-kernel Applications through Minimally Biased, High-throughput, and Energy-efficient SIMD Soft Multiplier-divider	2
QuadSeal: Quadruple Balancing to Mitigate Power Analysis Attacks with Variability Effects and Electromagnetic Fault Injection Attacks	2
Logic Diagnosis with Hybrid Fail Data	2
An Energy-Efficient Inference Method in Convolutional Neural Networks Based on Dynamic Adjustment of the Pruning Level	2
Worst-case Power Integrity Prediction Using Convolutional Neural Network	2
Test Compression for Launch-on-Capture Transition Fault Testing	2
Learning-based Phase-aware Multi-core CPU Workload Forecasting	2
E2HRL: An Energy-efficient Hardware Accelerator for Hierarchical Deep Reinforcement Learning	2
Approximate Learning and Fault-Tolerant Mapping for Energy-Efficient Neuromorphic Systems	2
Automatic Synthesis of FSMs for Enforcing Non-functional Requirements on MPSoCs Using Multi-objective Evolutionary Algorithms	2
Breaking the Design and Security Trade-off of Look-up-table–based Obfuscation	1
Uncertainty Theory Based Partitioning for Cyber-Physical Systems with Uncertain Reliability Analysis	1
Scalable and Accelerated Self-healing Control Circuit Using Evolvable Hardware	1
A Framework for Validation of Synthesized MicroElectrode Dot Array Actuations for Digital Microfluidic Biochips	1
A General Layout Pattern Clustering Using Geometric Matching-based Clip Relocation and Lower-bound Aided Optimization	1
Construction of All Multilayer Monolithic RSMTs and Its Application to Monolithic 3D IC Routing	1
Routability-driven Power/Ground Network Optimization Based on Machine Learning	1
Machine Learning Assisted Circuit Sizing Approach for Low-Voltage Analog Circuits with Efficient Variation-Aware Optimization	1
Component Fault Diagnosability of Hierarchical Cubic Networks	1
Optimizing VLIW Instruction Scheduling via a Two-Dimensional Constrained Dynamic Programming	1
Harmonic Estimation and Comparative Analysis of Ultra-High Speed Flip-Flop and Latch Topologies for Low Power and High Performance Future Generation Micro-/Nano Electronic Systems	1
Data Pruning-enabled High Performance and Reliable Graph Neural Network Training on ReRAM-based Processing-in-Memory Accelerators	1
Inferencing on Edge Devices: A Time- and Space-aware Co-scheduling Approach	1
An Adaptive Application Framework with Customizable Quality Metrics	1
A Problem-tailored Adversarial Deep Neural Network-Based Attack Model for Feed-Forward Physical Unclonable Functions	1
A PPA Study of Reinforced Placement Parameter Autotuning: Pseudo-3D vs. True-3D Placers	1
Optimal Model Partitioning with Low-Overhead Profiling on the PIM-based Platform for Deep Learning Inference	1
ARM-CO-UP: ARM COoperative Utilization of Processors	1
Application Mapping and Control-system Design for Microfluidic Biochips with Distributed Channel Storage	1
Accuracy Configurable Adders with Negligible Delay Overhead in Exact Operating Mode	1
A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts	1
Self Adaptive Logical Split Cache Techniques for Delayed Aging of NVM LLC	1
A Reliability-Aware Splitting Duty-Cycle Physical Unclonable Function Based on Trade-off Process, Voltage, and Temperature Variations	1

EPHA: An Energy-efficient Parallel Hybrid Architecture for ANNs and SNNs	1
A Brain-Inspired Hardware Architecture for Evolutionary Algorithms Based on Memristive Arrays	1
Dynamic Power Management in Large Manycore Systems: A Learning-to-Search Framework	1
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration	1
A Conditionally Chaotic Physically Unclonable Function Design Framework with High Reliability	1
Energy-Constrained Scheduling for Weakly Hard Real-Time Systems Using Standby-Sparing	1
Power Converter Circuit Design Automation Using Parallel Monte Carlo Tree Search	1
Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks	1
Virtuoso : Energy- and Latency-aware Streamlining of Streaming Videos on Systems-on-Chips	1
E 2 -VOR: An End-to-End En/Decoder Architecture for Efficient Video Object Recognition	1
Optimal Pattern Retargeting in IEEE 1687 Networks: A SAT-based Upper-Bound Computation	1
Advancing Hyperdimensional Computing Based on Trainable Encoding and Adaptive Training for Efficient and Accurate Learning	1
Application-level Validation of Accelerator Designs Using a Formal Software/Hardware Interface	1
BoA-PTA: A Bayesian Optimization Accelerated PTA Solver for SPICE Simulation	1
A Reconfigurable 7T SRAM Bit Cell for High Speed, Power Saving and Low Voltage Application	1
GANDSE: Generative Adversarial Network-based Design Space Exploration for Neural Network Accelerator Design	1
Low-energy Pipelined Hardware Design for Approximate Medium Filter	1
Survey of Machine Learning for Software-assisted Hardware Design Verification: Past, Present, and Prospect	1
SparGD: A Sparse GEMM Accelerator with Dynamic Dataflow	1
Dynamic Adaptation Using Deep Reinforcement Learning for Digital Microfluidic Biochips	1
A Deep Learning Framework for Solving Stress-based Partial Differential Equations in Electromigration Analysis	1
ProtFe: Low-Cost Secure Power Side-Channel Protection for General and Custom FeFET-Based Memories	1
Enhanced Watermarking for Paper-Based Digital Microfluidic Biochips	1
CNNFlow: Memory-driven Data Flow Optimization for Convolutional Neural Networks	1
Load Balanced PIM-Based Graph Processing	1
Improving LDPC Decoding Performance for 3D TLC NAND Flash by LLR Optimization Scheme for Hard and Soft Decision	1
Fast Area Optimization Approach for XNOR/OR-based Fixed Polarity Reed-Muller Logic Circuits based on Multi-strategy Wolf Pack Algorithm	1
A Multilevel Spectral Framework for Scalable Vectorless Power/Thermal Integrity Verification	1
CoVerPlan: A Co mprehensive Ver ification Plan ning Framework Leveraging PSS Specifications	1
Accurately Measuring Contention in Mesh NoCs in Time-Sensitive Embedded Systems	1