ACM Transactions on Design Automation of Electronic Systems

Papers
(The median citation count of ACM Transactions on Design Automation of Electronic Systems is 1. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-08-01 to 2025-08-01.)
ArticleCitations
Inferencing on Edge Devices: A Time- and Space-aware Co-scheduling Approach100
A Problem-tailored Adversarial Deep Neural Network-Based Attack Model for Feed-Forward Physical Unclonable Functions71
A Compact High-Dimensional Yield Analysis Method using Low-Rank Tensor Approximation50
A Mixed-Criticality Traffic Scheduler with Mitigating Congestion for CAN-to-TSN Gateway25
Reduced On-chip Storage of Seeds for Built-in Test Generation24
Multi-Row Guiding Template Design for Lamellar Directed Self-Assembly with Self-Aligned Via Process24
Graph Neural Networks for High-Level Synthesis Design Space Exploration23
IDeSyDe: Systematic Design Space Exploration via Design Space Identification22
Fast Area Optimization Approach for XNOR/OR-based Fixed Polarity Reed-Muller Logic Circuits based on Multi-strategy Wolf Pack Algorithm20
Exploring Large Language Models for Hierarchical Hardware Circuit and Testbench Generation19
A High-Performance Accelerator for Real-Time Super-Resolution on Edge FPGAs18
Layout Synthesis for Quantum Circuits Considering Toffoli Gate Decomposition17
ECO-GNN: Signoff Power Prediction Using Graph Neural Networks with Subgraph Approximation16
SparGD: A Sparse GEMM Accelerator with Dynamic Dataflow16
C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap16
The Resistance Analysis Attack and Security Enhancement of the IMC LUT Based on the Complementary Resistive Switch Cells14
A Reliability-Aware Splitting Duty-Cycle Physical Unclonable Function Based on Trade-off Process, Voltage, and Temperature Variations14
Component Fault Diagnosability of Hierarchical Cubic Networks14
Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems13
STRIVE: Empowering a Low Power Tensor Processing Unit with Fault Detection and Error Resilience13
Introduction to the Special Issue on Embedded System Software/Tools12
Securing Network-on-Chips against Trojan-Induced Packet Duplication Attacks12
Rethinking Logic Rewriting: Technology-Aware Subgraph Matching with Exact Synthesis12
A Tensor Network based Decision Diagram for Representation of Quantum Circuits12
DTGx2: Dual Target Diagnostic Test Generation12
Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs11
VeriGen: A Large Language Model for Verilog Code Generation10
Context-aware Data Augmentation for Hardware Code Fault localization10
Harnessing Machine Learning in Dynamic Thermal Management in Embedded CPU-GPU Platforms9
Enhanced Real-time Scheduling of AVB Flows in Time-Sensitive Networking9
Towards Fine-Grained Online Adaptive Approximation Control for Dense SLAM on Embedded GPUs9
Enhanced TransUNet Framework for Predicting Static IR Drop and Chip Routability9
Non-Preemptive Scheduling of Periodic Tasks with Data Dependencies in Heterogeneous Multiprocessor Embedded Systems9
Poor Man's Training on MCUs: A Memory-Efficient Quantized Back-Propagation-Free Approach8
EDA-Copilot: A RAG-Powered Intelligent Assistant for EDA Tools8
Improving LDPC Decoding Performance for 3D TLC NAND Flash by LLR Optimization Scheme for Hard and Soft Decision8
Interactive Visual Performance Space Exploration of Operational Amplifiers with Differentiable Neural Network Surrogate Models8
A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator7
Optimal Model Partitioning with Low-Overhead Profiling on the PIM-based Platform for Deep Learning Inference7
AiTPO: KAN-UNet Heterogeneous Network for Timing Prediction and Optimization at Global Routing7
Programmable In-memory Computing Circuit of Fast Hartley Transform7
LHS: LLM Assisted Efficient High-level Synthesis of Deep Learning Tasks7
Dynamic Per-Flow Queues in Shared Buffer TSN Switches7
ParTBC: Faster Estimation of Top- k Betweenness Centrality Vertices on GPU7
Optimal Pattern Retargeting in IEEE 1687 Networks: A SAT-based Upper-Bound Computation7
Boosting VLSI Design Flow Parameter Tuning with Random Embedding and Multi-objective Trust-region Bayesian Optimization7
Real-time Blood Pressure Prediction on Wearables with Edge-Based DNNs: A Co-Design Approach6
LLM-assisted Bug Identification and Correction for Verilog HDL6
NeuroCool: Dynamic Thermal Management of 3D DRAM for Deep Neural Networks through Customized Prefetching6
MapTune: Versatile ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning6
A Heterogeneous Chiplet Architecture for Accelerating End-to-End Transformer Models6
Systemization of Knowledge: Robust Deep Learning using Hardware-software co-design in Centralized and Federated Settings6
An Efficient Execution Framework of Two-Part Execution Scenario Analysis6
GANDSE: Generative Adversarial Network-based Design Space Exploration for Neural Network Accelerator Design6
Mitigating Memory Wall Effects in CNN Engines with On-the-Fly Weights Generation6
Detecting Adversarial Examples Utilizing Pixel Value Diversity6
Training PPA Models for Embedded Memories on a Low-data Diet6
Demand-Driven Multi-Target Sample Preparation on Resource-Constrained Digital Microfluidic Biochips6
CeMux: Maximizing the Accuracy of Stochastic Mux Adders and an Application to Filter Design6
An Efficient Reinforcement Learning Based Framework for Exploring Logic Synthesis6
RL-MUL 2.0: Multiplier Design Optimization with Parallel Deep Reinforcement Learning and Space Reduction5
Optimal Mixed-Cell-Height Detailed Placement with Discrete Spacing Costs5
Quantum Circuit Transformation: A Monte Carlo Tree Search Framework5
A Single Bitline Highly Stable, Low Power With High Speed Half-Select Disturb Free 11T SRAM Cell5
GenPart 2.0: Enhanced Hypergraph Partitioning with Vertex Weight Handling using a Generative Model5
MCMCF-Router: Multi-capacity Ordered Escape Routing Algorithms for Grid/Staggered Pin Array5
DeepVerifier: Learning to Update Test Sequences for Coverage-Guided Verification5
TriHOT: Triangular and Hexagonal Norm Based Timing-Driven Optical Routing with Wavelength Division Multiplexing5
Fault-Tolerant Cyclic Queuing and Forwarding with Fast ACK in Time-Sensitive Networking5
PSCaps: High-Performance Pose-Sensitive Layout Hotspot Detector based on CapsNet5
Deep Reinforcement Learning-Based Resource Allocation with Enhanced Perception and Low-Latency for Autonomous Driving in ISAC-aided VEC5
A Scenario-Based DVFS-Aware Hybrid Application Mapping Methodology for MPSoCs5
An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators5
ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction5
A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits5
FLAG: F inding L ine A nomalies (in RTL code) with G enerative AI5
Learning-based Phase-aware Multi-core CPU Workload Forecasting5
GAN-Place: Advancing Open Source Placers to Commercial-quality Using Generative Adversarial Networks and Transfer Learning5
Automatic Mapping of the Best-Suited DNN Pruning Schemes for Real-Time Mobile Acceleration4
Bridging Hotspot Detection and Mask Optimization via Domain-Crossing Masked Layout Modeling4
Machine-learning-driven Architectural Selection of Adders and Multipliers in Logic Synthesis4
Algorithm-Hardware Co-design for Accelerating Depthwise Separable CNNs4
Security Evaluation of State Space Obfuscation of Hardware IP through a Red Team-Blue Team Practice4
A Cascaded ReRAM-based Crossbar Architecture for Transformer Neural Network Acceleration4
DANCE: DAta-Network Co-optimization for Efficient Segmentation Model Training and Inference4
Scalable and Accelerated Self-healing Control Circuit Using Evolvable Hardware4
Sensor-Aware Data Imputation for Time-Series Machine Learning on Low-Power Wearable Devices4
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration4
Fault Localization Scheme for Missing Gate Faults in Reversible Circuits4
A High-performance Masking Design Approach for Saber against High-order Side-channel Attack4
Application Mapping and Control-system Design for Microfluidic Biochips with Distributed Channel Storage4
Polling-Based Memory Interface4
MOEA/D vs. NSGA-II: A Comprehensive Comparison for Multi/Many Objective Analog/RF Circuit Optimization through a Generic Benchmark4
Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic Devices4
FUBOCO: Structure Synthesis of Basic Op-Amps by FUnctional BlOck COmposition4
A Systematic Mapping Study on SystemC/TLM Modeling Capabilities in New Research Domains4
A Soft-Error Mitigation Approach Using Pulse Quenching Enhancement at Detailed Placement for Combinational Circuits4
A Low-Overhead and High-Security Cryptographic Circuit Design Utilizing the TIGFET-Based Three-Phase Single-Rail Pulse Register against Side-Channel Attacks4
A General Layout Pattern Clustering Using Geometric Matching-based Clip Relocation and Lower-bound Aided Optimization4
HAPE: Hardware-Aware LLM Pruning For Efficient On-Device Inference Optimization4
Multi-Objective Optimization for Safety-Related Available E/E Architectures Scoping Highly Automated Driving Vehicles4
Semi-Permanent Stuck-At Fault injection attacks on Elephant and GIFT lightweight ciphers4
Dynamic Adaptation Using Deep Reinforcement Learning for Digital Microfluidic Biochips3
Ax-BxP: Approximate Blocked Computation for Precision-reconfigurable Deep Neural Network Acceleration3
Empirical Guidelines for Deploying LLMs onto Resource-constrained Edge Devices3
Routability Optimization of Extreme Aspect Ratio Design through Non-uniform Placement Utilization and Selective Flip-flop Stacking3
Two-dimensional Search Space for Extracting Broadside Tests from Functional Test Sequences3
Construction of All Multilayer Monolithic RSMTs and Its Application to Monolithic 3D IC Routing3
A Switching NMOS Based Single Ended Sense Amplifier for High Density SRAM Applications3
PriorMSM: An Efficient Acceleration Architecture for Multi-Scalar Multiplication3
Efficient Test Chip Design via Smart Computation3
A Compact TRNG Design for FPGA Based on the Metastability of RO-driven Shift Registers3
Efficient Attacks on Strong PUFs via Covariance and Boolean Modeling3
ChatDSE: A Zero-Shot Microarchitecture Design Space Explorer Powered by GPT4.03
Learning from the Past: Efficient High-level Synthesis Design Space Exploration for FPGAs3
Structured Dynamic Precision for Deep Neural Networks Quantization3
Mathematical Framework for Optimizing Crossbar Allocation for ReRAM-based CNN Accelerators3
A Power Optimization Approach for Large-scale RM-TB Dual Logic Circuits Based on an Adaptive Multi-Task Intelligent Algorithm3
Synthesis of Clock Networks with a Mode-Reconfigurable Topology3
Surrogate Lagrangian Relaxation: A Path to Retrain-Free Deep Neural Network Pruning3
MAB-BMC: A Formal Verification Enhancer by Harnessing Multiple BMC Engines Together3
Introduction to the Special Issue on Machine Learning for CAD/EDA3
Hardware-aware Quantization/Mapping Strategies for Compute-in-Memory Accelerators3
Rescuing ReRAM-based Neural Computing Systems from Device Variation3
Estimating Power, Performance, and Area for On-Sensor Deployment of AR/VR Workloads Using an Analytical Framework3
Application-level Validation of Accelerator Designs Using a Formal Software/Hardware Interface2
EF-Train: Enable Efficient On-device CNN Training on FPGA through Data Reshaping for Online Adaptation or Personalization2
AutoSilicon: Scaling Up RTL Design Generation Capability of Large Language Models2
Distance-aware Approximate Nanophotonic Interconnect2
Introduction to the Special Issue on Design for Testability and Reliability of Security-aware Hardware2
Enhancing Lifetime and Performance of MLC NVM Caches Using Embedded Trace Buffers2
RSPP: Restricted Static Pseudo-Partitioning for Mitigation of Cross-Core Covert Channel Attacks2
Implementation, Characterization and Application of Path Changing Switch based Arbiter PUF on FPGA as a lightweight Security Primitive for IoT2
Sherlock: A Multi-Objective Design Space Exploration Framework2
Multi-Stream Scheduling of Inference Pipelines on Edge Devices - a DRL Approach2
HSG-RAG: Hierarchical Knowledge Base Construction for Embedded System Development2
Transfer Learning Enabled Modeling Paradigm for PVT-aware Circuit Performance Estimation2
Unveiling Cross-checking Opportunities in Verilog Compilers2
DRC-SG 2.0: Efficient Design Rule Checking Script Generation via Key Information Extraction2
A Brain-Inspired Hardware Architecture for Evolutionary Algorithms Based on Memristive Arrays2
ARM-CO-UP: ARM COoperative Utilization of Processors2
AIMCU-MESO: An In-Memory Computing Unit Constructed by MESO Device2
HEANA : A Hybrid Time-Amplitude Analog Optical Accelerator with Flexible Dataflows for Energy-Efficient CNN Inference2
Advancing Hyperdimensional Computing Based on Trainable Encoding and Adaptive Training for Efficient and Accurate Learning2
Introduction to the Special Section on Energy-Efficient AI Chips2
TMDS: Temperature-aware Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems2
A Survey on Transistor-Level Electrical Rule Checking of Integrated Circuits2
Secure & Reliable 10T SRAM Cell during Read, Write and Hold Operations against Power Analysis Attack2
Towards LDPC Read Performance of 3D Flash Memories with Layer-induced Error Characteristics2
CuPBoP: Making CUDA a Portable Language2
Energy Efficient Boosting of GEMM Accelerators for DNN via Reuse2
G-kway: Multilevel GPU-Accelerated k-way Graph Partitioner using Task Graph Parallelism2
SafeTI: A Hardware Traffic Injector for Complex MPSoC Platform Validation and Characterization2
Memristive-based Mixed-signal CGRA for Accelerating Deep Neural Network Inference2
NPU-Accelerated Imitation Learning for Thermal Optimization of QoS-Constrained Heterogeneous Multi-Cores2
CRP2.0: A Fast and Robust Cooperation between Routing and Placement in Advanced Technology Nodes2
Translating Test Responses to Images for Test-termination Prediction via Multiple Machine Learning Strategies2
A High Throughput STR-based TRNG by Jitter Precise Quantization Superposing2
LOGIC: Logic Synthesis for Digital In-Memory Computing2
Modeling Retention Errors of 3D NAND Flash for Optimizing Data Placement2
Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation2
Resister: A Resilient Interposer Architecture for Chiplet to Mitigate Timing Side-Channel Attacks2
FV-LIDAC: Formally Verified Library of Input Data Aware Approximate Arithmetic Circuits2
Improving the Performance of CNN Accelerator Architecture under the Impact of Process Variations2
Adaptive Redistribution Layer Routing for Chiplet-Package Co-Design in 2.5D System2
A Design Methodology for Energy-Aware Processing in Unmanned Aerial Vehicles2
Harmonic Estimation and Comparative Analysis of Ultra-High Speed Flip-Flop and Latch Topologies for Low Power and High Performance Future Generation Micro-/Nano Electronic Systems2
Task Modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems with Heterogeneous Resources2
gem5-NVDLA: A Simulation Framework for Compiling, Scheduling, and Architecture Evaluation on AI System-on-Chips2
Enable Deep Learning on Mobile Devices: Methods, Systems, and Applications1
HyperPlace: Harnessing a Large Language Model for Efficient Hyperparameter Optimization in GPU-Accelerated VLSI Placement1
Pareto Optimization of Analog Circuits Using Reinforcement Learning1
Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design1
Enhanced PATRON: Fault Injection and Power-aware FSM Encoding Through Linear Programming1
Mitigating Mode-switch through Run-time Computation of Response Time1
LithoExp: Explainable Two-stage CNN-based Lithographic Hotspot Detection with Layout Defect Localization1
A Survey on Security of Digital Microfluidic Biochips: Technology, Attack, and Defense1
Data Pruning-enabled High Performance and Reliable Graph Neural Network Training on ReRAM-based Processing-in-Memory Accelerators1
ZeroD-fender: A Resource-aware IoT Malware Detection Engine via Fine-grained Side-channel Analysis1
A CPU+FPGA OpenCL Heterogeneous Computing Platform for Multi-Kernel Pipeline1
H3D-Transformer: A Heterogeneous 3D (H3D) Computing Platform for Transformer Model Acceleration on Edge Devices1
Global Interconnect Optimization1
WCPNet: Jointly Predicting Wirelength, Congestion and Power for FPGA Using Multi-Task Learning1
Introduction to the Special Issue on Approximate Systems1
Magnetic Core TSV-Inductor Design and Optimization for On-chip DC-DC Converter1
CRM_BF:A Low-Overhead, High-Efficient and Reconfigurable Operation Unit Design Approach Using the Customized Reed-Muller Unit For Boolean Functions of Sequence Cipher Algorithms1
iPO: Constant Liar Parameter Optimization for Placement with Representation and Transfer Learning1
A Native SPICE Implementation of Memristor Models for Simulation of Neuromorphic Analog Signal Processing Circuits1
STCO: Enhancing Training Efficiency via Structured Sparse Tensor Compilation Optimization1
Comparative Analysis of Dynamic Power Consumption of Parallel Prefix Adder1
An Adaptive Application Framework with Customizable Quality Metrics1
CmpCNN: CMP Modeling with Transfer Learning CNN Architecture1
Flip : Data-centric Edge CGRA Accelerator1
Fault Injection Attack Emulation Framework for Early Evaluation of IC Designs1
HDLdebugger: Streamlining HDL debugging with Large Language Models1
Global Placement Exploiting Soft 2D Regularity1
Multi-target Fluid Mixing in MEDA Biochips: Theory and an Attempt toward Waste Minimization1
SHAREDD: Sharing of Test Data and Design-for-Testability Logic for Transition Fault Tests under Standard Scan1
A data-centric chip design agent framework for Verilog code generation1
HNM-CIM: An Algorithm-Hardware Co-designed SRAM-based CIM for Transformer Acceleration Exploiting Hybrid N:M Sparsity1
E2HRL: An Energy-efficient Hardware Accelerator for Hierarchical Deep Reinforcement Learning1
Energy-Constrained Scheduling for Weakly Hard Real-Time Systems Using Standby-Sparing1
Enhancing the Effectiveness of STLs for GPUs via Bounded Model Checking1
An Efficient Method of DRC Violation Prediction with a Serial Deep Learning Model1
Hierarchical Scheduling of an SDF/L Graph onto Multiple Processors1
EasyMRC: Efficient Mask Rule Checking via Representative Edge Sampling1
A Novel Approach to Reducing Testing Costs and Minimizing Defect Escapes Using Dynamic Neighborhood Range and Shapley Values1
Sorting it out in Hardware: A State-of-the-Art Survey1
Layout Decomposition and Printing Time Optimization for Inkjet-Printed Electronics1
Modified Decoupled Sense Amplifier with Improved Sensing Speed for Low-Voltage Differential SRAM1
A Conditionally Chaotic Physically Unclonable Function Design Framework with High Reliability1
Toward a Human-Readable State Machine Extraction1
Accelerating Deformable Convolution Networks with Dynamic and Irregular Memory Accesses1
Automatic Correction of Arithmetic Circuits in the Presence of Multiple Bugs by Groebner Basis Modification1
A Novel Hybrid Cache Coherence with Global Snooping for Many-core Architectures1
FixRTL: Auto-correction of Multiple RTL Bugs by a New Feature Burst Clustering Algorithm and Mutation1
Test Point Insertion for Multi-Cycle Power-On Self-Test1
PROTECTS: Progressive Rtl Obfuscation with ThrEshold Control Technique during architectural Synthesis1
Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks1
A Case for Precise, Fine-Grained Pointer Synthesis in High-Level Synthesis1
Wages: The Worst Transistor Aging Analysis for Large-scale Analog Integrated Circuits via Domain Generalization1
A Bridge-based Algorithm for Simultaneous Primal and Dual Defects Compression on Topologically Quantum-error-corrected Circuits1
ProtFe: Low-Cost Secure Power Side-Channel Protection for General and Custom FeFET-Based Memories1
Survey of Machine Learning for Software-assisted Hardware Design Verification: Past, Present, and Prospect1
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