ACM Transactions on Design Automation of Electronic Systems

Article	Citations
Introduction to the Special Section on Energy-Efficient AI Chips	162
Multi-Row Guiding Template Design for Lamellar Directed Self-Assembly with Self-Aligned Via Process	51
An Efficient Area and Reliability Optimization Method for MPRM Circuits Based on High-dimensional Genetic Algorithm	41
A Module-Linking Graph Assisted Hybrid Optimization Framework for Custom Analog and Mixed-Signal Circuit Parameter Synthesis	34
Introduction to the Special Issue on Approximate Systems	33
A Novel Hybrid Cache Coherence with Global Snooping for Many-core Architectures	23
Hierarchical Scheduling of an SDF/L Graph onto Multiple Processors	21
Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks	20
Design Automation for Tree-based Nearest Neighborhood–aware Placement of High-speed Cellular Automata on FPGA with Scan Path Insertion	18
A Bridge-based Algorithm for Simultaneous Primal and Dual Defects Compression on Topologically Quantum-error-corrected Circuits	16
Enhancing the Effectiveness of STLs for GPUs via Bounded Model Checking	15
IDeSyDe: Systematic Design Space Exploration via Design Space Identification	15
Energy-Constrained Scheduling for Weakly Hard Real-Time Systems Using Standby-Sparing	14
Floorplanning with Edge-aware Graph Attention Network and Hindsight Experience Replay	14
WCPNet: Jointly Predicting Wirelength, Congestion and Power for FPGA Using Multi-Task Learning	14
Design of Enhanced Reversible 9T SRAM Design for the Reduction in Sub-threshold Leakage Current with14nm FinFET Technology	13
Modeling Retention Errors of 3D NAND Flash for Optimizing Data Placement	13
Heterogeneous Integration Supply Chain Integrity Through Blockchain and CHSM	13
Applying reinforcement learning to learn best net to rip and re-route in global routing	12
An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators	12
Reduced On-chip Storage of Seeds for Built-in Test Generation	11
Introduction to the Special Issue on Design for Testability and Reliability of Security-aware Hardware	10
A High-Performance Accelerator for Real-Time Super-Resolution on Edge FPGAs	9
A Single Bitline Highly Stable, Low Power With High Speed Half-Select Disturb Free 11T SRAM Cell	9
Root-Cause Analysis with Semi-Supervised Co-Training for Integrated Systems	9

A Mixed-Criticality Traffic Scheduler with Mitigating Congestion for CAN-to-TSN Gateway	9
A Scenario-Based DVFS-Aware Hybrid Application Mapping Methodology for MPSoCs	9
Enhancing Lifetime and Performance of MLC NVM Caches Using Embedded Trace Buffers	9
Load Balanced PIM-Based Graph Processing	9
Deadline and Period Assignment for Guaranteeing Timely Response of the Cyber-Physical System	8
TMDS: Temperature-aware Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems	8
CNN-Cap: Effective Convolutional Neural Network-based Capacitance Models for Interconnect Capacitance Extraction	7
A Problem-tailored Adversarial Deep Neural Network-Based Attack Model for Feed-Forward Physical Unclonable Functions	7
Worst-case Power Integrity Prediction Using Convolutional Neural Network	7
A Native SPICE Implementation of Memristor Models for Simulation of Neuromorphic Analog Signal Processing Circuits	7
Inferencing on Edge Devices: A Time- and Space-aware Co-scheduling Approach	7
A High Throughput STR-based TRNG by Jitter Precise Quantization Superposing	7
A Survey and Perspective on Artificial Intelligence for Security-Aware Electronic Design Automation	7
A Compact High-Dimensional Yield Analysis Method using Low-Rank Tensor Approximation	6
A Case for Precise, Fine-Grained Pointer Synthesis in High-Level Synthesis	6
Machine Learning for Electronic Design Automation: A Survey	6
Quantum Circuit Transformation: A Monte Carlo Tree Search Framework	6
Security Assessment of Dynamically Obfuscated Scan Chain Against Oracle-guided Attacks	6
Learning-based Phase-aware Multi-core CPU Workload Forecasting	5
A Comprehensive Survey of Attacks without Physical Access Targeting Hardware Vulnerabilities in IoT/IIoT Devices, and Their Detection Mechanisms	5
Secure & Reliable 10T SRAM Cell during Read, Write and Hold Operations against Power Analysis Attack	5
HEANA : A Hybrid Time-Amplitude Analog Optical Accelerator with Flexible Dataflows for Energy-Efficient CNN Inference	5
An Energy-Efficient Inference Method in Convolutional Neural Networks Based on Dynamic Adjustment of the Pruning Level	5
Graph Neural Networks for High-Level Synthesis Design Space Exploration	5
E 2 -VOR: An End-to-End En/Decoder Architecture for Efficient Video Object Recognition	5
Test Point Insertion for Multi-Cycle Power-On Self-Test	5
Fast Area Optimization Approach for XNOR/OR-based Fixed Polarity Reed-Muller Logic Circuits based on Multi-strategy Wolf Pack Algorithm	5
Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements	5
Unveiling Cross-checking Opportunities in Verilog Compilers	5
Auto-tuning Fixed-point Precision with TVM on RISC-V Packed SIMD Extension	5
Fault Injection Attack Emulation Framework for Early Evaluation of IC Designs	4
AIMCU-MESO: An In-Memory Computing Unit Constructed by MESO Device	4
A General Layout Pattern Clustering Using Geometric Matching-based Clip Relocation and Lower-bound Aided Optimization	4
Sherlock: A Multi-Objective Design Space Exploration Framework	4
A Reliability-Aware Splitting Duty-Cycle Physical Unclonable Function Based on Trade-off Process, Voltage, and Temperature Variations	4
A Constructive Approach for Threshold Function Identification	4
A High-performance Masking Design Approach for Saber against High-order Side-channel Attack	4
Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems	4
EF-Train: Enable Efficient On-device CNN Training on FPGA through Data Reshaping for Online Adaptation or Personalization	4
A Delay-Adjustable, Self-Testable Flip-Flop for Soft-Error Tolerability and Delay-Fault Testability	4
Machine Learning Based Framework for Fast Resource Estimation of RTL Designs Targeting FPGAs	4
Multi-Objective Optimization for Safety-Related Available E/E Architectures Scoping Highly Automated Driving Vehicles	4
Automatic Mapping of the Best-Suited DNN Pruning Schemes for Real-Time Mobile Acceleration	4
FUBOCO: Structure Synthesis of Basic Op-Amps by FUnctional BlOck COmposition	4
Implication of Optimizing NPU Dataflows on Neural Architecture Search for Mobile Devices	4
A Fast Optimal Double-row Legalization Algorithm	4
Component Fault Diagnosability of Hierarchical Cubic Networks	4
HLS-IRT: Hardware Trojan Insertion through Modification of Intermediate Representation During High-Level Synthesis	3
Automatic Test Pattern Generation for Robust Quantum Circuit Testing	3
Introduction to the Special Issue on Embedded System Software/Tools	3

SIMTAM: Generation Diversity Test Programs for FPGA Simulation Tools Testing Via Timing Area Mutation	3
DeLoSo: Detecting Logic Synthesis Optimization Faults Based on Configuration Diversity	3
Deep Reinforcement Learning-based Mining Task Offloading Scheme for Intelligent Connected Vehicles in UAV-aided MEC	3
DeepFlow: A Cross-Stack Pathfinding Framework for Distributed AI Systems	3
Harmonic Estimation and Comparative Analysis of Ultra-High Speed Flip-Flop and Latch Topologies for Low Power and High Performance Future Generation Micro-/Nano Electronic Systems	3
AmLuCEP: Amalgamating LUT-based Compression and Adaptive Encoding Assisted Block Placement To Improve Lifetime of PCM-based Main Memories	3
gem5-NVDLA: A Simulation Framework for Compiling, Scheduling, and Architecture Evaluation on AI System-on-Chips	3
A Tensor Network based Decision Diagram for Representation of Quantum Circuits	3
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration	3
A Survey on Security of Digital Microfluidic Biochips: Technology, Attack, and Defense	3
Adversarial Circuit Rewriting against Graph Neural Network-based Operator Detection	3
ZoneTrace: Zone Monitoring Tool for F2FS on ZNS SSDs	3
On-chip ESD Protection Design Methodologies by CAD Simulation	3
The Resistance Analysis Attack and Security Enhancement of the IMC LUT Based on the Complementary Resistive Switch Cells	3
D 3 PBO: D ynamic D omain D ecomposition-based P	3
CRP2.0: A Fast and Robust Cooperation between Routing and Placement in Advanced Technology Nodes	3
MCMCF-Router: Multi-capacity Ordered Escape Routing Algorithms for Grid/Staggered Pin Array	3
NPU-Accelerated Imitation Learning for Thermal Optimization of QoS-Constrained Heterogeneous Multi-Cores	3
SafeTI: A Hardware Traffic Injector for Complex MPSoC Platform Validation and Characterization	3
A Deep Learning Framework for Solving Stress-based Partial Differential Equations in Electromigration Analysis	3
Enhanced Watermarking for Paper-Based Digital Microfluidic Biochips	3
GAN-Place: Advancing Open Source Placers to Commercial-quality Using Generative Adversarial Networks and Transfer Learning	3
An Efficient FPGA Architecture with Turn-Restricted Switch Boxes	3
SparGD: A Sparse GEMM Accelerator with Dynamic Dataflow	3
Multi-target Fluid Mixing in MEDA Biochips: Theory and an Attempt toward Waste Minimization	3
Routability-driven Power/Ground Network Optimization Based on Machine Learning	3
Harnessing Machine Learning in Dynamic Thermal Management in Embedded CPU-GPU Platforms	2
Sensor-Aware Data Imputation for Time-Series Machine Learning on Low-Power Wearable Devices	2
DDAM: D ata D istribution- A ware M apping of CNNs on Processing-In-Memory S	2
A Low-power Programmable Machine Learning Hardware Accelerator Design for Intelligent Edge Devices	2
Energy Efficient Error Resilient Multiplier Using Low-power Compressors	2
Degraded Mode-benefited I/O Scheduling to Ensure I/O Responsiveness in RAID-enabled SSDs	2
Non-Preemptive Scheduling of Periodic Tasks with Data Dependencies in Heterogeneous Multiprocessor Embedded Systems	2
GNN-based Multi-bit Flip-flop Clustering and Post-clustering Design Optimization for Energy-efficient 3D ICs	2
Security Evaluation of State Space Obfuscation of Hardware IP through a Red Team-Blue Team Practice	2
A Brain-Inspired Hardware Architecture for Evolutionary Algorithms Based on Memristive Arrays	2
STRIVE: Empowering a Low Power Tensor Processing Unit with Fault Detection and Error Resilience	2
Implementation, Characterization and Application of Path Changing Switch based Arbiter PUF on FPGA as a lightweight Security Primitive for IoT	2
DANCE: DAta-Network Co-optimization for Efficient Segmentation Model Training and Inference	2
Dataflow Model–based Software Synthesis Framework for Parallel and Distributed Embedded Systems	2
Advancing Hyperdimensional Computing Based on Trainable Encoding and Adaptive Training for Efficient and Accurate Learning	2
Application Mapping and Control-system Design for Microfluidic Biochips with Distributed Channel Storage	2
Introduction to the Special Section on High-level Synthesis for FPGA: Next-generation Technologies and Applications	2
Breaking the Design and Security Trade-off of Look-up-table–based Obfuscation	2
Design Space Optimization of Shared Memory Architecture in Accelerator-rich Systems	2
Design of Synthesis-time Vectorized Arithmetic Hardware for Tapered Floating-point Addition and Subtraction	2
LOGIC: Logic Synthesis for Digital In-Memory Computing	2
Toward a Human-Readable State Machine Extraction	2
ECO-GNN: Signoff Power Prediction Using Graph Neural Networks with Subgraph Approximation	2
FTT-NAS: Discovering Fault-tolerant Convolutional Neural Architecture	2
ARM-CO-UP: ARM COoperative Utilization of Processors	2
A Module-Level Configuration Methodology for Programmable Camouflaged Logic	2
Task Modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems with Heterogeneous Resources	2
Capacity-Aware Wash Optimization with Dynamic Fluid Scheduling and Channel Storage for Continuous-Flow Microfluidic Biochips	2
Enhanced Real-time Scheduling of AVB Flows in Time-Sensitive Networking	2
Data Privacy Made Easy: Enhancing Applications with Homomorphic Encryption	2
Synthesizing Brain-network-inspired Interconnections for Large-scale Network-on-chips	2
Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming Approach	2
GraphPlanner: Floorplanning with Graph Neural Network	2
LithoExp: Explainable Two-stage CNN-based Lithographic Hotspot Detection with Layout Defect Localization	2
ICP-RL: Identifying Critical Paths for Fault Diagnosis Using Reinforcement Learning	2
A Soft-Error Mitigation Approach Using Pulse Quenching Enhancement at Detailed Placement for Combinational Circuits	2
POEM: Performance Optimization and Endurance Management for Non-volatile Caches	2
Distance-aware Approximate Nanophotonic Interconnect	2
SwitchX: Gmin-Gmax Switching for Energy-efficient and Robust Implementation of Binarized Neural Networks on ReRAM Xbars	1
A Design Methodology for Energy-Aware Processing in Unmanned Aerial Vehicles	1
Low-energy Pipelined Hardware Design for Approximate Medium Filter	1
A Runtime Reconfigurable Design of Compute-in-Memory–Based Hardware Accelerator for Deep Learning Inference	1
Software/Hardware Co-design of 3D NoC-based GPU Architectures for Accelerated Graph Computations	1
Incremental Concolic Testing of Register-Transfer Level Designs	1
VeriGen: A Large Language Model for Verilog Code Generation	1
A Cascaded ReRAM-based Crossbar Architecture for Transformer Neural Network Acceleration	1
Towards Fine-Grained Online Adaptive Approximation Control for Dense SLAM on Embedded GPUs	1
Fast Candidate Screening for Post-diagnosis Refinement	1
Design Automation Algorithms for the NP-Separate VLSI Design Methodology	1
Leveraging Automatic High-Level Synthesis Resource Sharing to Maximize Dynamical Voltage Overscaling with Error Control	1
A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts	1
QuadSeal: Quadruple Balancing to Mitigate Power Analysis Attacks with Variability Effects and Electromagnetic Fault Injection Attacks	1
Fault Localization Scheme for Missing Gate Faults in Reversible Circuits	1
Lightning: Leveraging DVFS-induced Transient Fault Injection to Attack Deep Learning Accelerator of GPUs	1

Pareto Optimization of Analog Circuits Using Reinforcement Learning	1
Towards LDPC Read Performance of 3D Flash Memories with Layer-induced Error Characteristics	1
DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs	1
Multiterminal Pathfinding in Practical VLSI Systems with Deep Neural Networks	1
Polling-Based Memory Interface	1
Security Threat Analyses and Attack Models for Approximate Computing Systems	1
TAAL	1
Memristive-based Mixed-signal CGRA for Accelerating Deep Neural Network Inference	1
Energy Efficient Boosting of GEMM Accelerators for DNN via Reuse	1
Efficient Attacks on Strong PUFs via Covariance and Boolean Modeling	1
MOEA/D vs. NSGA-II: A Comprehensive Comparison for Multi/Many Objective Analog/RF Circuit Optimization through a Generic Benchmark	1
Application-level Validation of Accelerator Designs Using a Formal Software/Hardware Interface	1
Transfer Learning Enabled Modeling Paradigm for PVT-aware Circuit Performance Estimation	1
ESPSim: An Efficient Scalable Power Grid Simulator Based on Parallel Algebraic Multigrid	1
Translating Test Responses to Images for Test-termination Prediction via Multiple Machine Learning Strategies	1
Performance-driven Wire Sizing for Analog Integrated Circuits	1
Realizing In-Memory Computing using Reliable Differential 8T SRAM for Improved Latency	1
An Efficient Reinforcement Learning Based Framework for Exploring Logic Synthesis	1
Surrogate Lagrangian Relaxation: A Path to Retrain-Free Deep Neural Network Pruning	1
CBDC-PUF: A Novel Physical Unclonable Function Design Framework Utilizing Configurable Butterfly Delay Chain Against Modeling Attack	1
Optimal Pattern Retargeting in IEEE 1687 Networks: A SAT-based Upper-Bound Computation	1
Virtuoso : Energy- and Latency-aware Streamlining of Streaming Videos on Systems-on-Chips	1
Accelerating Graph Computations on 3D NoC-Enabled PIM Architectures	1
EDA-Copilot: A RAG-Powered Intelligent Assistant for EDA Tools	1
Efficient One-pass Synthesis for Digital Microfluidic Biochips	1
Optimal Model Partitioning with Low-Overhead Profiling on the PIM-based Platform for Deep Learning Inference	1
Semi-Permanent Stuck-At Fault injection attacks on Elephant and GIFT lightweight ciphers	1
Accurately Measuring Contention in Mesh NoCs in Time-Sensitive Embedded Systems	1
A Multilevel Spectral Framework for Scalable Vectorless Power/Thermal Integrity Verification	1
Scalable and Accelerated Self-healing Control Circuit Using Evolvable Hardware	1
A Reconfigurable 7T SRAM Bit Cell for High Speed, Power Saving and Low Voltage Application	1
DeepOTF: Learning Equations-constrained Prediction for Electromagnetic Behavior	1
DRC-SG 2.0: Efficient Design Rule Checking Script Generation via Key Information Extraction	1
An Efficient and Effective Optimization Algorithm for Buffer and Splitter Insertion in AQFP Circuits	1
IMPRoVED: Integrated Method to Predict PostRouting setup Violations in Early Design Stages	1
A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route	1
Programmable In-memory Computing Circuit of Fast Hartley Transform	1
A Compact TRNG Design for FPGA Based on the Metastability of RO-driven Shift Registers	1
Improving the Performance of CNN Accelerator Architecture under the Impact of Process Variations	1
Enhanced Compiler Technology for Software-based Hardware Fault Detection	1