ACM Transactions on Design Automation of Electronic Systems

Article	Citations
Machine Learning for Electronic Design Automation: A Survey	117
Enable Deep Learning on Mobile Devices: Methods, Systems, and Applications	47
Security Assessment of Dynamically Obfuscated Scan Chain Against Oracle-guided Attacks	32
AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators	27
Reconfigurable Network-on-Chip Security Architecture	20
TAAL	19
Adversarial Perturbation Attacks on ML-based CAD	18
MaxSense	18
A Survey on Security of Digital Microfluidic Biochips: Technology, Attack, and Defense	15
Modular Neural Networks for Low-Power Image Classification on Embedded Devices	15
High-Level Synthesis of Key-Obfuscated RTL IP with Design Lockout and Camouflaging	14
A Comprehensive Survey of Attacks without Physical Access Targeting Hardware Vulnerabilities in IoT/IIoT Devices, and Their Detection Mechanisms	14
CeMux: Maximizing the Accuracy of Stochastic Mux Adders and an Application to Filter Design	13
EF-Train: Enable Efficient On-device CNN Training on FPGA through Data Reshaping for Online Adaptation or Personalization	13
FTT-NAS: Discovering Fault-tolerant Convolutional Neural Architecture	12
Voltage-Based Covert Channels Using FPGAs	12
Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design	12
Directed Test Generation for Activation of Security Assertions in RTL Models	11
PREASC	10
Core Placement Optimization for Multi-chip Many-core Neural Network Systems with Reinforcement Learning	10
MNFTL	10
A Robust Modulus-Based Matrix Splitting Iteration Method for Mixed-Cell-Height Circuit Legalization	10
MeF-RAM: A New Non-Volatile Cache Memory Based on Magneto-Electric FET	9
Security Threat Analyses and Attack Models for Approximate Computing Systems	9
Machine Learning Approach for Fast Electromigration Aware Aging Prediction in Incremental Design of Large Scale On-chip Power Grid Network	8

A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits	8
A Tensor Network based Decision Diagram for Representation of Quantum Circuits	8
NoC Application Mapping Optimization Using Reinforcement Learning	8
Graph Neural Networks for High-Level Synthesis Design Space Exploration	8
High-Level Synthesis Implementation of an Embedded Real-Time HEVC Intra Encoder on FPGA for Media Applications	7
TransNet	7
Design Flow and Methodology for Dynamic and Static Energy-constrained Scheduling Framework in Heterogeneous Multicore Embedded Devices	7
FUBOCO: Structure Synthesis of Basic Op-Amps by FUnctional BlOck COmposition	7
Machine Learning for Congestion Management and Routability Prediction within FPGA Placement	7
Towards Smarter Diagnosis	7
FastCFI: Real-time Control-Flow Integrity Using FPGA without Code Instrumentation	6
Mitigating Negative Impacts of Read Disturb in SSDs	6
NeuPow	6
Sherlock: A Multi-Objective Design Space Exploration Framework	6
High-throughput Near-Memory Processing on CNNs with 3D HBM-like Memory	6
Learning from the Past: Efficient High-level Synthesis Design Space Exploration for FPGAs	6
ESPSim: An Efficient Scalable Power Grid Simulator Based on Parallel Algebraic Multigrid	6
Implementation, Characterization and Application of Path Changing Switch based Arbiter PUF on FPGA as a lightweight Security Primitive for IoT	6
A Deterministic-Path Routing Algorithm for Tolerating Many Faults on Very-Large-Scale Network-on-Chip	6
Machine Learning Approaches for Efficient Design Space Exploration of Application-Specific NoCs	6
RASCv2: Enabling Remote Access to Side-Channels for Mission Critical and IoT Systems	6
HeM3D	6
A Module-Linking Graph Assisted Hybrid Optimization Framework for Custom Analog and Mixed-Signal Circuit Parameter Synthesis	6
Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration	5
A Comprehensive Survey on Electronic Design Automation and Graph Neural Networks: Theory and Applications	5
Dataflow Model–based Software Synthesis Framework for Parallel and Distributed Embedded Systems	5
Robust Multi-Target Sample Preparation on MEDA Biochips Obviating Waste Production	5
Predicting Memory Compiler Performance Outputs Using Feed-forward Neural Networks	5
VeriGen: A Large Language Model for Verilog Code Generation	5
Multi-Fidelity Surrogate-Based Optimization for Electromagnetic Simulation Acceleration	5
Quantum Circuit Transformation: A Monte Carlo Tree Search Framework	5
Efficient Layout Hotspot Detection via Neural Architecture Search	5
A Runtime Reconfigurable Design of Compute-in-Memory–Based Hardware Accelerator for Deep Learning Inference	5
Fine-grained Adaptive Testing Based on Quality Prediction	5
Fault-based Built-in Self-test and Evaluation of Phase Locked Loops	4
Ising-FPGA	4
Software/Hardware Co-design of 3D NoC-based GPU Architectures for Accelerated Graph Computations	4
Heterogeneous Integration Supply Chain Integrity Through Blockchain and CHSM	4
Machine Learning-based Defect Coverage Boosting of Analog Circuits under Measurement Variations	4
A Learning-based Methodology for Scenario-aware Mapping of Soft Real-time Applications onto Heterogeneous MPSoCs	4
Design Space Optimization of Shared Memory Architecture in Accelerator-rich Systems	4
A Survey and Perspective on Artificial Intelligence for Security-Aware Electronic Design Automation	4
Magnetic Core TSV-Inductor Design and Optimization for On-chip DC-DC Converter	4
Ax-BxP: Approximate Blocked Computation for Precision-reconfigurable Deep Neural Network Acceleration	4
SwitchX : Gmin-Gmax Switching for Energy-efficient and Robust Implementation of Binarized Neural Networks on ReRAM Xbars	4
CNN-Cap: Effective Convolutional Neural Network-based Capacitance Models for Interconnect Capacitance Extraction	4
Efficient Parasitic-aware g m / I D -	3
A Low-power Programmable Machine Learning Hardware Accelerator Design for Intelligent Edge Devices	3
A Switching NMOS Based Single Ended Sense Amplifier for High Density SRAM Applications	3
Accelerating Graph Computations on 3D NoC-Enabled PIM Architectures	3

Energy-Efficient LSTM Inference Accelerator for Real-Time Causal Prediction	3
A Delay-Adjustable, Self-Testable Flip-Flop for Soft-Error Tolerability and Delay-Fault Testability	3
Toward Taming the Overhead Monster for Data-flow Integrity	3
Energy-Efficient GPU L2 Cache Design Using Instruction-Level Data Locality Similarity	3
Multiterminal Pathfinding in Practical VLSI Systems with Deep Neural Networks	3
Automatic Mapping of the Best-Suited DNN Pruning Schemes for Real-Time Mobile Acceleration	3
MEDUSA: A Multi-Resolution Machine Learning Congestion Estimation Method for 2D and 3D Global Routing	3
A Native SPICE Implementation of Memristor Models for Simulation of Neuromorphic Analog Signal Processing Circuits	3
Distance-aware Approximate Nanophotonic Interconnect	3
Hardware Security Risks and Threat Analyses in Advanced Manufacturing Industry	3
Energy Efficient Boosting of GEMM Accelerators for DNN via Reuse	3
Demand-Driven Multi-Target Sample Preparation on Resource-Constrained Digital Microfluidic Biochips	3
DDAM: D ata D istribution- A ware M apping of CNNs on Processing-In-Memory S	3
Security of Electrical, Optical, and Wireless On-chip Interconnects: A Survey	3
CRP2.0: A Fast and Robust Cooperation between Routing and Placement in Advanced Technology Nodes	3
COPE	3
ECO-GNN: Signoff Power Prediction Using Graph Neural Networks with Subgraph Approximation	3
A Dynamic Huffman Coding Method for Reliable TLC NAND Flash Memory	3
Improving FPGA-Based Logic Emulation Systems through Machine Learning	3
A Design Methodology for Energy-Aware Processing in Unmanned Aerial Vehicles	3
Machine Learning for Statistical Modeling	3
Wire Load Oriented Analog Routing with Matching Constraints	3
MOEA/D vs. NSGA-II: A Comprehensive Comparison for Multi/Many Objective Analog/RF Circuit Optimization through a Generic Benchmark	3
MVP: An Efficient CNN Accelerator with Matrix, Vector, and Processing-Near-Memory Units	3
Leveraging Automatic High-Level Synthesis Resource Sharing to Maximize Dynamical Voltage Overscaling with Error Control	3
Placement of Digital Microfluidic Biochips via a New Evolutionary Algorithm	3
Auto-tuning Fixed-point Precision with TVM on RISC-V Packed SIMD Extension	3
A Symbolic Approach to Detecting Hardware Trojans Triggered by Don’t Care Transitions	3
Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements	3
SecureTVM: A TVM-based Compiler Framework for Selective Privacy-preserving Neural Inference	3
TMDS: Temperature-aware Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems	3
Synthesizing Brain-network-inspired Interconnections for Large-scale Network-on-chips	3
E2HRL: An Energy-efficient Hardware Accelerator for Hierarchical Deep Reinforcement Learning	2
SmartDR	2
Towards LDPC Read Performance of 3D Flash Memories with Layer-induced Error Characteristics	2
Multi-objective Optimization of Mapping Dataflow Applications to MPSoCs Using a Hybrid Evaluation Combining Analytic Models and Measurements	2
Machine-learning-driven Architectural Selection of Adders and Multipliers in Logic Synthesis	2
GraphPlanner: Floorplanning with Graph Neural Network	2
Degraded Mode-benefited I/O Scheduling to Ensure I/O Responsiveness in RAID-enabled SSDs	2
Multi-Objective Optimization for Safety-Related Available E/E Architectures Scoping Highly Automated Driving Vehicles	2
Toward a Human-Readable State Machine Extraction	2
Approximate Learning and Fault-Tolerant Mapping for Energy-Efficient Neuromorphic Systems	2
A High Throughput STR-based TRNG by Jitter Precise Quantization Superposing	2
Rescuing ReRAM-based Neural Computing Systems from Device Variation	2
FaultDroid	2
DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs	2
FPGAPRO: A Defense Framework Against Crosstalk-Induced Secret Leakage in FPGA	2
A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route	2
Logic Diagnosis with Hybrid Fail Data	2
Performance-driven Wire Sizing for Analog Integrated Circuits	2
Implication of Optimizing NPU Dataflows on Neural Architecture Search for Mobile Devices	2
Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems	2
A Compact High-Dimensional Yield Analysis Method using Low-Rank Tensor Approximation	2
Learning-based Phase-aware Multi-core CPU Workload Forecasting	2
TROP: TRust-aware OPportunistic Routing in NoC with Hardware Trojans	2
DRAGON: Dynamic Recurrent Accelerator for Graph Online Convolution	2
An Efficient Ring Oscillator PUF Using Programmable Delay Units on FPGA	2
Memory-Throughput Trade-off for CNN-Based Applications at the Edge	2
CBDC-PUF: A Novel Physical Unclonable Function Design Framework Utilizing Configurable Butterfly Delay Chain Against Modeling Attack	2
A Locality Optimizer for Loop-dominated Applications Based on Reuse Distance Analysis	2
QuadSeal: Quadruple Balancing to Mitigate Power Analysis Attacks with Variability Effects and Electromagnetic Fault Injection Attacks	2
On-chip ESD Protection Design Methodologies by CAD Simulation	2
Leakage-Aware Dynamic Thermal Management of 3D Memories	2
Test Point Insertion for Multi-Cycle Power-On Self-Test	2
Design Automation for Tree-based Nearest Neighborhood–aware Placement of High-speed Cellular Automata on FPGA with Scan Path Insertion	2
Power Converter Circuit Design Automation Using Parallel Monte Carlo Tree Search	1
Automatic Synthesis of FSMs for Enforcing Non-functional Requirements on MPSoCs Using Multi-objective Evolutionary Algorithms	1
Hardware-aware Quantization/Mapping Strategies for Compute-in-Memory Accelerators	1
RSPP: Restricted Static Pseudo-Partitioning for Mitigation of Cross-Core Covert Channel Attacks	1
Modified Decoupled Sense Amplifier with Improved Sensing Speed for Low-Voltage Differential SRAM	1
Plasticine: A Cross-layer Approximation Methodology for Multi-kernel Applications through Minimally Biased, High-throughput, and Energy-efficient SIMD Soft Multiplier-divider	1
A Reconfigurable 7T SRAM Bit Cell for High Speed, Power Saving and Low Voltage Application	1
A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts	1
Routability-driven Power/Ground Network Optimization Based on Machine Learning	1
An Energy-Efficient Inference Method in Convolutional Neural Networks Based on Dynamic Adjustment of the Pruning Level	1
Design of Enhanced Reversible 9T SRAM Design for the Reduction in Sub-threshold Leakage Current with14nm FinFET Technology	1
Self Adaptive Logical Split Cache Techniques for Delayed Aging of NVM LLC	1
A Mixed-Criticality Traffic Scheduler with Mitigating Congestion for CAN-to-TSN Gateway	1
BoA-PTA: A Bayesian Optimization Accelerated PTA Solver for SPICE Simulation	1
A Problem-tailored Adversarial Deep Neural Network-Based Attack Model for Feed-Forward Physical Unclonable Functions	1

Test Compression for Launch-on-Capture Transition Fault Testing	1
CNNFlow: Memory-driven Data Flow Optimization for Convolutional Neural Networks	1
Uncertainty-aware Energy Harvest Prediction and Management for IoT Devices	1
A PPA Study of Reinforced Placement Parameter Autotuning: Pseudo-3D vs. True-3D Placers	1
Accuracy Configurable Adders with Negligible Delay Overhead in Exact Operating Mode	1
A Low-Overhead and High-Security Cryptographic Circuit Design Utilizing the TIGFET-Based Three-Phase Single-Rail Pulse Register against Side-Channel Attacks	1
An Adaptive Application Framework with Customizable Quality Metrics	1
Accurately Measuring Contention in Mesh NoCs in Time-Sensitive Embedded Systems	1
Low-energy Pipelined Hardware Design for Approximate Medium Filter	1
NPU-Accelerated Imitation Learning for Thermal Optimization of QoS-Constrained Heterogeneous Multi-Cores	1
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration	1
Inferencing on Edge Devices: A Time- and Space-aware Co-scheduling Approach	1
GANDSE: Generative Adversarial Network-based Design Space Exploration for Neural Network Accelerator Design	1
Worst-case Power Integrity Prediction Using Convolutional Neural Network	1
ProtFe: Low-Cost Secure Power Side-Channel Protection for General and Custom FeFET-Based Memories	1
Uncertainty Theory Based Partitioning for Cyber-Physical Systems with Uncertain Reliability Analysis	1
A Conditionally Chaotic Physically Unclonable Function Design Framework with High Reliability	1
A Framework for Validation of Synthesized MicroElectrode Dot Array Actuations for Digital Microfluidic Biochips	1
Optimal Pattern Retargeting in IEEE 1687 Networks: A SAT-based Upper-Bound Computation	1
Thermal Management for FPGA Nodes in HPC Systems	1
Application Mapping and Control-system Design for Microfluidic Biochips with Distributed Channel Storage	1
Memristive-based Mixed-signal CGRA for Accelerating Deep Neural Network Inference	1
Deep Reinforcement Learning-based Mining Task Offloading Scheme for Intelligent Connected Vehicles in UAV-aided MEC	1
Component Fault Diagnosability of Hierarchical Cubic Networks	1
Harmonic Estimation and Comparative Analysis of Ultra-High Speed Flip-Flop and Latch Topologies for Low Power and High Performance Future Generation Micro-/Nano Electronic Systems	1
Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks	1
Structured Dynamic Precision for Deep Neural Networks Quantization	1
E 2 -VOR: An End-to-End En/Decoder Architecture for Efficient Video Object Recognition	1