ACM Transactions on Design Automation of Electronic Systems

Papers
(The H4-Index of ACM Transactions on Design Automation of Electronic Systems is 18. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-01-01 to 2026-01-01.)
ArticleCitations
Layout Synthesis for Quantum Circuits Considering Toffoli Gate Decomposition138
Reduced On-chip Storage of Seeds for Built-in Test Generation115
Multi-Row Guiding Template Design for Lamellar Directed Self-Assembly with Self-Aligned Via Process61
A Problem-tailored Adversarial Deep Neural Network-Based Attack Model for Feed-Forward Physical Unclonable Functions36
Fast Area Optimization Approach for XNOR/OR-based Fixed Polarity Reed-Muller Logic Circuits based on Multi-strategy Wolf Pack Algorithm33
Exploring Large Language Models for Hierarchical Hardware Circuit and Testbench Generation33
IDeSyDe: Systematic Design Space Exploration via Design Space Identification27
Inferencing on Edge Devices: A Time- and Space-aware Co-scheduling Approach27
Scalable Yield Analysis of SRAM and Analog Circuits Using Multi-Kernel Sparse Representation27
C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap23
Graph Neural Networks for High-Level Synthesis Design Space Exploration22
A High-Performance Accelerator for Real-Time Super-Resolution on Edge FPGAs20
InterAxNN: Reconfigurable and Approximate in-Memory Processing Accelerator for Ultra-Low-Power Binary Neural Network Inference in Intermittently Powered Systems20
Towards Generalizable and Efficient Circuit Topology Design: A Graph-Transformer-based Surrogate Model with Curriculum Learning19
A Mixed-Criticality Traffic Scheduler with Mitigating Congestion for CAN-to-TSN Gateway19
DTGx2: Dual Target Diagnostic Test Generation18
The Resistance Analysis Attack and Security Enhancement of the IMC LUT Based on the Complementary Resistive Switch Cells18
STRIVE: Empowering a Low Power Tensor Processing Unit with Fault Detection and Error Resilience18
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