IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Article	Citations
Architecture of Cobweb-Based Redundant TSV for Clustered Faults	130
An Efficient Hardware Accelerator for Structured Sparse Convolutional Neural Networks on FPGAs	68
High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell	66
Cryptographic Accelerators for Digital Signature Based on Ed25519	55
Flux-Controlled Memristor Emulator and Its Experimental Results	55
Mixed-Signal Computing for Deep Neural Network Inference	49
Low-Cost Stochastic Number Generators for Stochastic Computing	45
FPnew: An Open-Source Multiformat Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing	45
Stride 2 1-D, 2-D, and 3-D Winograd for Convolutional Neural Networks	40
ASSURE: RTL Locking Against an Untrusted Foundry	35
Practical Implementation of Multichannel Filtered-x Least Mean Square Algorithm Based on the Multiple-Parallel-Branch With Folding Architecture for Large-Scale Active Noise Control	35
Uni-OPU: An FPGA-Based Uniform Accelerator for Convolutional and Transposed Convolutional Networks	35
Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators	34
Design Methodology for Distributed Large-Scale ERSFQ Bias Networks	34
PLAC: Piecewise Linear Approximation Computation for All Nonlinear Unary Functions	34
PUF-Based Secure Chaotic Random Number Generator Design Methodology	33
Area-Efficient Nano-AES Implementation for Internet-of-Things Devices	33
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse	32
High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND	30
Design and Analysis of Approximate 4–2 Compressors for High-Accuracy Multipliers	29
In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands	28
Designing Novel AAD Pooling in Hardware for a Convolutional Neural Network Accelerator	27
High-Performance Spintronic Nonvolatile Ternary Flip-Flop and Universal Shift Register	27
Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates	26
SCOPE: Synthesis-Based Constant Propagation Attack on Logic Locking	26

Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory	25
A Twofold Lookup Table Architecture for Efficient Approximation of Activation Functions	25
GenMap: A Genetic Algorithmic Approach for Optimizing Spatial Mapping of Coarse-Grained Reconfigurable Architectures	24
Design Exploration of Energy-Efficient Accuracy-Configurable Dadda Multipliers With Improved Lifetime Based on Voltage Overscaling	24
Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes	23
A 0.6-V Power-Efficient Active-RC Analog Low-Pass Filter With Cutoff Frequency Selection	23
Analysis of the Impact of Process Variations and Manufacturing Defects on the Performance of Carbon-Nanotube FETs	22
Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT	22
A 2–24-GHz 360° Full-Span Differential Vector Modulator Phase Rotator With Transformer-Based Poly-Phase Quadrature Network	22
TxSim: Modeling Training of Deep Neural Networks on Resistive Crossbar Systems	21
Computing-in-Memory for Performance and Energy-Efficient Homomorphic Encryption	20
SWM: A High-Performance Sparse-Winograd Matrix Multiplication CNN Accelerator	20
TiM-DNN: Ternary In-Memory Accelerator for Deep Neural Networks	20
ADMM-Based Infinity-Norm Detection for Massive MIMO: Algorithm and VLSI Architecture	20
A Highly Unified Reconfigurable Multicore Architecture to Speed Up NTT/INTT for Homomorphic Polynomial Multiplication	20
Unified Analog PUF and TRNG Based on Current-Steering DAC and VCO	20
A 175.2-mW 4-Stage OTA With Wide Load Range (400 pF–12 nF) Using Active Parallel Compensation	20
A 0.5-V Multiple-Input Bulk-Driven OTA in 0.18-μm CMOS	20
Real-Time SSDLite Object Detection on FPGA	20
An Enhanced Input Differential Pair for Low-Voltage Bulk-Driven Amplifiers	20
ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators	19
Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System	19
Low-Power Retentive True Single-Phase-Clocked Flip-Flop With Redundant-Precharge-Free Operation	19
DAD-FF: Hardening Designs by Delay-Adjustable D-Flip-Flop for Soft-Error-Rate Reduction	19
A Highly Robust and Low-Power Real-Time Double Node Upset Self-Healing Latch for Radiation-Prone Applications	19
Very Fast, High-Performance 5-2 and 7-2 Compressors in CMOS Process for Rapid Parallel Accumulations	19
SIXOR: Single-Cycle In-Memristor XOR	18
Power Side-Channel Leakage Assessment Framework at Register-Transfer Level	18
Efficient Architectures for Multigigabit CCSDS LDPC Encoders	18
Design of Approximate Booth Squarer for Error-Tolerant Computing	18
Heterogeneous Mixed-Signal Monolithic 3-D In-Memory Computing Using Resistive RAM	18
Voltage Reference With Linear-Temperature-Dependent Power Consumption	18
SAT-Hard Cyclic Logic Obfuscation for Protecting the IP in the Manufacturing Supply Chain	18
A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push–Pull SS-PD and a Fast-Locking FLL Achieving −82.2-dBc REF Spur and −255-dB FOM	17
An Algorithm–Hardware Co-Optimized Framework for Accelerating N:M Sparse Transformers	17
GH CORDIC-Based Architecture for Computing $N$ th Root of Single-Precision Floating-Point Number	17
High-Performance COTS FPGA SoC for Parallel Hyperspectral Image Compression With CCSDS-123.0-B-1	17
An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FGPA Implementation	17
Parallel and Flexible 5G LDPC Decoder Architecture Targeting FPGA	17
A 1036-F2/Bit High Reliability Temperature Compensated Cross-Coupled Comparator-Based PUF	17
Machine-Learning-Based Self-Tunable Design of Approximate Computing	17
PVHArray: An Energy-Efficient Reconfigurable Cryptographic Logic Array With Intelligent Mapping	17
Physical Attack Protection Techniques for IC Chip Level Hardware Security	17
PCBChain: Lightweight Reconfigurable Blockchain Primitives for Secure IoT Applications	17
Reliable CRC-Based Error Detection Constructions for Finite Field Multipliers With Applications in Cryptography	17
Gain-Cell Embedded DRAM Under Cryogenic Operation—A First Study	16
Memristive Computational Memory Using Memristor Overwrite Logic (MOL)	16
Side-Channel Hardware Trojan for Provably-Secure SCA-Protected Implementations	16
Securing Hardware Accelerators for CE Systems Using Biometric Fingerprinting	16
Design and Implementation of Approximate DCT Architecture in Quantum-Dot Cellular Automata	16

FPGA Implementation of an Improved OMP for Compressive Sensing Reconstruction	16
A 35-GHz TX and RX Front End With High TX Output Power for Ka-Band FMCW Phased-Array Radar Transceivers in CMOS Technology	15
Design Space Exploration for Chiplet-Assembly-Based Processors	15
Dugdugi: An Optimal Fault Addressing Scheme for Octagon-Like On-Chip Communication Networks	15
A Reinforcement Learning-Based Framework for Solving the IP Mapping Problem	15
ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs	15
Efficient Error Detection Architectures for Postquantum Signature Falcon’s Sampler and KEM SABER	15
A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh	14
List-GRAND: A Practical Way to Achieve Maximum Likelihood Decoding	14
Power Distribution Attacks in Multitenant FPGAs	14
Low Power Unsupervised Anomaly Detection by Nonparametric Modeling of Sensor Statistics	14
Fast Binary Counters and Compressors Generated by Sorting Network	14
A 75-Gb/s/mm2 and Energy-Efficient LDPC Decoder Based on a Reduced Complexity Second Minimum Approximation Min-Sum Algorithm	14
High-Utilization, High-Flexibility Depth-First CNN Coprocessor for Image Pixel Processing on FPGA	14
True Random Number Generation Using Latency Variations of FRAM	14
Radiation-Hardened, Read-Disturbance-Free New-Quatro-10T Memory Cell for Aerospace Applications	14
A Compact Low-Voltage True Random Number Generator Based on Inkjet Printing Technology	14
Background Calibration of Bit Weights in Pipelined-SAR ADCs Using Paired Comparators	14
A Reconfigurable CMOS Rectifier With 14-dB Power Dynamic Range Achieving >36-dB/mm2 FoM for RF-Based Hybrid Energy Harvesting	13
A Second-Order Noise-Shaping SAR ADC Using Two Passive Integrators Separated by the Comparator	13
High-Throughput/Low-Energy MTJ-Based True Random Number Generator Using a Multi-Voltage/Current Converter	13
High-Precision PLL Delay Matrix With Overclocking and Double Data Rate for Accurate FPGA Time-to-Digital Converters	13
Soft Error Tolerant Convolutional Neural Networks on FPGAs With Ensemble Learning	13
An EEG-Based Hypnotic State Monitor for Patients During General Anesthesia	13
A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations	13
F-DNA: Fast Convolution Architecture for Deconvolutional Network Acceleration	13
Approximate Memory Compression	12
Designing Efficient and High-Performance AI Accelerators With Customized STT-MRAM	12
Cache-Out: Leaking Cache Memory Using Hardware Trojan	12
Memristors Enabled Computing Correlation Parameter In-Memory System: A Potential Alternative to Von Neumann Architecture	12
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation—Part I: CNFET Transistor Optimization	12
A Three-Stage Comparator and Its Modified Version With Fast Speed and Low Kickback	12
A Multirate Fully Parallel LDPC Encoder for the IEEE 802.11n/ac/ax QC-LDPC Codes Based on Reduced Complexity XOR Trees	12
A Timing Mismatch Background Calibration Algorithm With Improved Accuracy	12
VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative	12
Multisymbol Architecture of the Entropy Coder for H.265/HEVC Video Encoders	12
Spreading Operation Frequency Ranges of Memristor Emulators via a New Sine-Based Method	12
Performance and Accuracy Tradeoffs for Training Graph Neural Networks on ReRAM-Based Architectures	12
All-Digital Bandwidth Mismatch Calibration of TI-ADCs Based on Optimally Induced Minimization	12
A New Hardware-Efficient Spectrum-Sensor VLSI Architecture for Data-Fusion-Based Cooperative Cognitive-Radio Network	12
Anti-PVT-Variation Low-Power Time-to-Digital Converter Design Using 90-nm CMOS Process	12
Radiation-Hardened 0.3–0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications	12
A 32-Gb/s PAM-4 SST Transmitter With Four-Tap FFE Using High-Impedance Driver in 28-nm FDSOI	11
An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power	11
Efficient Execution of Temporal Convolutional Networks for Embedded Keyword Spotting	11
Low-Power, Low-Noise Edge-Race Comparator for SAR ADCs	11
Improving TID Radiation Robustness of a CMOS OxRAM-Based Neuron Circuit by Using Enclosed Layout Transistors	11
GreenTPU: Predictive Design Paradigm for Improving Timing Error Resilience of a Near-Threshold Tensor Processing Unit	11
FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators	11
A Radiation-Hardened CMOS Full-Adder Based on Layout Selective Transistor Duplication	11
Breaking Analog Locking Techniques	11
Area-Efficient Extended 3-D Inductor Based on TSV Technology for RF Applications	11
All-Digital CMOS Time-to-Digital Converter With Temperature-Measuring Capability	11
Benchmark of the Compute-in-Memory-Based DNN Accelerator With Area Constraint	11
Recurrent Neural Networks With Column-Wise Matrix–Vector Multiplication on FPGAs	11
AxPPA: Approximate Parallel Prefix Adders	11
An IP Core Mapping Algorithm Based on Neural Networks	11
A Hierarchical Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs	11
McPAT-Monolithic: An Area/Power/Timing Architecture Modeling Framework for 3-D Hybrid Monolithic Multicore Systems	11
HarTBleed: Using Hardware Trojans for Data Leakage Exploits	11
AdaTrust: Combinational Hardware Trojan Detection Through Adaptive Test Pattern Construction	11
Integer Codes Correcting Double Errors and Triple-Adjacent Errors Within a Byte	11
Formal Modeling of Network-on-Chip Using CFSM and its Application in Detecting Deadlock	10
NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators	10
Verification of Scheduling of Conditional Behaviors in High-Level Synthesis	10
MeNTT: A Compact and Efficient Processing-in-Memory Number Theoretic Transform (NTT) Accelerator	10
A 14-bit 200-Ms/s SHA-Less Pipelined ADC With Aperture Error Reduction	10
Analog and Mixed-Signal Layout Automation Using Digital Place-and-Route Tools	10
A 2.4-GHz Area-Efficient and Fast-Locking Subharmonically Injection-Locked Type-I PLL	10
A 215-F² Bistable Physically Unclonable Function With an ACF of <0.005 and a Native Bit Instability of 2.05% in 65-nm CMOS Process	10
Applying Thermal Side-Channel Attacks on Asymmetric Cryptography	10
A Configurable Floating-Point Multiple-Precision Processing Element for HPC and AI Converged Computing	10
Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits	10
A Multimode Configurable Physically Unclonable Function With Bit-Instability-Screening and Power-Gating Strategies	10
NeuPart: Using Analytical Models to Drive Energy-Efficient Partitioning of CNN Computations on Cloud-Connected Mobile Clients	10
A High-Performance SIKE Hardware Accelerator	10
Glitch-Optimized Circuit Blocks for Low-Power High-Performance Booth Multipliers	10
A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n- and p-type Flip-Flops	10
Accurate On-Chip Temperature Sensing for Multicore Processors Using Embedded Thermal Sensors	10
Time and Area Optimized Testing of Automotive ICs	10

Analysis of a Pipelined Architecture for Sparse DNNs on Embedded Systems	10
Analysis and Design of Current Mode Class-D Power Amplifiers With Finite Feeding Inductors	10
Ultralow-Power Localization of Insect-Scale Drones: Interplay of Probabilistic Filtering and Compute-in-Memory	10
Facial Biometric for Securing Hardware Accelerators	10
Analysis and Design of Unified Architectures for Zero-Attraction-Based Sparse Adaptive Filters	10
Scheduling of Data Access for the Radix-2k FFT Processor Using Single-Port Memory	10
Hardware Implementation of an OPC UA Server for Industrial Field Devices	9
Dynamic Workload Allocation for Edge Computing	9
A Programmable SoC-Based Accelerator for Privacy-Enhancing Technologies and Functional Encryption	9
A Multiring Julia Fractal Chaotic System With Separated-Scroll Attractors	9
Information Storage Bit-Flipping Decoder for LDPC Codes	9
Sub-1-V BGR and POR Hybrid Circuit With 2.25-μA Current Dissipation and Low Complexity	9
A 3.85-Gb/s 8 × 8 Soft-Output MIMO Detector With Lattice-Reduction-Aided Channel Preprocessing	9
Detecting Hardware Trojans in PCBs Using Side Channel Loopbacks	9
An Area-Efficient SAR ADC With Mismatch Error Shaping Technique Achieving 102-dB SFDR 90.2-dB SNDR Over 20-kHz Bandwidth	9
Hybrid Accumulator Factored Systolic Array for Machine Learning Acceleration	9
Nonscaling Adders and Subtracters for Stochastic Computing Using Markov Chains	9
Thermal-Aware Floorplanning and TSV-Planning for Mixed-Type Modules in a Fixed-Outline 3-D IC	9
Performance and Security Analysis of Parameter-Obfuscated Analog Circuits	9
A High-Performance LDO Regulator Enabling Low-Power SoC With Voltage Scaling Approaches	9
QEC: A Quantum Entropy Chip and Its Applications	9
A Conversion Mode Reconfigurable SAR ADC for Multistandard Systems	9
Revisiting Stochastic Computing in the Era of Nanoscale Nonvolatile Technologies	9
Interstice: Inverter-Based Memristive Neural Networks Discretization for Function Approximation Applications	9
A 0.506-pJ 16-kb 8T SRAM With Vertical Read Wordlines and Selective Dual Split Power Lines	9
Reliable Architectures for Finite Field Multipliers Using Cyclic Codes on FPGA Utilized in Classic and Post-Quantum Cryptography	9
A 16-kb 9T Ultralow-Voltage SRAM With Column-Based Split Cell-VSS, Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28-nm FDSOI	9
An Efficient Parallel DA-Based Fixed-Width Design for Approximate Inner-Product Computation	9
RPE-TCAM: Reconfigurable Power-Efficient Ternary Content-Addressable Memory on FPGAs	9
Low-Supply Sensitivity LC VCOs With Complementary Varactors	9
A 23–36.8-GHz Low-Noise Frequency Synthesizer With a Fundamental Colpitts VCO Array in SiGe BiCMOS for 5G Applications	8
Secure XOR-CIM Engine: Compute-In-Memory SRAM Architecture With Embedded XOR Encryption	8
Optimizing FPGA Logic Circuitry for Variable Voltage Supplies	8
Fast and Accurate Estimation of Statistical Eye Diagram for Nonlinear High-Speed Links	8
Optimizing FPGA Logic Block Architectures for Arithmetic	8
Programmable Daisychaining of Microelectrodes to Secure Bioassay IP in MEDA Biochips	8
A High-Speed Low-Noise Comparator With Auxiliary-Inverter-Based Common Mode-Self-Regulation for Low-Supply-Voltage SAR ADCs	8
Efficient Performance Modeling for Automated CMOS Analog Circuit Synthesis	8
FN-CACTI: Advanced CACTI for FinFET and NC-FinFET Technologies	8
Cerebron: A Reconfigurable Architecture for Spatiotemporal Sparse Spiking Neural Networks	8
A VLSI Majority-Logic Device Based on Spin Transfer Torque Mechanism for Brain-Inspired Computing Architecture	8
A Power Analysis Attack Resistant Multicore Platform With Effective Randomization Techniques	8
A Time-Domain Reconfigurable Second-Order Noise Shaping ADC With Single Fan-Out Gated Delay Cells	8
A Hybrid Miller-Cascode Compensation for Fast Settling in Two-Stage Operational Amplifiers	8
Dataflow-Aware Macro Placement Based on Simulated Evolution Algorithm for Mixed-Size Designs	8
PWL-Based Architecture for the Logarithmic Computation of Floating-Point Numbers	8
VCO-Based Comparator: A Fully Adaptive Noise Scaling Comparator for High-Precision and Low-Power SAR ADCs	8
An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC	8
An Area-Efficient High-Resolution Segmented ΣΔ-DAC for Built-In Self-Test Applications	8
A Fast Leakage-Aware Green’s-Function-Based Thermal Simulator for 3-D Chips	8
SCERPA Simulation of Clocked Molecular Field-Coupling Nanocomputing	8
Machine Learning Attack Resistant Area-Efficient Reconfigurable Ising-PUF	7
Variation-Aware Delay Fault Testing for Carbon-Nanotube FET Circuits	7
A 0.3 nW, 0.093%/V Line Sensitivity, Temperature Compensated Bulk-Programmable Voltage Reference for Wireless Sensor Nodes	7
On Efficiency Enhancement of SHA-3 for FPGA-Based Multimodal Biometric Authentication	7
A 300-mV Auto Shutdown Comparator-Based Continuous Time Δ∑ Modulator	7
Exploring the Design of Energy-Efficient Intermittently Powered Systems Using Reconfigurable Ferroelectric Transistors	7
High-Performance Concatenation Decoding of Reed–Solomon Codes With SPC Codes	7
High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors	7
A Ku-Band Eight-Element Phased-Array Transmitter With Built-in Self-Test Capability in 180-nm CMOS Technology	7
RNN-Based Radio Resource Management on Multicore RISC-V Accelerator Architectures	7
Hard-to-Detect Fault Analysis in FinFET SRAMs	7
A −20-dBm Sensitivity RF Energy-Harvesting Rectifier Front End Using a Transformer IMN	7
An Optimized M-Term Karatsuba-Like Binary Polynomial Multiplier for Finite Field Arithmetic	7
ARXON: A Framework for Approximate Communication Over Photonic Networks-on-Chip	7
A Low-Power PAM4 Receiver With an Adaptive Variable-Gain Rectifier-Based Decoder	7
A 4.4-mA ESD-Safe 900-MHz LNA With 0.9-dB Noise Figure	7
EM Side-Channel Countermeasure for Switched-Capacitor DC–DC Converters Based on Amplitude Modulation	7
A Pre-Activation, Golden IC Free, Hardware Trojan Detection Approach	7
Design of FPGA-Implemented Reed–Solomon Erasure Code (RS-EC) Decoders With Fault Detection and Location on User Memory	7
A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI	7
Efficient Register Renaming Architectures for 8-bit AES Datapath at 0.55 pJ/bit in 16-nm FinFET	7
A 12-Bit Two-Step Single-Slope ADC With a Constant Input-Common-Mode Level Resistor Ramp Generator	7
Energy-Efficient Logarithmic Square Rooter for Error-Resilient Applications	7
Development of a Short-Term to Long-Term Supervised Spiking Neural Network Processor	7
Golden-Free Hardware Trojan Detection Using Self-Referencing	7
THETA: A High-Efficiency Training Accelerator for DNNs With Triple-Side Sparsity Exploration	7
Efficient Implementation of Dilithium Signature Scheme on FPGA SoC Platform	7
Communication-Aware Task Scheduling for Energy-Harvesting Nonvolatile Processors	7
An Ultralow-Power OOK/BFSK/DBPSK Wake-Up Receiver Based on Injection-Locked Oscillator	7
A Generalized Power Supply Induced Jitter Model Based on Power Supply Rejection Ratio Response	7
Alternatives to Bicubic Interpolation Considering FPGA Hardware Resource Consumption	7
On Fast and Exact Computation of Error Metrics in Approximate LSB Adders	7
An M-Cache-Based Security Monitoring and Fault Recovery Architecture for Embedded Processor	7
High-Dimensional Many-Objective Bayesian Optimization for LDE-Aware Analog IC Sizing	7
Fast Modular Multipliers for Supersingular Isogeny-Based Post-Quantum Cryptography	7
A 0.3-V 8.5-μ a Bulk-Driven OTA	7
CapCAM: A Multilevel Capacitive Content Addressable Memory for High-Accuracy and High-Scalability Search and Compute Applications	7
Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process	7
An Error Compensation Technique for Low-Voltage DNN Accelerators	7
IMCA: An Efficient In-Memory Convolution Accelerator	7
CRC-Based Error Detection Constructions for FLT and ITA Finite Field Inversions Over GF(2 m )	7
Differential Aging Sensor Using Subthreshold Leakage Current to Detect Recycled ICs	7
SALE: Smartly Allocating Low-Cost Many-Bit ECC for Mitigating Read and Write Errors in STT-RAM Caches	6
pMOS Pass Gate Local Bitline SRAM Architecture With Virtual $V_{\mathrm{SS}}$ for Near-Threshold Operation	6