IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Article	Citations
Droplet Transportation in MEDA-Based Biochips: An Enhanced Technique for Intelligent Cross-Contamination Avoidance	94
Call for Applications and Nominations Search for the Editor-in-Chief of IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS	63
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	52
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	39
HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization	38
Identifying Optimal Workload Offloading Partitions for CPU-PIM Graph Processing Accelerators	38
Hardware–Algorithm Codesigned Low-Latency and Resource-Efficient OMP Accelerator for DOA Estimation on FPGA	34
M2-ViT: Accelerating Hybrid Vision Transformers With Two-Level Mixed Quantization	34
Bandwidth-Latency-Thermal Co-Optimization of Interconnect-Dominated Many-Core 3D-IC	32
A Novel Prediction-Based Two-Tiered ECC for Mitigating SWD Errors in HBM	31
Research on Hardware Acceleration of Traffic Sign Recognition Based on Spiking Neural Network and FPGA Platform	31
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	31
Edge PoolFormer: Modeling and Training of PoolFormer Network on RRAM Crossbar for Edge-AI Applications	29
Improved Step-GRAND: Low-Latency Soft-Input Guessing Random Additive Noise Decoding	29
An Efficient and Precision-Reconfigurable Digital CIM Macro for DNN Accelerators	28
Table of contents	26
TechRxiv: Share Your Preprint Research with the World!	26
AxPPA: Approximate Parallel Prefix Adders	25
A 0.3-V 8.5-μ a Bulk-Driven OTA	25
An Enhanced Input Differential Pair for Low-Voltage Bulk-Driven Amplifiers	25
IEEE Transactions on Very Large Scale Integration (VLSI) Systems	25
Detection of Recycled ICs Using Backscattering Side-Channel Analysis	24
Efficient Error Detection Architectures for Postquantum Signature Falcon’s Sampler and KEM SABER	24
Design and Analysis of Sub-Sampling Phase-Locked Loop for Quantum Computing	23
Table of Contents	23

DRC Violation Prediction After Global Route Through Convolutional Neural Network	23
OPTIMA: An Approach for Online Management of Cache Approximation Levels in Approximate Processing Systems	23
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	23
Single Test Type to Replace Broadside and Skewed-Load Tests for Transition Faults	22
Corrections to “Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator” [Jul 23 1078-1082]	22
VLSI Design of a High-Performance Multicontext MQ Arithmetic Coder	22
A 5-mm2, 4.7-μW Convolutional Neural Network Layer Accelerator for Miniature Systems	21
An Efficient CNN Accelerator Achieving High PE Utilization Using a Dense-/Sparse-Aware Redundancy Reduction Method and Data–Index Decoupling Workflow	21
IMCA: An Efficient In-Memory Convolution Accelerator	21
Table of Contents	20
A 24–40-GHz Broadband Beamforming TRX Front-End IC With Unified Phase and Gain Control for Multiband Phased Array Systems	20
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	20
A Fast Cross-Layer Dynamic Power Estimation Method by Tracking Cycle-Accurate Activity Factors With Spark Streaming	20
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	20
Design Exploration of Fault-Tolerant Deep Neural Networks Using Posit Number Representation System	20
A Reconfigurable Neural Network Processor With Tile-Grained Multicore Pipeline for Object Detection on FPGA	20
A 10-Gb/s Inductorless Low-Power TIA With a 400-fF Low-Speed Avalanche Photodiode Realized in CMOS Process	19
A MOS-DTMOS Implementation of Floating Memristor Emulator for High-Frequency Applications	18
Another Look at Side-Channel-Resistant Encoding Schemes	17
Write–Verify-Free MLC RRAM Using Nonbinary Encoding for AI Weight Storage at the Edge	17
IEEE Transactions on Very Large Scale Integration (VLSI) Systems	17
Table of Contents	17
Adaptable Approximate Multiplier Design Based on Input Distribution and Polarity	17
Low-Power Retentive True Single-Phase-Clocked Flip-Flop With Redundant-Precharge-Free Operation	17
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	16
A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation	16
A Fully Digital SRAM-Based Four-Layer In-Memory Computing Unit Achieving Multiplication Operations and Results Store	16
iEDCL: Streamlined, False-Error-Free Error Detection and Correction Scheme in a Near-Threshold Enabled 32-bit Processor	16
Novel Formulations of M-Term Overlap-Free Karatsuba Binary Polynomial Multipliers and Their Hardware Implementations	16
A Reliable and Efficient Online Solution for Adaptive Voltage and Frequency Scaling on FPGAs	15
A Three-Stage Comparator and Its Modified Version With Fast Speed and Low Kickback	15
On the Resiliency of Protected Masked S-Boxes Against Template Attack in the Presence of Temperature and Aging Misalignments	15
An Electrical-Thermal Co-Simulation Model of Chiplet Heterogeneous Integration Systems	15
ABS: Accumulation Bit-Width Scaling Method for Designing Low-Precision Tensor Core	15
A 20-V Pulse Driver Based on All-nMOS Charge Pump Without Reversion Loss and Overstress in 65-nm Standard CMOS Technology	14
IEEE Transactions on Very Large Scale Integration (VLSI) Systems	14
Behavioral Model for High-Speed SAR ADCs With On-Chip References	14
A High-Precision and High-Dynamic-Range Current-Mode WTA Circuit for Low-Supply-Voltage Applications	14
Securing Against Side-Channel Attacks With Wide-Range In Situ Random Voltage Dithering on Async-Logic AES Engine	14
Table of contents	14
CEVGMM: Computationally Efficient Versatile Generic Memristor Model	14
Protecting Parallel Data Encryption in Multi-Tenant FPGAs by Exploring Simple but Effective Clocking Methodologies	14
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	14
IEEE Transactions on Very Large Scale Integration (VLSI) Systems	14
An Injection-Locked and Sub-Sampling Clock Multiplier With a Two-Step SC DAC Achieving 2.67% Jitter Variation	14
Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs	13
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	13
THETA: A High-Efficiency Training Accelerator for DNNs With Triple-Side Sparsity Exploration	13
IPOCIM: Artificial Intelligent Architecture Design Space Exploration With Scalable Ping-Pong Computing-in-Memory Macro	13
Functional Test Sequences as a Source for Partially Functional Launch-on-Shift Tests	13

Enabling Write-Reduction Multiversion Scheme With Efficient Dual-Range Query Over NVRAM	13
A Programmable and Reconfigurable CMOS Analog Hopfield Network for NP-Hard Problems	13
A Design of 12.8-Gpixels/s Hardware-Efficient Lossless Embedded Compression Engine for Video Coding Applications	13
Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches	12
Microarchitecture Design Space Exploration via Pareto-Driven Active Learning	12
A Parallel Architecture and Implementation for Near-Lossless Hyperspectral Image Compression Based on CCSDS 123.0-B-2 With Scalable Data-Rate Performance	12
Analysis and Design of Magnetically Tuned W -Band Oscillators	12
An Energy-Efficient Spiking Neural Network Accelerator Based on Spatio-Temporal Redundancy Reduction	12
Reconfigurable Stateful Logic Circuit With Cu/CuI/Pt Memristors for In-Memory Computing	12
A Low-Power Co-Processor to Predict Ventricular Arrhythmia for Wearable Healthcare Devices	12
Fast Search and Efficient Placement Algorithm for Reconfigurable Tasks on Modern Heterogeneous FPGAs	11
Functional Constraints in the Selection of Two-Cycle Gate-Exhaustive Faults for Test Generation	11
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	11
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	11
Signal and Power Integrity IO Buffer Modeling Under Separate Power and Ground Supply Voltage Variation of the Input and Output Stages	11
An Algorithm–Hardware Co-Optimized Framework for Accelerating N:M Sparse Transformers	11
Hard-to-Detect Fault Analysis in FinFET SRAMs	11
Hidden Costs of Analog Deobfuscation Attacks	11
A Ku-Band Eight-Element Phased-Array Transmitter With Built-in Self-Test Capability in 180-nm CMOS Technology	11
IMCRYPTO: An In-Memory Computing Fabric for AES Encryption and Decryption	11
Table of Contents	11
Dummy Faulty Units for Reduced Fail Data Volume From Logic Faults	11
X-Former: In-Memory Acceleration of Transformers	11
A 12.93–16 Gb/s Reference-Less Baud-Rate CDR Circuit With One-Tap DFE and Semirotational Frequency Detection	10
A Code-Recombination Algorithm-Based ADC With Feature Extraction for WBSN Applications	10
Diagnostic Test Point Insertion and Test Compaction	10
FPGA Crystal Oscillator Circuit Emulation Based on Wave Digital Filter	10
TrustGuard: Standalone FPGA-Based Security Monitoring Through Power Side-Channel	10
Training Accelerator for Two Means Decision Tree	10
An Energy-Efficient Conditional Biasing Write Assist With Built-In Time-Based Write-Margin-Tracking for Low-Voltage SRAM	10
A Current-Adjusting Auto-Zeroing Technique for DC-Offset and Flicker-Noise Cancellation	10
An Efficient Hard-Detection GRAND Decoder for Systematic Linear Block Codes	10
Performance and Energy Studies on NC-FinFET Cache-Based Systems With FN-McPAT	10
FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators	10
Rowhammer Vulnerability of DRAMs in 3-D Integration	10
A Novel Design Approach and VLSI Architecture of Rationalized Bi-Orthogonal Wavelet Filter Banks	10
A Single-Chip Solution for Diagnosing Peripheral Arterial Disease	10
Built-In Self-Test of High-Density and Realistic ILV Layouts in Monolithic 3-D ICs	10
Layout-Aware Area Optimization of Transposable STT-MRAM for a Processing-In-Memory System	10
RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache Systems	10
Decap Insertion With Local Cell Relocation Minimizing IR-Drop Violations and Routing DRVs	10
Graceful Degradation of Reconfigurable Scan Networks	10
Soft Error Tolerant Convolutional Neural Networks on FPGAs With Ensemble Learning	9
Minimizing the Maximum Processor Temperature by Temperature-Aware Scheduling of Real-Time Tasks	9
Guest Editorial Selected Papers From IEEE Nordic Circuits and Systems Conference (NorCAS) 2023	9
Timing Variability-Aware Analysis and Optimization for Variable-Latency Designs	9
A Reusable and Efficient Architecture for QC-LDPC Encoder With Less Expansion Factors	9
Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System	9
A Masked Hardware Accelerator for Feed-Forward Neural Networks With Fixed-Point Arithmetic	9
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	9
A Low-Power Timing-Error-Tolerant Circuit by Controlling a Clock	9
Built-In Self-Repair of Small Delay Faults Occurring to TSVs in a 3D-DRAM Using an Enhanced Pulse-Vanishing Test	9
A Tri-Mode Reconfigurable Receiver for GNSS/NB-IoT/BLE With 68-dB HR3 and 60-dB IMRR in 28-nm CMOS	9
A 3.85-Gb/s 8 × 8 Soft-Output MIMO Detector With Lattice-Reduction-Aided Channel Preprocessing	9
On Continuing DNN Accelerator Architecture Scaling Using Tightly Coupled Compute-on-Memory 3-D ICs	9
NS3K: A 3-nm Nanosheet FET Standard Cell Library Development and its Impact	9
Table of Contents	9
A Simplified Vector-Sum Phase Shifter Topology With Low Noise Figure and High Voltage Gain	9
A Reconfigurable CMOS Stack Rectifier With 22.8-dB Dynamic Range Achieving 47.91% Peak PCE for IoT/WSN Application	9
Testability Evaluation for Local Design Modifications	9
Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process	9
Efficient Design of Majority-Logic-Based Approximate Arithmetic Circuits	9
MeNTT: A Compact and Efficient Processing-in-Memory Number Theoretic Transform (NTT) Accelerator	9
Table of Contents	9
Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT	8
Sophon: A Time-Repeatable and Low-Latency Architecture for Embedded Real-Time Systems Based on RISC-V	8
Heterogeneous Mixed-Signal Monolithic 3-D In-Memory Computing Using Resistive RAM	8
Half-Precision Logarithmic Arithmetic Unit Based on the Fused Logarithmic and Antilogarithmic Converter	8
RosebudVirt: A High-Performance and Partially Reconfigurable FPGA Virtualization Framework for Multitenant Networks	8
A Novel Two-Stage Timing Mismatch Calibration Technique for Time-Interleaved ADCs	8
Low-Overhead Triple-Node-Upset-Tolerant Latch Design in 28-nm CMOS	8
Data Criticality in Multithreaded Applications: An Insight for Many-Core Systems	8
ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator	8
An Optimized M-Term Karatsuba-Like Binary Polynomial Multiplier for Finite Field Arithmetic	8
FPUx: High-Performance Floating-Point Support for Cost-Constrained RISC-V Cores	8
ArXrCiM: Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory	8
A Hybrid Domain and Pipelined Analog Computing Chain for MVM Computation	8
Physical Attack Protection Techniques for IC Chip Level Hardware Security	8
A Generic Dynamic Responding Mechanism and Secure Authentication Protocol for Strong PUFs	8
A Sparse CNN Accelerator for Eliminating Redundant Computations in Intra- and Inter-Convolutional/Pooling Layers	8

An Efficient High-Throughput Structured-Light Depth Engine	8
Analysis and Design of Ripple-Free Bandgap Reference Circuit With p-n-p Bipolars	8
An End-to-End Bundled-Data Asynchronous Circuits Design Flow: From RTL to GDS	8
Design of an S-ECIES Cryptoprocessor Using Gaussian Normal Bases Over GF(2 m )	8
FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Networks With Efficient DSP and Memory Optimization	8
Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes	8
55–100-GHz Enhanced Gilbert Cell Mixer Design in 22-nm FDSOI CMOS	7
High-Accuracy and Low-Multiplication Recursive Discrete Cosine Transform Algorithm Design and Its Realization in Mel-Scale Frequency Cepstral Coefficients	7
Timestamp-Based Secure Shield Architecture for Detecting Invasive Attacks	7
A High-Speed Dynamic Element Matching Decoder With Integrated Background Calibration Control	7
Dual-Rail Precharge Logic-Based Side-Channel Countermeasure for DNN Systolic Array	7
Unveiling the True Power of the Latched Ring Oscillator for a Unified PUF and TRNG Architecture	7
A CMOS Readout Circuit for Resistive Tactile Sensor Array Using Crosstalk Suppression and Nonuniformity Compensation Techniques	7
Exposing Reliability Degradation and Mitigation in Approximate DNNs Under Permanent Faults	7
A Hybrid RO-TDL-Based On-Chip Voltage Monitor for FPGA Applications	7
Low-Latency PAPR Reduction Architecture for Discrete Multitone Based on Approximate Midrange	7
An On-Chip Low-Cost Averaging Digital Sampling Scope for 80-GS/s Measurement of Wireline Pulse Responses	7
A 206 μW Vital Signs Monitoring System on Chip for Measuring Five Vitals	7
Multidie 3-D Stacking of Memory Dominated Neuromorphic Architectures	7
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	7
SiPGuard: Run-Time System-in-Package Security Monitoring via Power Noise Variation	7
De-Embedding Methodology to Characterize Linearity of Active Filters Under Process Variations	7
An Efficient Test Architecture Using Hybrid Built-In Self-Test for Processing-in-Memory	7
A Quad-Core VCO Incorporating Area-Saving Folded S-Shaped Tail Filtering in 28-nm CMOS	7
A New ACD-OMP Accelerator With Clustered Computing Look-Ahead	7
MCAIMem: A Mixed SRAM and eDRAM Cell for Area and Energy-Efficient On-Chip AI Memory	7
Endurance-Aware Compiler for 3-D Stackable FeRAM as Global Buffer in TPU-Like Architecture	7
Retry-Based Synchronization for Online Testing of Identical Logic Blocks	7
GNN-Based Hardware Trojan Detection at Register Transfer Level Leveraging Multiple-Category Features	7
Online Fault Detection in ReRAM-Based Computing Systems for Inferencing	7
FPGA Implementation of Staged Projection Refining Multiple Orthogonal Matching Pursuit Algorithm for Compressed Sensing	7
A Methodology for Datapath Energy Prediction and Optimization in Near Threshold Voltage Regime	7
Editorial New Beginnings for IEEE TVLSI	6
Area-Efficient Parallel Multiplication Units for CNN Accelerators With Output Channel Parallelization	6
Reliability Evaluation and Fault Tolerance Design for FPGA Implemented Reed Solomon (RS) Erasure Decoders	6
A Miniaturized Wideband Interdigital Bandpass Filter With High Out-Band Suppression Based on TSV Technology for W-Band Application	6
A Fully Integrated 10-V Pulse Driver Using Multiband Pulse-Frequency Modulation in 65-nm CMOS	6
Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis	6
Via-Avoidance-Oriented Interposer Routing for Layer Minimization in 2.5-D IC Designs	6
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	6
Design of FPGA-Implemented Reed–Solomon Erasure Code (RS-EC) Decoders With Fault Detection and Location on User Memory	6
Test Methodology for Defect-Based Bridge Faults	6
Table of Contents	6
Enabling a New Methodology of Neural Coding: Multiplexing Temporal Encoding in Neuromorphic Computing	6
A Temperature Compensated Ring Oscillator With LC-Based Period Error Detection	6
RISE: RISC-V SoC for En/Decryption Acceleration on the Edge for Homomorphic Encryption	6
A 24-Gb/s MIPI C-/D-PHY Receiver Bridge Chip With Phase Error Calibration Supporting FPGA-Based Frame Grabber	6
Power-Efficient VLSI Architecture of a New Class of Dyadic Gabor Wavelets for Medical Image Retrieval	6
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	6
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation—Part I: CNFET Transistor Optimization	6
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	6
Increase Your Knowledge of Technical Standards	6
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	6
Noise Analysis and Design Methodology of Chopper Amplifiers With Analog DC-Servo Loop for Biopotential Acquisition Applications	6
Analysis and Design of a DC-12-GHz Distribution Power Amplifier for Quantum Key Distribution Application	6
A Wide-Range All-Digital Delay-Locked Loop for DDR1–DDR5 Applications	6
A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations	6
Bit-Complemented Test Data to Replace the Tail of a Fault Coverage Curve	6
Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation	6
Table of Contents	6
Streaming Dilated Convolution Engine	6
Table of Contents	6
An 8.55–17.11-GHz DDS FMCW Chirp Synthesizer PLL Based on Double-Edge Zero-Crossing Sampling PD With 51.7-fsrms Jitter and Fast Frequency Hopping	6
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	6
A Vector Processor for Mean Field Bayesian Channel Estimation	5
Table of contents	5
Table of Contents	5
IEEE Transactions on Very Large Scale Integration (VLSI) Systems	5
A Rail-to-Rail Transconductance Amplifier Based on Current Generator Circuits	5
Estimating Redundancy-Reliability of CNNs Based on Strip-Median Attributes	5
PALS: Distributed Gradient Clocking on Chip	5
Miniaturization Strategy for Directional Couplers Based on Through-Silicon Via Insertion and Neuro-Transfer Function Modeling Method	5
CR-DRAM: Improving DRAM Refresh Energy Efficiency With Inter-Subarray Charge Recycling	5
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	5
IEEE Transactions on Very Large Scale Integration (VLSI) Systems	5
Clock Delivery Network Design and Analysis for Interposer-Based 2.5-D Heterogeneous Systems	5
Allocation of Always-On State Retention Storage for Power Gated Circuits—Steady-State- Driven Approach	5
IEEE Women in Engineering	5
Cost-Effective Analytical Models of Resistive Opens Defects in FinFET Technology	5
High Restore Yield NVSRAM Structures With Dual Complementary RRAM Devices for High-Speed Applications	5
High-Density NVMe SSD With DRAM-Less eRAID Architecture	5
An 8-bit 1.5-GS/s Two-Step SAR ADC With Embedded Interstage Gain	5
Designing Precharge-Free Energy-Efficient Content-Addressable Memories	5
High-Performance Concatenation Decoding of Reed–Solomon Codes With SPC Codes	5
Improving a Ka-Band Integrated Balanced Power Amplifier Performance by Compensating Quadrature Hybrid Mismatch Effects	5
Stochastic Computing Using Amplitude and Frequency Encoding	5
Table of contents	5
Connect. Support. Inspire.	5
RCU-$2^m$: A VLSI Radix-$2^m$ Cubic Unit	5
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	5
Test Sequences for Faults in the Scan Logic	5
Synthesis of Approximate Parallel-Prefix Adders	5
Static-Linearity Enhancement Techniques for Digital-to-Analog Converters Exploiting Optimal Arrangements of Unit Elements	5
Table of Contents	5
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	5