IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Article	Citations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	75
Call for Applications and Nominations Search for the Editor-in-Chief of IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS	70
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	66
A High-Performance SCNN Accelerator Using Parallel Sparsity Detection and Index-Oriented Computation Workflow	64
A Trifilar Transformer-Based Class-F23 VCO With Noise-Circulating Technology	62
Table of Contents	58
Behavioral Model for High-Speed SAR ADCs With On-Chip References	57
Diagnostic Test Point Insertion and Test Compaction	52
ABS: Accumulation Bit-Width Scaling Method for Designing Low-Precision Tensor Core	51
High-Precision Low-Latency Method and Architecture for Computing Binary and Decimal Logarithms	48
Experimental Demonstration of Stochastic Bayesian Inference Using Müller C-Elements	45
HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization	43
A Parallel Architecture and Implementation for Near-Lossless Hyperspectral Image Compression Based on CCSDS 123.0-B-2 With Scalable Data-Rate Performance	43
Improved Step-GRAND: Low-Latency Soft-Input Guessing Random Additive Noise Decoding	43
Signal and Power Integrity IO Buffer Modeling Under Separate Power and Ground Supply Voltage Variation of the Input and Output Stages	43
Low-Overhead Triple-Node-Upset-Tolerant Latch Design in 28-nm CMOS	42
A Generalized Design Methodology for Multi-Input Collaborative-Flip Synchronized Switch Harvesting on Capacitors: From Theory to Optimization Strategy	41
Countering Side-Channel Attacks With a Dynamic S-Box Based on Affine Transformations and Gold Sequences	40
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	39
A Generic Dynamic Responding Mechanism and Secure Authentication Protocol for Strong PUFs	39
FARMER: Online-Learning-Based Workload Consolidation on Large FPGAs Accelerated With Dynamic Partial Reconfiguration	38
VLSI Architecture for an Adaptive Transmission Estimation-Based Video Dehazing Method	35
Analysis and Design of Magnetically Tuned W -Band Oscillators	34
Built-In Self-Test of High-Density and Realistic ILV Layouts in Monolithic 3-D ICs	34
RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache Systems	34

A Fast and Energy-Efficient Level Shifter With Complementary Output Buffer for Energy-Constrained Systems	33
Efficient SoC Power Estimation With Machine Learning	33
A High-Speed Dynamic Element Matching Decoder With Integrated Background Calibration Control	31
Hidden Costs of Analog Deobfuscation Attacks	31
An Efficient VLSI Architecture for Hammerstein-Type Spline Adaptive Filters	30
Defect-Aware Built-In Self-Test and Dynamic Repair for Fan-Out Wafer-Level Packaging	30
ASTRA: Automated Insertion of Distributed Entropy Sources for Robust Authentication	30
Highly Stable Reconfigurable TERO PUF Architecture for Hardware Security Applications	30
Protecting Parallel Data Encryption in Multi-Tenant FPGAs by Exploring Simple but Effective Clocking Methodologies	29
A 12-bit 2-GS/s Pipeline ADC in 28-nm CMOS With Linear-Error Self-Calibration	29
Table of Contents	28
ZuSE-KI-Mobil: AI Chip Design Platform for Automotive and Industrial Applications	28
Upscale Layer Acceleration on Existing AI Hardware	27
A Dual-Mode Buck Converter with Light-Load Efficiency Improvement and Seamless Mode Transition Technique	27
Estimating Redundancy-Reliability of CNNs Based on Strip-Median Attributes	27
A 28-nm 9-kb SRAM Computing-in-Memory Macro With Segmented Charge Sharing for Multimode MAC Operations	27
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	27
IEEE Women in Engineering	26
Analyzing the Vulnerabilities of External SDRAM on System-on-Chip Field Programmable Gate Array Devices	26
Editorial New Beginnings for IEEE TVLSI	26
A 370-nW Bio-AFE With 2.9-μ Vrms Input Noise in an Octa-Channel System-in-Package for Multimode Bio-Signal Acquisition	26
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	26
A Sub-0.9-ps Static Phase Offset 500 MHz Delay-Locked Loop With a Large Gain Phase Detector	25
A Reconfigurable CMOS Rectifier With 14-dB Power Dynamic Range Achieving >36-dB/mm2 FoM for RF-Based Hybrid Energy Harvesting	25
Cost-Effective Analytical Models of Resistive Opens Defects in FinFET Technology	24
Test Sequences for Faults in the Scan Logic	24
Test Methodology for Defect-Based Bridge Faults	24
Analysis and Design of a DC-12-GHz Distribution Power Amplifier for Quantum Key Distribution Application	24
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	23
In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays	23
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	23
Test Data Compression for Transparent-Scan Sequences	23
Robust Security of Hardware Accelerators Using Protein Molecular Biometric Signature and Facial Biometric Encryption Key	23
SPICED+: Syntactical Bug Pattern Identification and Correction of Trojans in A/MS Circuits Using LLM-Enhanced Detection	22
Bayesian Model Calibration for Deep-Learning-Based Indirect Test of Analog Circuits	22
A Cryogenic 2T GC-eDRAM With an Inverter-Based Readout Scheme and an 80 ms Retention Time	22
Page Type-Aware Data Migration Technique for Read Disturb Management of NAND Flash Memory	22
PERA: Power-Efficient Routing Architecture for SRAM-Based FPGAs in Dark Silicon Era	22
High-Reliability and High-Throughput CIM 10T-SRAM for Multiplication and Accumulation Operations With 274.3 GOPS and 200–237.5 TOPS/W	22
Metal Stack Exploration for Front- Versus Back- Side Clock and Signal Allocation for Advanced CMOS PPA Improvements	22
Power Side-Channel Leakage Assessment Framework at Register-Transfer Level	22
RISE: RISC-V SoC for En/Decryption Acceleration on the Edge for Homomorphic Encryption	21
High Restore Yield NVSRAM Structures With Dual Complementary RRAM Devices for High-Speed Applications	21
FeFET Local Multiply and Global Accumulate Voltage-Sensing Computation-In-Memory Circuit Design for Neuromorphic Computing	21
An Optimized Low-Power VLSI Architecture for ECG/VCG Data Compression for IoHT Wearable Device Application	21
Test Primitives: The Unified Notation for Characterizing March Test Sequences	20
A 36-Gb/s 2× Half-Baud-Rate Adaptive Receiver in 28-nm CMOS	20
FAMS: A FrAmework of Memory-Centric Mapping for DNNs on Systolic Array Accelerators	20
An Ultralow-Energy Voltage Level Shifter With an Output-Cycle-Based Dynamic Biasing Scheme in a 130-nm CMOS Technology	20
Adaptive Machine Learning-Based Proactive Thermal Management for NoC Systems	20

Efficient ORBGRAND Implementation With Parallel Noise Sequence Generation	19
An Efficient NVM-Based Architecture for Intermittent Computing Under Energy Constraints	19
CINELL: An Energy-Efficient Compute-In/Near-Memory eDRAM Processor for Sparse Transformer-Based Large Language Models	19
A Sample-and-Hold-Based 453-ps True Time Delay Circuit With a Wide Bandwidth of 0.5–2.5 GHz in 65-nm CMOS	19
A 0.3 nW, 0.093%/V Line Sensitivity, Temperature Compensated Bulk-Programmable Voltage Reference for Wireless Sensor Nodes	19
A 4.86-pJ/b Energy-Efficient Fully Parallel Stochastic LDPC Decoder With Two-Stage Shared Memory	19
A Twofold Clock and Voltage-Based Detection Method for Laser Logic State Imaging Attack	18
A Study on Nonlinearity in Mixers Using a Time-Varying Volterra-Based Distortion Contribution Analysis Tool	18
A High-Performance Low-Power Double-Node Upset Resilient Latch for Harsh Radiation Environments	18
A 9T SRAM Computation-in-Memory Architecture With High-Precision MAC, Enhanced Bitline Voltage Margin, and Improved Frequency Performance Over Conventional Architectures	18
FLAT: Layout-Aware and Security Property-Assisted Timing Fault-Injection Attack Assessment	18
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	18
A 2.5-MHz BW, 75-dB SNDR Noise-Shaping SAR ADC With a 1st-Order Hybrid EF-CIFF Structure Assisted by Unity-Gain Buffer	18
Area-Efficient Pipeline Architecture for Serial Real-Valued Fast Fourier Transform	17
BSSE: Design Space Exploration on the BOOM With Semi-Supervised Learning	17
FELIX: FPGA-Based Scalable and Lightweight Accelerator for Large Integer Extended GCD	17
A Reconfigurable Multiple Transform Selection Architecture for VVC	17
A Fully Integrated Storage-Free Energy Harvesting System With Voltage Self-Regulation and Dual-Channel Power Extraction	17
DSHD-CAM: High-Throughput RRAM CAM Leveraging Dynamic Shifted Hamming Distance for Genome Analysis	17
MRFI: An Open-Source Multiresolution Fault Injection Framework for Neural Network Processing	17
A Fast Transient Response Distributed Power Supply With Dynamic Output Switching for Power Side-Channel Attack Mitigation	17
Design of Low-Complexity Quantized Compressive Sensing Using Measurement Predictive Coding	16
Dynamic Rate Neural Acceleration Using Multiprocessing Mode Support	16
A 6.25-MHz 3.4-mW Single Clock DPWM Technique Using Matrix Shift Array	16
A 1.6-mW Sparse Deep Learning Accelerator for Speech Separation	16
An Area-Efficient and Reconfigurable Accelerator for Massive MIMO Systems	16
HARDSEA: Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory Computing Accelerator for Dynamic Sparse Self-Attention in Transformer	16
RV-WINO: A RISC-V Neural Network Accelerator Based on Winograd Algorithm Fabricated in 55-nm CMOS Process	16
A 0.97 nJ/Conversion BJT-Based Temperature Sensor With a Low-Power Two-Stage Dynamic Comparator	16
A Scalable and Efficient NTT/INTT Architecture Using Group-Based Pairwise Memory Access and Fast Interstage Reordering	16
Blocker-Tolerant Inductor-Less Harmonic Selection Wideband Receiver Front-End for 5G Applications	15
Thermally Constrained Codesign of Heterogeneous 3-D Integration of Compute-in-Memory, Digital ML Accelerator, and RISC-V Cores for Mixed ML and Non-ML Workloads	15
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	15
A High Speed and Area Efficient Processor for Elliptic Curve Scalar Point Multiplication for GF(2 m )	15
Implementation of a Multipath Fully Differential OTA in 0.18-μm CMOS Process	15
Design and Analysis of the Leapfrog Control-Bounded A/D Converter	14
An Analytical Model of Mismatch Dominance Crossover in High-Speed Flash ADC Cores	14
An Energy-Efficient Neuromorphic Self-Attention Core Exploiting Dual Sparsity in Neurons and Spikes	14
A 2-Lane DAC-/ADC-Based 2 × 2 MIMO PAM-4 MMSE-DFE Wireline Transceiver With FEXT Cancellation on RFSoC Platform	14
Toward Reliable Onboard AI in Space: A Fault-Tolerant Soft GPU-Based System-on-Chip	14
FASE: An FPGA-Based Accelerator for Lightweight Sample Entropy With Monte Carlo Sampling	14
A 578-TOPS/W RRAM-Based Binary Convolutional Neural Network Macro for Tiny AI Edge Devices	14
Metal Layer Sharing: A Routing Optimization Technique for Monolithic 3D ICs	14
MoE-Sched: Enabling Efficient FPGA Deployment of Mixture-of-Experts Vision Transformers via Coordinated Scheduling	14
Not All Fabrics Are Created Equal: Exploring eFPGA Parameters for IP Redaction	14
MCM-SR: Multiple Constant Multiplication-Based CNN Streaming Hardware Architecture for Super-Resolution	14
A Real-Time Rotation Calibration for Interchannel Offset Mismatch in Time-Interleaved SAR ADCs	13
Binaryware: A High-Performance Digital Hardware Accelerator for Binary Neural Networks	13
ATT-TA: A Cooperative Multiagent Deep Reinforcement Learning Approach for TSV Assignment in 3-D ICs	13
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	13
A Novel Parallel Feed-Forward Current Ripple Rejection (PFFCRR) Technique for High Load Current High PSRR nMOS LDOs	13
A Secure-by-Design Hardware/Operating System as a Substrate for Trustworthy Computing	13
Efficient and Predictable Context Switching for Mixed-Criticality and Real-Time Systems	13
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	13
A High-Throughput and Flexible Architecture Based on a Reconfigurable Mixed-Radix FFT With Twiddle Factor Compression and Conflict-Free Access	13
A Power-On-Reset Circuit With Accurate Trigger-Point Voltage and Ultralow Typical Quiescent Current for Emerging Nonvolatile Memory	13
Analog Matrix Inversion Circuit Design for Solving Tridiagonal Linear Systems: A Compact and Decoupled Approach	12
Synthesis of Analog and Mixed-Signal Circuits on a Programmable Array	12
High Signal-to-Noise Ratio and High-Sensitivity 4-D LiDAR Imaging Receiver	12
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	12
A Model Splitting Approach to Improve Reliability and Accuracy for Alternate Test of Analog/Mixed-Signal Circuits	12
Real-Time Driver Monitoring: Implementing FPGA-Accelerated CNNs for Pose Detection	12
A Real-Time Object Detection Processor With xnor-Based Variable-Precision Computing Unit	12
Analog Probe Module (APM) for Enhanced IC Observability: From Concept to Application	12
A 10-Gb/s/lane, Energy-Efficient Transceiver With Reference-Less Hybrid CDR for Mobile Display Link Interfaces	12
An Energy-Efficient Kalman Filter Coprocessor Design for Multiple-Object Tracking Targeting at Video Understanding	12
Modular RTIC: Lightweight Real Time for Customized Architectures	12
Multiplierless MP-Kernel Machine for Energy-Efficient Edge Devices	12
Table of Contents	12
Enhancing ConvNets With ConvFIFO: A Crossbar PIM Architecture Based on Kernel-Stationary First-In-First-Out Dataflow	12
CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor Sizing	12
M2M: A Fine-Grained Mapping Framework to Accelerate Multiple DNNs on a Multi-Chiplet Architecture	11
Editorial Rolling Out the IEEE TVLSI EDICS	11
ACBN: Approximate Calculated Batch Normalization for Efficient DNN On-Device Training Processor	11
A 380-μW Electrochemical Impedance Measurement System for Protein Sensing	11
A Low-Ripple DIDO DC–DC Hybrid Interface With Optimal-Hysteresis-Controlled MPPT for TEH	11
A 1.28-μW Heart-Rate SoC Achieving 99.68% QRS Detection Accuracy for Long-Term Continuous Cardiac Monitoring Applications	11
A 25-GHz PLL Achieving 8-ns Phase-Shifting Time With Double-Path Modulation Scheme	11
ReAdapt-II: Energy-Quality Optimizations for VLSI Adaptive Filters Through Automatic Reconfiguration and Built-In Iterative Dividers	11
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	11

A Hierarchical 3-D Physical Design Method for Ultralarge-Scale Logic-on-Memory CGRA Chip	11
Re-Pen: Reinforcement Learning-Enforced Penetration Testing for SoC Security Verification	11
Highly Reliable RRAM-Based Physical Unclonable Function With Auto-Write Technique	11
High Bandwidth Thermal Covert Channel in 3-D-Integrated Multicore Processors	11
A 10-bit 50-MS/s Radiation Tolerant Split Coarse/Fine SAR ADC in 65-nm CMOS	11
A 16-bit 1-MS/s SAR ADC With Capacitor Mismatch Self-Calibration	11
Design of a Stochastic Computing Architecture for the Phansalkar Algorithm	11
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	11
An Energy-Efficient Binary-Interfaced Stochastic Multiplier Using Parallel Datapaths	11
A 0.67–5.67-GHz Ring-Based MDLL With 154-fs RMS Jitter and Stochastic Sampling for Spurious Tone Reduction in 5-nm FinFET	11
Efficient and Accurate ECO Leakage Optimization Framework With GNN and Bidirectional LSTM	11
A Scalable and Efficient Architecture for Binary Polynomial Multiplication in BIKE Utilizing Inter-/Inner-Wise Sparsity and Block-by-Block Pipeline	11
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	11
Scalable Hierarchical Instruction Cache for Ultralow-Power Processors Clusters	11
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	11
Table of Contents	11
Low-Latency and Reconfigurable VLSI-Architectures for Computing Eigenvalues and Eigenvectors Using CORDIC-Based Parallel Jacobi Method	11
Hardware-Efficient Low-Distortion Sinusoidal Signal Generator Using FPGA-Based Dual-DAC Digital Predistortion	11
Secure Edge-Coded Signaling IoT Transceiver With Reduced Encryption Overhead	11
A 40-nm Embedded Flash With Highly Reliable Bitline Transmission and Low-Voltage Current Sense Amplifier	11
Table of Contents	11
Table of Contents	11
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	11
A 66-Gb/s/5.5-W RISC-V Many-Core Cluster for 5G+ Software-Defined Radio Uplinks	11
Table of Contents	11
An Improved MOS Self-Biased Ring Amplifier and Modified Auto-Zeroing Scheme	11
An OOK and Binary FSK Reconfigurable Dual-Band Noncoherent IR-UWB Receiver Supporting Ternary Signaling	11
COPMA: Compact and Optimized Polynomial Multiplier Accelerator for High-Performance Implementation of LWR-Based PQC	11
Cross-Layer Approximate Design of Low-Power Fractional Motion Estimation Accelerators for VVC	10
RRAM-Based Spectral-Domain Convolution Accelerator for Reliable and Energy-Efficient CNN Inference	10
An Area-Energy-Efficient 64–2048 Point FFT With Approximate Plane-Fitting Complex Multipliers	10
A Hardware Attack Secure SRAM: A HAS-16T SRAM Cell Resistant to Side Channel Attacks and Fault-Injection Attacks	10
PUF-CIM: SRAM-Based Compute-In-Memory With Zero Bit-Error-Rate Physical Unclonable Function for Lightweight Secure Edge Computing	10
Improvement in Resilience of AES Design With Reconfigured CFB Mode Against Power Attacks	10
Hardware-Efficient, On-the-Fly, On-Implant Spike Sorter Dedicated to Brain-Implantable Microsystems	10
A Low-Cost Quadruple-Node-Upsets Resilient Latch Design	10
Hardware-Accelerator Design by Composition: Dataflow Component Interfaces With Tydi-Chisel	10
X-Rel: Energy-Efficient and Low-Overhead Approximate Reliability Framework for Error-Tolerant Applications Deployed in Critical Systems	10
A Physics-Informed Neural Network Surrogate for Runtime PDN and Dynamic Droop Prediction in 2.5-D Chiplet Integration	10
Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies	10
Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS	10
Residual Feedback Neural Network Calibration for a 12-bit 1-GS/s Pipelined-SAR ADC	10
Design and Analysis of an Ultralow-Voltage Complementary Fold-Interleaved Multiple-Tail Current Mode Logic	10
A 28 nm Dual-Mode SRAM-CIM Macro With Local Computing Cell for CNNs and Grayscale Edge Detection	10
A Time-Domain Reconfigurable Second-Order Noise Shaping ADC With Single Fan-Out Gated Delay Cells	10
FTC: A Universal Framework for Fault-Injection Attack Detection and Prevention	10
A Floating-Point SRAM Computing-in-Memory Macro Using Digital-Domain Structure for CNNs	10
An 197-μJ/Frame Single-Frame Bundle Adjustment Hardware Accelerator for Mobile Visual Odometry	10
Posit Process Element for Using in Energy-Efficient DNN Accelerators	10
A 28 nm 16-kb Sign-Extension-Less Digital-Compute-in-Memory Macro With Extension-Friendly Compute Units and Accuracy-Adjustable Adder-Tree	10
A Masked Hardware Accelerator for Feed-Forward Neural Networks With Fixed-Point Arithmetic	9
A Programmable and Reconfigurable CMOS Analog Hopfield Network for NP-Hard Problems	9
THETA: A High-Efficiency Training Accelerator for DNNs With Triple-Side Sparsity Exploration	9
Novel Formulations of M-Term Overlap-Free Karatsuba Binary Polynomial Multipliers and Their Hardware Implementations	9
A 35.2-kHz, 75.4-dB Bulk-Driven OTA Using Degenerative Current Tram Structure	9
A Hybrid RO-TDL-Based On-Chip Voltage Monitor for FPGA Applications	9
A Hybrid Domain and Pipelined Analog Computing Chain for MVM Computation	9
High-Accuracy and Low-Multiplication Recursive Discrete Cosine Transform Algorithm Design and Its Realization in Mel-Scale Frequency Cepstral Coefficients	9
A Mixed-Mode Acceleration via Sparsity-Adjustable Pruning for Balancing Computation Density in Lightweight CNNs	9
RA-Aware Fail Data Collection Architecture for Cost Reduction	9
An Energy-Efficient Spiking Neural Network Accelerator Based on Spatio-Temporal Redundancy Reduction	9
MCAIMem: A Mixed SRAM and eDRAM Cell for Area and Energy-Efficient On-Chip AI Memory	9
A 20-V Pulse Driver Based on All-nMOS Charge Pump Without Reversion Loss and Overstress in 65-nm Standard CMOS Technology	9
A High-Order High-Throughput Multibank FFT Engine With Optimized Floating-Point Radix-2 Butterfly Units	9
A MOS-DTMOS Implementation of Floating Memristor Emulator for High-Frequency Applications	9
A CMOS Readout Circuit for Resistive Tactile Sensor Array Using Crosstalk Suppression and Nonuniformity Compensation Techniques	9
TIDE-S: Telemetry Informed Delay Testing With Optimized Sensor Placement	9
A Novel Two-Stage Timing Mismatch Calibration Technique for Time-Interleaved ADCs	9
QPA: A Quantization-Aware Piecewise Polynomial Approximation Methodology for Hardware-Efficient Implementations	9
Functional Test Sequences as a Source for Partially Functional Launch-on-Shift Tests	9
A Fourth-Order Tunable Bandwidth Gm -C Filter for ECG Detection Achieving −7.9 dBV IIP3 Under a 0.5 V Supply	9
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	9
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	9
An Electrical-Thermal Co-Simulation Model of Chiplet Heterogeneous Integration Systems	9
A Current-Adjusting Auto-Zeroing Technique for DC-Offset and Flicker-Noise Cancellation	9
A Falcon Signature Verification Accelerator Using Area-Efficient NTT Architecture With Simplified Barrett Modular Multiplier	9
IMCRYPTO: An In-Memory Computing Fabric for AES Encryption and Decryption	9
Efficient Design of Majority-Logic-Based Approximate Arithmetic Circuits	9
Unlimited Vector Processing for Wireless Baseband Based on RISC-V Extension	9
General Compilation and Mixed-Precision Partitioning: A Combined Approach for Adaptive On-Device Learning	9
Testability Evaluation for Local Design Modifications	9
An Efficient High-Throughput Structured-Light Depth Engine	9
A Soft Iterative Receiver With Simplified EP Detection for Coded MIMO Systems	9
An Area and Energy-Efficient Systolic Array Accelerator Architecture for Deep Neural Networks Using Stochastic Computing	9
A High-Throughput Hardware Design for the AV1 Decoder Intraprediction	9
On Continuing DNN Accelerator Architecture Scaling Using Tightly Coupled Compute-on-Memory 3-D ICs	9
Energy-Efficient Encoding for High-Speed Serial Interfaces	8
Functionally Possible Path Delay Faults With High Functional Switching Activity	8
A 22-nm 264-GOPS/mm2 6T SRAM and Proportional Current Compute Cell-Based Computing-in-Memory Macro for CNNs	8
A 56-Gb/s, 6.3-pJ/bit PAM-4 DFB Laser Driver Incorporating Asymmetric Equalization and Integrated CDR in 28 nm CMOS	8
Table of Contents	8
A Supply Noise-Insensitive Ring DCO With a Self-Biased Shunt Regulator Array in Wide-Range Digital PLL	8
Chip Aging and Transition Faults With High Switching Activities Under Scan-Based Tests	8
12-bit SAR ADC Employing a 9-bit CDAC in Vanilla CMOS 40-nm Technology	8
Dual-Rail Precharge Logic-Based Side-Channel Countermeasure for DNN Systolic Array	8