IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Papers
(The TQCC of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is 6. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-08-01 to 2024-08-01.)
ArticleCitations
Cryptographic Accelerators for Digital Signature Based on Ed2551972
An Efficient Hardware Accelerator for Structured Sparse Convolutional Neural Networks on FPGAs72
Mixed-Signal Computing for Deep Neural Network Inference62
Design Methodology for Distributed Large-Scale ERSFQ Bias Networks51
FPnew: An Open-Source Multiformat Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing49
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse43
Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators40
PLAC: Piecewise Linear Approximation Computation for All Nonlinear Unary Functions38
ASSURE: RTL Locking Against an Untrusted Foundry37
Design and Analysis of Approximate 4–2 Compressors for High-Accuracy Multipliers37
Area-Efficient Nano-AES Implementation for Internet-of-Things Devices35
Designing Novel AAD Pooling in Hardware for a Convolutional Neural Network Accelerator33
SCOPE: Synthesis-Based Constant Propagation Attack on Logic Locking32
High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND31
High-Performance Spintronic Nonvolatile Ternary Flip-Flop and Universal Shift Register30
A Twofold Lookup Table Architecture for Efficient Approximation of Activation Functions29
Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates29
Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes29
Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory28
Reliable Architectures for Finite Field Multipliers Using Cyclic Codes on FPGA Utilized in Classic and Post-Quantum Cryptography28
GenMap: A Genetic Algorithmic Approach for Optimizing Spatial Mapping of Coarse-Grained Reconfigurable Architectures25
A 0.5-V Multiple-Input Bulk-Driven OTA in 0.18-μm CMOS25
A Highly Robust and Low-Power Real-Time Double Node Upset Self-Healing Latch for Radiation-Prone Applications25
TxSim: Modeling Training of Deep Neural Networks on Resistive Crossbar Systems24
A 2–24-GHz 360° Full-Span Differential Vector Modulator Phase Rotator With Transformer-Based Poly-Phase Quadrature Network24
A 0.6-V Power-Efficient Active-RC Analog Low-Pass Filter With Cutoff Frequency Selection23
Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT23
A Highly Unified Reconfigurable Multicore Architecture to Speed Up NTT/INTT for Homomorphic Polynomial Multiplication23
Unified Analog PUF and TRNG Based on Current-Steering DAC and VCO23
Fast Binary Counters and Compressors Generated by Sorting Network23
SWM: A High-Performance Sparse-Winograd Matrix Multiplication CNN Accelerator22
Parallel and Flexible 5G LDPC Decoder Architecture Targeting FPGA22
ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators22
An Enhanced Input Differential Pair for Low-Voltage Bulk-Driven Amplifiers22
Computing-in-Memory for Performance and Energy-Efficient Homomorphic Encryption22
An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FGPA Implementation22
Low-Power Retentive True Single-Phase-Clocked Flip-Flop With Redundant-Precharge-Free Operation22
Real-Time SSDLite Object Detection on FPGA21
An Algorithm–Hardware Co-Optimized Framework for Accelerating N:M Sparse Transformers21
Power Side-Channel Leakage Assessment Framework at Register-Transfer Level21
Physical Attack Protection Techniques for IC Chip Level Hardware Security21
ADMM-Based Infinity-Norm Detection for Massive MIMO: Algorithm and VLSI Architecture21
Efficient Error Detection Architectures for Postquantum Signature Falcon’s Sampler and KEM SABER21
SIXOR: Single-Cycle In-Memristor XOR20
Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System20
A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh20
Heterogeneous Mixed-Signal Monolithic 3-D In-Memory Computing Using Resistive RAM20
PCBChain: Lightweight Reconfigurable Blockchain Primitives for Secure IoT Applications20
A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push–Pull SS-PD and a Fast-Locking FLL Achieving −82.2-dBc REF Spur and −255-dB FOM19
High-Performance COTS FPGA SoC for Parallel Hyperspectral Image Compression With CCSDS-123.0-B-119
Memristors Enabled Computing Correlation Parameter In-Memory System: A Potential Alternative to Von Neumann Architecture19
Reliable CRC-Based Error Detection Constructions for Finite Field Multipliers With Applications in Cryptography19
FPGA Implementation of an Improved OMP for Compressive Sensing Reconstruction19
Gain-Cell Embedded DRAM Under Cryogenic Operation—A First Study19
Memristive Computational Memory Using Memristor Overwrite Logic (MOL)18
A Reconfigurable CMOS Rectifier With 14-dB Power Dynamic Range Achieving >36-dB/mm2 FoM for RF-Based Hybrid Energy Harvesting18
A 35-GHz TX and RX Front End With High TX Output Power for Ka-Band FMCW Phased-Array Radar Transceivers in CMOS Technology18
Design and Implementation of Approximate DCT Architecture in Quantum-Dot Cellular Automata18
A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations18
Machine-Learning-Based Self-Tunable Design of Approximate Computing18
Securing Hardware Accelerators for CE Systems Using Biometric Fingerprinting18
A Reinforcement Learning-Based Framework for Solving the IP Mapping Problem17
Dugdugi: An Optimal Fault Addressing Scheme for Octagon-Like On-Chip Communication Networks17
CRC-Based Error Detection Constructions for FLT and ITA Finite Field Inversions Over GF(2 m )17
Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS16
A New Hardware-Efficient Spectrum-Sensor VLSI Architecture for Data-Fusion-Based Cooperative Cognitive-Radio Network16
High-Throughput/Low-Energy MTJ-Based True Random Number Generator Using a Multi-Voltage/Current Converter16
A Timing Mismatch Background Calibration Algorithm With Improved Accuracy16
High-Utilization, High-Flexibility Depth-First CNN Coprocessor for Image Pixel Processing on FPGA15
Power Distribution Attacks in Multitenant FPGAs15
Performance and Accuracy Tradeoffs for Training Graph Neural Networks on ReRAM-Based Architectures15
True Random Number Generation Using Latency Variations of FRAM15
A Multirate Fully Parallel LDPC Encoder for the IEEE 802.11n/ac/ax QC-LDPC Codes Based on Reduced Complexity XOR Trees15
A Configurable Floating-Point Multiple-Precision Processing Element for HPC and AI Converged Computing15
Low Power Unsupervised Anomaly Detection by Nonparametric Modeling of Sensor Statistics14
Spreading Operation Frequency Ranges of Memristor Emulators via a New Sine-Based Method14
List-GRAND: A Practical Way to Achieve Maximum Likelihood Decoding14
Sub-1-V BGR and POR Hybrid Circuit With 2.25-μA Current Dissipation and Low Complexity14
VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative14
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation—Part I: CNFET Transistor Optimization14
A Second-Order Noise-Shaping SAR ADC Using Two Passive Integrators Separated by the Comparator14
A Radiation-Hardened CMOS Full-Adder Based on Layout Selective Transistor Duplication14
An EEG-Based Hypnotic State Monitor for Patients During General Anesthesia14
Radiation-Hardened, Read-Disturbance-Free New-Quatro-10T Memory Cell for Aerospace Applications14
Soft Error Tolerant Convolutional Neural Networks on FPGAs With Ensemble Learning14
A Time-Domain Reconfigurable Second-Order Noise Shaping ADC With Single Fan-Out Gated Delay Cells14
An IP Core Mapping Algorithm Based on Neural Networks13
An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power13
Hybrid Accumulator Factored Systolic Array for Machine Learning Acceleration13
Recurrent Neural Networks With Column-Wise Matrix–Vector Multiplication on FPGAs13
F-DNA: Fast Convolution Architecture for Deconvolutional Network Acceleration13
Ultralow-Power Localization of Insect-Scale Drones: Interplay of Probabilistic Filtering and Compute-in-Memory13
Facial Biometric for Securing Hardware Accelerators13
Designing Efficient and High-Performance AI Accelerators With Customized STT-MRAM13
Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits13
Anti-PVT-Variation Low-Power Time-to-Digital Converter Design Using 90-nm CMOS Process13
A Three-Stage Comparator and Its Modified Version With Fast Speed and Low Kickback13
Analog and Mixed-Signal Layout Automation Using Digital Place-and-Route Tools13
NeuPart: Using Analytical Models to Drive Energy-Efficient Partitioning of CNN Computations on Cloud-Connected Mobile Clients13
Breaking Analog Locking Techniques13
A 12-Bit Two-Step Single-Slope ADC With a Constant Input-Common-Mode Level Resistor Ramp Generator13
Cerebron: A Reconfigurable Architecture for Spatiotemporal Sparse Spiking Neural Networks12
MeNTT: A Compact and Efficient Processing-in-Memory Number Theoretic Transform (NTT) Accelerator12
A −20-dBm Sensitivity RF Energy-Harvesting Rectifier Front End Using a Transformer IMN12
Efficient Implementation of Dilithium Signature Scheme on FPGA SoC Platform12
McPAT-Monolithic: An Area/Power/Timing Architecture Modeling Framework for 3-D Hybrid Monolithic Multicore Systems12
Low-Power, Low-Noise Edge-Race Comparator for SAR ADCs12
AdaTrust: Combinational Hardware Trojan Detection Through Adaptive Test Pattern Construction12
Analysis of a Pipelined Architecture for Sparse DNNs on Embedded Systems12
A 14-bit 200-Ms/s SHA-Less Pipelined ADC With Aperture Error Reduction12
Detecting Hardware Trojans in PCBs Using Side Channel Loopbacks12
All-Digital CMOS Time-to-Digital Converter With Temperature-Measuring Capability12
NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators12
Integer Codes Correcting Double Errors and Triple-Adjacent Errors Within a Byte12
AxPPA: Approximate Parallel Prefix Adders12
A 32-Gb/s PAM-4 SST Transmitter With Four-Tap FFE Using High-Impedance Driver in 28-nm FDSOI12
A Hierarchical Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs12
Improving TID Radiation Robustness of a CMOS OxRAM-Based Neuron Circuit by Using Enclosed Layout Transistors12
Accurate On-Chip Temperature Sensing for Multicore Processors Using Embedded Thermal Sensors12
Multisymbol Architecture of the Entropy Coder for H.265/HEVC Video Encoders12
A High-Performance and Low-Cost Single-Event Multiple-Node-Upsets Resilient Latch Design11
Glitch-Optimized Circuit Blocks for Low-Power High-Performance Booth Multipliers11
Area-Efficient Extended 3-D Inductor Based on TSV Technology for RF Applications11
A 0.3 nW, 0.093%/V Line Sensitivity, Temperature Compensated Bulk-Programmable Voltage Reference for Wireless Sensor Nodes11
A Multimode Configurable Physically Unclonable Function With Bit-Instability-Screening and Power-Gating Strategies11
A 2.4-GHz Area-Efficient and Fast-Locking Subharmonically Injection-Locked Type-I PLL11
Applying Thermal Side-Channel Attacks on Asymmetric Cryptography11
Benchmark of the Compute-in-Memory-Based DNN Accelerator With Area Constraint11
A 16-kb 9T Ultralow-Voltage SRAM With Column-Based Split Cell-VSS, Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28-nm FDSOI11
A 0.3-V 8.5-μ a Bulk-Driven OTA11
Efficient Execution of Temporal Convolutional Networks for Embedded Keyword Spotting11
Efficient Performance Modeling for Automated CMOS Analog Circuit Synthesis11
On Efficiency Enhancement of SHA-3 for FPGA-Based Multimodal Biometric Authentication11
FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators11
High-Dimensional Many-Objective Bayesian Optimization for LDE-Aware Analog IC Sizing10
A Multiring Julia Fractal Chaotic System With Separated-Scroll Attractors10
Design of DNN-Based Low-Power VLSI Architecture to Classify Atrial Fibrillation for Wearable Devices10
A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n- and p-type Flip-Flops10
Nonscaling Adders and Subtracters for Stochastic Computing Using Markov Chains10
A Reconfigurable Multiple Transform Selection Architecture for VVC10
An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC10
A 3.85-Gb/s 8 × 8 Soft-Output MIMO Detector With Lattice-Reduction-Aided Channel Preprocessing10
Thermal-Aware Floorplanning and TSV-Planning for Mixed-Type Modules in a Fixed-Outline 3-D IC10
A High-Performance SIKE Hardware Accelerator10
Hardware Implementation of an OPC UA Server for Industrial Field Devices10
A Programmable SoC-Based Accelerator for Privacy-Enhancing Technologies and Functional Encryption10
Time and Area Optimized Testing of Automotive ICs10
A VLSI Majority-Logic Device Based on Spin Transfer Torque Mechanism for Brain-Inspired Computing Architecture10
An Optimized M-Term Karatsuba-Like Binary Polynomial Multiplier for Finite Field Arithmetic10
Low-Cost Online Convolution Checksum Checker10
A High-Speed Low-Noise Comparator With Auxiliary-Inverter-Based Common Mode-Self-Regulation for Low-Supply-Voltage SAR ADCs10
SCERPA Simulation of Clocked Molecular Field-Coupling Nanocomputing10
A 215-F² Bistable Physically Unclonable Function With an ACF of <0.005 and a Native Bit Instability of 2.05% in 65-nm CMOS Process10
Dynamic Workload Allocation for Edge Computing10
Fast and Accurate Estimation of Statistical Eye Diagram for Nonlinear High-Speed Links10
A 700-μm², Ring-Oscillator-Based Thermal Sensor in 16-nm FinFET9
Compute-in-Memory Technologies and Architectures for Deep Learning Workloads9
Revisiting Stochastic Computing in the Era of Nanoscale Nonvolatile Technologies9
A More Accurate and Robust Binary Ring-LWE Decryption Scheme and Its Hardware Implementation for IoT Devices9
Multiple-Mode-Supporting Floating-Point FMA Unit for Deep Learning Processors9
ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator9
Golden-Free Hardware Trojan Detection Using Self-Referencing9
Dataflow-Aware Macro Placement Based on Simulated Evolution Algorithm for Mixed-Size Designs9
A 23–36.8-GHz Low-Noise Frequency Synthesizer With a Fundamental Colpitts VCO Array in SiGe BiCMOS for 5G Applications9
VCO-Based Comparator: A Fully Adaptive Noise Scaling Comparator for High-Precision and Low-Power SAR ADCs9
Secure XOR-CIM Engine: Compute-In-Memory SRAM Architecture With Embedded XOR Encryption9
Information Storage Bit-Flipping Decoder for LDPC Codes9
Analysis and Design of Magnetically Tuned W -Band Oscillators9
A Hybrid Miller-Cascode Compensation for Fast Settling in Two-Stage Operational Amplifiers9
Efficient Register Renaming Architectures for 8-bit AES Datapath at 0.55 pJ/bit in 16-nm FinFET9
A 4.4-mA ESD-Safe 900-MHz LNA With 0.9-dB Noise Figure9
An Area-Efficient SAR ADC With Mismatch Error Shaping Technique Achieving 102-dB SFDR 90.2-dB SNDR Over 20-kHz Bandwidth9
Alternatives to Bicubic Interpolation Considering FPGA Hardware Resource Consumption9
Performance and Security Analysis of Parameter-Obfuscated Analog Circuits9
RPE-TCAM: Reconfigurable Power-Efficient Ternary Content-Addressable Memory on FPGAs9
Golden Reference-Free Hardware Trojan Localization Using Graph Convolutional Network9
A Conversion Mode Reconfigurable SAR ADC for Multistandard Systems9
A Fast Leakage-Aware Green’s-Function-Based Thermal Simulator for 3-D Chips8
A Low-Power PAM4 Receiver With an Adaptive Variable-Gain Rectifier-Based Decoder8
ARXON: A Framework for Approximate Communication Over Photonic Networks-on-Chip8
An Efficient CNN Accelerator Using Inter-Frame Data Reuse of Videos on FPGAs8
A Fast Convergence Second-Order Compensation for Timing Skew in Time-Interleaved ADCs8
A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI8
Development of a Short-Term to Long-Term Supervised Spiking Neural Network Processor8
THETA: A High-Efficiency Training Accelerator for DNNs With Triple-Side Sparsity Exploration8
A Universal Efficient Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders8
Differential Aging Sensor Using Subthreshold Leakage Current to Detect Recycled ICs8
A High-Performance Dual-Topology CMOS Rectifier With 19.5-dB Power Dynamic Range for RF-Based Hybrid Energy Harvesting8
PWL-Based Architecture for the Logarithmic Computation of Floating-Point Numbers8
A Pre-Activation, Golden IC Free, Hardware Trojan Detection Approach8
High-Performance Concatenation Decoding of Reed–Solomon Codes With SPC Codes8
Low-Overhead Triple-Node-Upset-Tolerant Latch Design in 28-nm CMOS8
A Ku-Band Eight-Element Phased-Array Transmitter With Built-in Self-Test Capability in 180-nm CMOS Technology8
High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors8
A 60-Mode High-Throughput Parallel-Processing FFT Processor for 5G/4G Applications8
A Generalized Power Supply Induced Jitter Model Based on Power Supply Rejection Ratio Response8
Digital Watermarking for Detecting Malicious Intellectual Property Cores in NoC Architectures8
FN-CACTI: Advanced CACTI for FinFET and NC-FinFET Technologies8
An Area-Efficient High-Resolution Segmented ΣΔ-DAC for Built-In Self-Test Applications8
IMCA: An Efficient In-Memory Convolution Accelerator8
Locking by Untuning: A Lock-Less Approach for Analog and Mixed-Signal IC Security7
Approximate Softmax Functions for Energy-Efficient Deep Neural Networks7
A 300-mV Auto Shutdown Comparator-Based Continuous Time Δ∑ Modulator7
Exploring the Design of Energy-Efficient Intermittently Powered Systems Using Reconfigurable Ferroelectric Transistors7
Hard-to-Detect Fault Analysis in FinFET SRAMs7
CapCAM: A Multilevel Capacitive Content Addressable Memory for High-Accuracy and High-Scalability Search and Compute Applications7
An Error Compensation Technique for Low-Voltage DNN Accelerators7
Design and Evaluation of a Hybrid Chaotic-Bistable Ring PUF7
Speed/Area-Efficient ECC Processor Implementation Over GF(2 m ) on FPGA via Novel Algorithm-Architecture Co-Design7
A Multiband VCO Using a Switched Series Resonance for Fine Frequency Tuning Sensitivity and Phase Noise Improvement7
FracTCAM: Fracturable LUTRAM-Based TCAM Emulation on Xilinx FPGAs7
An Ultralow-Power OOK/BFSK/DBPSK Wake-Up Receiver Based on Injection-Locked Oscillator7
Implementation of a Multipath Fully Differential OTA in 0.18-μm CMOS Process7
An M-Cache-Based Security Monitoring and Fault Recovery Architecture for Embedded Processor7
Cyclic Sparsely Connected Architectures for Compact Deep Convolutional Neural Networks7
LEAP: Lightweight and Efficient Accelerator for Sparse Polynomial Multiplication of HQC7
Fast Modular Multipliers for Supersingular Isogeny-Based Post-Quantum Cryptography7
A MOS-DTMOS Implementation of Floating Memristor Emulator for High-Frequency Applications7
Energy-Efficient Logarithmic Square Rooter for Error-Resilient Applications7
SCARE: Side Channel Attack on In-Memory Computing for Reverse Engineering7
Cascode Cross-Coupled Stage High-Speed Dynamic Comparator in 65 nm CMOS7
Multiplierless MP-Kernel Machine for Energy-Efficient Edge Devices7
A 0.0067-mm2 12-bit 20-MS/s SAR ADC Using Digital Place-and-Route Tools in 40-nm CMOS7
A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMSJitter, −258.7-dB FOM, and −75.17-dBc Reference Spur7
Variation-Aware Delay Fault Testing for Carbon-Nanotube FET Circuits7
EM Side-Channel Countermeasure for Switched-Capacitor DC–DC Converters Based on Amplitude Modulation7
A Wide-Range All-Digital Delay-Locked Loop for DDR1–DDR5 Applications7
EFFORT: A Comprehensive Technique to Tackle Timing Violations and Improve Energy Efficiency of Near-Threshold Tensor Processing Units7
Design of FPGA-Implemented Reed–Solomon Erasure Code (RS-EC) Decoders With Fault Detection and Location on User Memory7
An 8-Bit in Resistive Memory Computing Core With Regulated Passive Neuron and Bitline Weight Mapping7
Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process7
RNN-Based Radio Resource Management on Multicore RISC-V Accelerator Architectures7
A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks7
Stochastic Computing Max & Min Architectures Using Markov Chains: Design, Analysis, and Implementation7
A 2.56-GS/s 12-bit 8x-Interleaved ADC With 156.6-dB FoM S in 65-nm CMOS7
Communication-Aware Task Scheduling for Energy-Harvesting Nonvolatile Processors7
Machine Learning Attack Resistant Area-Efficient Reconfigurable Ising-PUF7
ADIC: Anomaly Detection Integrated Circuit in 65-nm CMOS Utilizing Approximate Computing7
Adaptable Approximate Multiplier Design Based on Input Distribution and Polarity6
A Miniaturized Wideband Interdigital Bandpass Filter With High Out-Band Suppression Based on TSV Technology for W-Band Application6
RASHT: A Partially Reconfigurable Architecture for Efficient Implementation of CNNs6
Preprocessing of the Physical Leakage Information to Combine Side-Channel Distinguishers6
Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches6
Robust Security of Hardware Accelerators Using Protein Molecular Biometric Signature and Facial Biometric Encryption Key6
R2F: A Remote Retraining Framework for AIoT Processors With Computing Errors6
A Fully Digital SRAM-Based Four-Layer In-Memory Computing Unit Achieving Multiplication Operations and Results Store6
A Reconfigurable Neural Network Processor With Tile-Grained Multicore Pipeline for Object Detection on FPGA6
A 25–30-GHz RMS Error-Minimized 360° Continuous Analog Phase Shifter Using Closed-Loop Self-Tuning I/Q Generator6
Configurable Memory With a Multilevel Shared Structure Enabling In-Memory Computing6
Approximation of Transcendental Functions With Guaranteed Algorithmic QoS by Multilayer Pareto Optimization6
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