IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Article	Citations
Cryptographic Accelerators for Digital Signature Based on Ed25519	85
Mixed-Signal Computing for Deep Neural Network Inference	67
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse	53
FPnew: An Open-Source Multiformat Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing	53
Design Methodology for Distributed Large-Scale ERSFQ Bias Networks	51
Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators	45
ASSURE: RTL Locking Against an Untrusted Foundry	38
Design and Analysis of Approximate 4–2 Compressors for High-Accuracy Multipliers	38
Designing Novel AAD Pooling in Hardware for a Convolutional Neural Network Accelerator	37
Area-Efficient Nano-AES Implementation for Internet-of-Things Devices	37
High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND	34
SCOPE: Synthesis-Based Constant Propagation Attack on Logic Locking	34
High-Performance Spintronic Nonvolatile Ternary Flip-Flop and Universal Shift Register	32
A Twofold Lookup Table Architecture for Efficient Approximation of Activation Functions	31
Reliable Architectures for Finite Field Multipliers Using Cyclic Codes on FPGA Utilized in Classic and Post-Quantum Cryptography	31
Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes	31
Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates	29
GenMap: A Genetic Algorithmic Approach for Optimizing Spatial Mapping of Coarse-Grained Reconfigurable Architectures	28
Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory	28
TxSim: Modeling Training of Deep Neural Networks on Resistive Crossbar Systems	26
A Highly Robust and Low-Power Real-Time Double Node Upset Self-Healing Latch for Radiation-Prone Applications	26
A 2–24-GHz 360° Full-Span Differential Vector Modulator Phase Rotator With Transformer-Based Poly-Phase Quadrature Network	26
A Highly Unified Reconfigurable Multicore Architecture to Speed Up NTT/INTT for Homomorphic Polynomial Multiplication	25
An Enhanced Input Differential Pair for Low-Voltage Bulk-Driven Amplifiers	25
An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FGPA Implementation	25

A 0.5-V Multiple-Input Bulk-Driven OTA in 0.18-μm CMOS	25
Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT	25
Unified Analog PUF and TRNG Based on Current-Steering DAC and VCO	24
Computing-in-Memory for Performance and Energy-Efficient Homomorphic Encryption	24
An Algorithm–Hardware Co-Optimized Framework for Accelerating N:M Sparse Transformers	24
Fast Binary Counters and Compressors Generated by Sorting Network	24
SWM: A High-Performance Sparse-Winograd Matrix Multiplication CNN Accelerator	23
Parallel and Flexible 5G LDPC Decoder Architecture Targeting FPGA	23
ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators	23
Physical Attack Protection Techniques for IC Chip Level Hardware Security	23
Power Side-Channel Leakage Assessment Framework at Register-Transfer Level	23
Efficient Error Detection Architectures for Postquantum Signature Falcon’s Sampler and KEM SABER	23
Real-Time SSDLite Object Detection on FPGA	22
A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh	22
Design and Implementation of Approximate DCT Architecture in Quantum-Dot Cellular Automata	22
Low-Power Retentive True Single-Phase-Clocked Flip-Flop With Redundant-Precharge-Free Operation	22
Heterogeneous Mixed-Signal Monolithic 3-D In-Memory Computing Using Resistive RAM	21
Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS	21
Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System	21
ADMM-Based Infinity-Norm Detection for Massive MIMO: Algorithm and VLSI Architecture	21
Gain-Cell Embedded DRAM Under Cryogenic Operation—A First Study	20
Reliable CRC-Based Error Detection Constructions for Finite Field Multipliers With Applications in Cryptography	20
Memristive Computational Memory Using Memristor Overwrite Logic (MOL)	20
A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations	20
CRC-Based Error Detection Constructions for FLT and ITA Finite Field Inversions Over GF(2 m )	20
SIXOR: Single-Cycle In-Memristor XOR	20
A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push–Pull SS-PD and a Fast-Locking FLL Achieving −82.2-dBc REF Spur and −255-dB FOM	20
High-Performance COTS FPGA SoC for Parallel Hyperspectral Image Compression With CCSDS-123.0-B-1	20
Memristors Enabled Computing Correlation Parameter In-Memory System: A Potential Alternative to Von Neumann Architecture	20
FPGA Implementation of an Improved OMP for Compressive Sensing Reconstruction	20
A Reconfigurable CMOS Rectifier With 14-dB Power Dynamic Range Achieving >36-dB/mm2 FoM for RF-Based Hybrid Energy Harvesting	19
Machine-Learning-Based Self-Tunable Design of Approximate Computing	18
Dugdugi: An Optimal Fault Addressing Scheme for Octagon-Like On-Chip Communication Networks	17
A Reinforcement Learning-Based Framework for Solving the IP Mapping Problem	17
A Multirate Fully Parallel LDPC Encoder for the IEEE 802.11n/ac/ax QC-LDPC Codes Based on Reduced Complexity XOR Trees	17
A Configurable Floating-Point Multiple-Precision Processing Element for HPC and AI Converged Computing	17
Performance and Accuracy Tradeoffs for Training Graph Neural Networks on ReRAM-Based Architectures	17
List-GRAND: A Practical Way to Achieve Maximum Likelihood Decoding	17
A New Hardware-Efficient Spectrum-Sensor VLSI Architecture for Data-Fusion-Based Cooperative Cognitive-Radio Network	16
A Second-Order Noise-Shaping SAR ADC Using Two Passive Integrators Separated by the Comparator	16
A Timing Mismatch Background Calibration Algorithm With Improved Accuracy	16
Spreading Operation Frequency Ranges of Memristor Emulators via a New Sine-Based Method	16
A Time-Domain Reconfigurable Second-Order Noise Shaping ADC With Single Fan-Out Gated Delay Cells	15
Soft Error Tolerant Convolutional Neural Networks on FPGAs With Ensemble Learning	15
High-Utilization, High-Flexibility Depth-First CNN Coprocessor for Image Pixel Processing on FPGA	15
True Random Number Generation Using Latency Variations of FRAM	15
AxPPA: Approximate Parallel Prefix Adders	15
Power Distribution Attacks in Multitenant FPGAs	15
An EEG-Based Hypnotic State Monitor for Patients During General Anesthesia	15
Golden Reference-Free Hardware Trojan Localization Using Graph Convolutional Network	14

Design of DNN-Based Low-Power VLSI Architecture to Classify Atrial Fibrillation for Wearable Devices	14
Designing Efficient and High-Performance AI Accelerators With Customized STT-MRAM	14
A 12-Bit Two-Step Single-Slope ADC With a Constant Input-Common-Mode Level Resistor Ramp Generator	14
A 0.3-V 8.5-μ a Bulk-Driven OTA	14
A High-Performance and Low-Cost Single-Event Multiple-Node-Upsets Resilient Latch Design	14
Detecting Hardware Trojans in PCBs Using Side Channel Loopbacks	14
VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative	14
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation—Part I: CNFET Transistor Optimization	14
Ultralow-Power Localization of Insect-Scale Drones: Interplay of Probabilistic Filtering and Compute-in-Memory	14
A Radiation-Hardened CMOS Full-Adder Based on Layout Selective Transistor Duplication	14
An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power	14
Accurate On-Chip Temperature Sensing for Multicore Processors Using Embedded Thermal Sensors	14
A Three-Stage Comparator and Its Modified Version With Fast Speed and Low Kickback	14
Cerebron: A Reconfigurable Architecture for Spatiotemporal Sparse Spiking Neural Networks	13
A 32-Gb/s PAM-4 SST Transmitter With Four-Tap FFE Using High-Impedance Driver in 28-nm FDSOI	13
Efficient Implementation of Dilithium Signature Scheme on FPGA SoC Platform	13
A 0.3 nW, 0.093%/V Line Sensitivity, Temperature Compensated Bulk-Programmable Voltage Reference for Wireless Sensor Nodes	13
Recurrent Neural Networks With Column-Wise Matrix–Vector Multiplication on FPGAs	13
Facial Biometric for Securing Hardware Accelerators	13
Multisymbol Architecture of the Entropy Coder for H.265/HEVC Video Encoders	13
Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits	13
MeNTT: A Compact and Efficient Processing-in-Memory Number Theoretic Transform (NTT) Accelerator	13
Analog and Mixed-Signal Layout Automation Using Digital Place-and-Route Tools	13
An IP Core Mapping Algorithm Based on Neural Networks	13
Hybrid Accumulator Factored Systolic Array for Machine Learning Acceleration	13
Applying Thermal Side-Channel Attacks on Asymmetric Cryptography	12
Improving TID Radiation Robustness of a CMOS OxRAM-Based Neuron Circuit by Using Enclosed Layout Transistors	12
A 16-kb 9T Ultralow-Voltage SRAM With Column-Based Split Cell-VSS, Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28-nm FDSOI	12
Efficient Performance Modeling for Automated CMOS Analog Circuit Synthesis	12
Digital Watermarking for Detecting Malicious Intellectual Property Cores in NoC Architectures	12
A Multimode Configurable Physically Unclonable Function With Bit-Instability-Screening and Power-Gating Strategies	12
A −20-dBm Sensitivity RF Energy-Harvesting Rectifier Front End Using a Transformer IMN	12
Low-Power, Low-Noise Edge-Race Comparator for SAR ADCs	12
AdaTrust: Combinational Hardware Trojan Detection Through Adaptive Test Pattern Construction	12
Dataflow-Aware Macro Placement Based on Simulated Evolution Algorithm for Mixed-Size Designs	11
A 215-F² Bistable Physically Unclonable Function With an ACF of <0.005 and a Native Bit Instability of 2.05% in 65-nm CMOS Process	11
On Efficiency Enhancement of SHA-3 for FPGA-Based Multimodal Biometric Authentication	11
High-Dimensional Many-Objective Bayesian Optimization for LDE-Aware Analog IC Sizing	11
A 3.85-Gb/s 8 × 8 Soft-Output MIMO Detector With Lattice-Reduction-Aided Channel Preprocessing	11
Competitive Neural Network Circuit Based on Winner-Take-All Mechanism and Online Hebbian Learning Rule	11
SCERPA Simulation of Clocked Molecular Field-Coupling Nanocomputing	11
Area-Efficient Extended 3-D Inductor Based on TSV Technology for RF Applications	11
VCO-Based Comparator: A Fully Adaptive Noise Scaling Comparator for High-Precision and Low-Power SAR ADCs	11
ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator	11
FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators	11
Efficient Execution of Temporal Convolutional Networks for Embedded Keyword Spotting	11
A 2.4-GHz Area-Efficient and Fast-Locking Subharmonically Injection-Locked Type-I PLL	11
Secure XOR-CIM Engine: Compute-In-Memory SRAM Architecture With Embedded XOR Encryption	11
Time and Area Optimized Testing of Automotive ICs	11
An Optimized M-Term Karatsuba-Like Binary Polynomial Multiplier for Finite Field Arithmetic	11
Golden-Free Hardware Trojan Detection Using Self-Referencing	10
A High-Performance SIKE Hardware Accelerator	10
Hardware Implementation of an OPC UA Server for Industrial Field Devices	10
Dynamic Workload Allocation for Edge Computing	10
An Area-Efficient High-Resolution Segmented ΣΔ-DAC for Built-In Self-Test Applications	10
A Multiring Julia Fractal Chaotic System With Separated-Scroll Attractors	10
A High-Speed Low-Noise Comparator With Auxiliary-Inverter-Based Common Mode-Self-Regulation for Low-Supply-Voltage SAR ADCs	10
Nonscaling Adders and Subtracters for Stochastic Computing Using Markov Chains	10
Fast and Accurate Estimation of Statistical Eye Diagram for Nonlinear High-Speed Links	10
FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Networks With Efficient DSP and Memory Optimization	10
Low-Cost Online Convolution Checksum Checker	10
Thermal-Aware Floorplanning and TSV-Planning for Mixed-Type Modules in a Fixed-Outline 3-D IC	10
A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n- and p-type Flip-Flops	10
A Reconfigurable Multiple Transform Selection Architecture for VVC	10
An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC	10
Analysis and Design of Magnetically Tuned W -Band Oscillators	10
An Area-Efficient SAR ADC With Mismatch Error Shaping Technique Achieving 102-dB SFDR 90.2-dB SNDR Over 20-kHz Bandwidth	9
A 23–36.8-GHz Low-Noise Frequency Synthesizer With a Fundamental Colpitts VCO Array in SiGe BiCMOS for 5G Applications	9
Alternatives to Bicubic Interpolation Considering FPGA Hardware Resource Consumption	9
A 33–41-GHz SiGe-BiCMOS Digital Step Attenuator With Minimized Unit Impedance Variation	9
Information Storage Bit-Flipping Decoder for LDPC Codes	9
CapCAM: A Multilevel Capacitive Content Addressable Memory for High-Accuracy and High-Scalability Search and Compute Applications	9
High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors	9
A Conversion Mode Reconfigurable SAR ADC for Multistandard Systems	9
Variation-Aware Delay Fault Testing for Carbon-Nanotube FET Circuits	9
Compute-in-Memory Technologies and Architectures for Deep Learning Workloads	9
FN-CACTI: Advanced CACTI for FinFET and NC-FinFET Technologies	9
A Fast Convergence Second-Order Compensation for Timing Skew in Time-Interleaved ADCs	9
Multiple-Mode-Supporting Floating-Point FMA Unit for Deep Learning Processors	9
Low-Overhead Triple-Node-Upset-Tolerant Latch Design in 28-nm CMOS	9

Approximate Softmax Functions for Energy-Efficient Deep Neural Networks	9
A Fast Leakage-Aware Green’s-Function-Based Thermal Simulator for 3-D Chips	9
A 60-Mode High-Throughput Parallel-Processing FFT Processor for 5G/4G Applications	9
A 4.4-mA ESD-Safe 900-MHz LNA With 0.9-dB Noise Figure	9
Revisiting Stochastic Computing in the Era of Nanoscale Nonvolatile Technologies	9
A More Accurate and Robust Binary Ring-LWE Decryption Scheme and Its Hardware Implementation for IoT Devices	9
A Pre-Activation, Golden IC Free, Hardware Trojan Detection Approach	9
Performance and Security Analysis of Parameter-Obfuscated Analog Circuits	9
Design and Evaluation of a Hybrid Chaotic-Bistable Ring PUF	9
A 700-μm², Ring-Oscillator-Based Thermal Sensor in 16-nm FinFET	9
Gate Delay Estimation With Library Compatible Current Source Models and Effective Capacitance	9
A Universal Efficient Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders	8
A 2.56-GS/s 12-bit 8x-Interleaved ADC With 156.6-dB FoM S in 65-nm CMOS	8
A Multiband VCO Using a Switched Series Resonance for Fine Frequency Tuning Sensitivity and Phase Noise Improvement	8
A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI	8
An Efficient CNN Accelerator Using Inter-Frame Data Reuse of Videos on FPGAs	8
Hard-to-Detect Fault Analysis in FinFET SRAMs	8
EM Side-Channel Countermeasure for Switched-Capacitor DC–DC Converters Based on Amplitude Modulation	8
Development of a Short-Term to Long-Term Supervised Spiking Neural Network Processor	8
A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks	8
Differential Aging Sensor Using Subthreshold Leakage Current to Detect Recycled ICs	8
ARXON: A Framework for Approximate Communication Over Photonic Networks-on-Chip	8
Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process	8
A Generalized Power Supply Induced Jitter Model Based on Power Supply Rejection Ratio Response	8
Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches	8
Design of FPGA-Implemented Reed–Solomon Erasure Code (RS-EC) Decoders With Fault Detection and Location on User Memory	8
A MOS-DTMOS Implementation of Floating Memristor Emulator for High-Frequency Applications	8
SCARE: Side Channel Attack on In-Memory Computing for Reverse Engineering	8
A High-Performance Dual-Topology CMOS Rectifier With 19.5-dB Power Dynamic Range for RF-Based Hybrid Energy Harvesting	8
High-Performance Concatenation Decoding of Reed–Solomon Codes With SPC Codes	8
PWL-Based Architecture for the Logarithmic Computation of Floating-Point Numbers	8
A Ku-Band Eight-Element Phased-Array Transmitter With Built-in Self-Test Capability in 180-nm CMOS Technology	8
Implementation of a Multipath Fully Differential OTA in 0.18-μm CMOS Process	8
THETA: A High-Efficiency Training Accelerator for DNNs With Triple-Side Sparsity Exploration	8
IMCA: An Efficient In-Memory Convolution Accelerator	8
A Miniaturized Wideband Interdigital Bandpass Filter With High Out-Band Suppression Based on TSV Technology for W-Band Application	7
Fast Modular Multipliers for Supersingular Isogeny-Based Post-Quantum Cryptography	7
An Error Compensation Technique for Low-Voltage DNN Accelerators	7
Exploring the Design of Energy-Efficient Intermittently Powered Systems Using Reconfigurable Ferroelectric Transistors	7
Cascode Cross-Coupled Stage High-Speed Dynamic Comparator in 65 nm CMOS	7
Fast and Low-Power Quantized Fixed Posit High-Accuracy DNN Implementation	7
Fast Hybrid Karatsuba Multiplier for Type II Pentanomials	7
Machine Learning Attack Resistant Area-Efficient Reconfigurable Ising-PUF	7
An Energy-Efficient Mixed-Bitwidth Systolic Accelerator for NAS-Optimized Deep Neural Networks	7
Configurable Memory With a Multilevel Shared Structure Enabling In-Memory Computing	7
A Wide-Range All-Digital Delay-Locked Loop for DDR1–DDR5 Applications	7
On Database-Free Authentication of Microelectronic Components	7
NS3K: A 3-nm Nanosheet FET Standard Cell Library Development and its Impact	7
An 8-Bit in Resistive Memory Computing Core With Regulated Passive Neuron and Bitline Weight Mapping	7
Cyclic Sparsely Connected Architectures for Compact Deep Convolutional Neural Networks	7
Speed/Area-Efficient ECC Processor Implementation Over GF(2 m ) on FPGA via Novel Algorithm-Architecture Co-Design	7
Multiplierless MP-Kernel Machine for Energy-Efficient Edge Devices	7
RPkNN: An OpenCL-Based FPGA Implementation of the Dimensionality-Reduced kNN Algorithm Using Random Projection	7
Vina-FPGA: A Hardware-Accelerated Molecular Docking Tool With Fixed-Point Quantization and Low-Level Parallelism	7
An Ultralow-Power OOK/BFSK/DBPSK Wake-Up Receiver Based on Injection-Locked Oscillator	7
ADIC: Anomaly Detection Integrated Circuit in 65-nm CMOS Utilizing Approximate Computing	7
LEAP: Lightweight and Efficient Accelerator for Sparse Polynomial Multiplication of HQC	7
RASHT: A Partially Reconfigurable Architecture for Efficient Implementation of CNNs	7
Energy-Efficient Logarithmic Square Rooter for Error-Resilient Applications	7
Adaptable Approximate Multiplier Design Based on Input Distribution and Polarity	7
RNN-Based Radio Resource Management on Multicore RISC-V Accelerator Architectures	7
EFFORT: A Comprehensive Technique to Tackle Timing Violations and Improve Energy Efficiency of Near-Threshold Tensor Processing Units	7
Sense: Model-Hardware Codesign for Accelerating Sparse CNNs on Systolic Arrays	7
Stochastic Computing Max & Min Architectures Using Markov Chains: Design, Analysis, and Implementation	7
A 0.0067-mm2 12-bit 20-MS/s SAR ADC Using Digital Place-and-Route Tools in 40-nm CMOS	7
FracTCAM: Fracturable LUTRAM-Based TCAM Emulation on Xilinx FPGAs	7
A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMSJitter, −258.7-dB FOM, and −75.17-dBc Reference Spur	7
Locking by Untuning: A Lock-Less Approach for Analog and Mixed-Signal IC Security	7
An M-Cache-Based Security Monitoring and Fault Recovery Architecture for Embedded Processor	7
A Reconfigurable Neural Network Processor With Tile-Grained Multicore Pipeline for Object Detection on FPGA	6
Low-Noise Distributed RC Oscillator	6
A 0.8-V, 2.55-GHz, 2.62-mW Charge-Pump PLL With High Spectrum Purity	6
Delay-Constrained GNR Routing for Layer Minimization	6
Energy-Efficient Multiple Network-on-Chip Architecture With Bandwidth Expansion	6
A 25–30-GHz RMS Error-Minimized 360° Continuous Analog Phase Shifter Using Closed-Loop Self-Tuning I/Q Generator	6
R2F: A Remote Retraining Framework for AIoT Processors With Computing Errors	6
Preprocessing of the Physical Leakage Information to Combine Side-Channel Distinguishers	6
A Sparse CNN Accelerator for Eliminating Redundant Computations in Intra- and Inter-Convolutional/Pooling Layers	6
Cross-Layer Approximate Hardware Synthesis for Runtime Configurable Accuracy	6
Energy-Efficient Time-Based Adaptive Encoding for Off-Chip Communication	6
A High-Speed Floating-Point Multiply-Accumulator Based on FPGAs	6
Low Flicker Dimmable Multichannel LED Driver With Matrix-Style DPWM and Precise Current Matching	6
A Twofold Clock and Voltage-Based Detection Method for Laser Logic State Imaging Attack	6
Design of SEU-Tolerant Turbo Decoders Implemented on SRAM-FPGAs	6
An 8.55–17.11-GHz DDS FMCW Chirp Synthesizer PLL Based on Double-Edge Zero-Crossing Sampling PD With 51.7-fsrms Jitter and Fast Frequency Hopping	6
SiPGuard: Run-Time System-in-Package Security Monitoring via Power Noise Variation	6
A Fully Digital SRAM-Based Four-Layer In-Memory Computing Unit Achieving Multiplication Operations and Results Store	6
An Improved MOS Self-Biased Ring Amplifier and Modified Auto-Zeroing Scheme	6
Architectural Exploration for Energy-Efficient Fixed-Point Kalman Filter VLSI Design	6
Ultra-Low Power SAR ADC Using Statistical Characteristics of Low-Activity Signals	6
FPGA Implementations of 256-Bit SNOW Stream Ciphers for Postquantum Mobile Security	6
On-Chip Thermal Profiling to Detect Malicious Activity: System-Level Concepts and Design of Key Building Blocks	6
Robust Security of Hardware Accelerators Using Protein Molecular Biometric Signature and Facial Biometric Encryption Key	6
Approximation of Transcendental Functions With Guaranteed Algorithmic QoS by Multilayer Pareto Optimization	6
A Generic Dynamic Responding Mechanism and Secure Authentication Protocol for Strong PUFs	6