IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Papers
(The median citation count of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is 1. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-03-01 to 2024-03-01.)
ArticleCitations
Architecture of Cobweb-Based Redundant TSV for Clustered Faults129
An Efficient Hardware Accelerator for Structured Sparse Convolutional Neural Networks on FPGAs67
High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell65
Cryptographic Accelerators for Digital Signature Based on Ed2551953
Flux-Controlled Memristor Emulator and Its Experimental Results50
Mixed-Signal Computing for Deep Neural Network Inference48
Low-Cost Stochastic Number Generators for Stochastic Computing45
FPnew: An Open-Source Multiformat Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing42
Stride 2 1-D, 2-D, and 3-D Winograd for Convolutional Neural Networks38
Novel Write-Enhanced and Highly Reliable RHPD-12T SRAM Cells for Space Applications36
Practical Implementation of Multichannel Filtered-x Least Mean Square Algorithm Based on the Multiple-Parallel-Branch With Folding Architecture for Large-Scale Active Noise Control35
ASSURE: RTL Locking Against an Untrusted Foundry34
Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators34
Design Methodology for Distributed Large-Scale ERSFQ Bias Networks33
PUF-Based Secure Chaotic Random Number Generator Design Methodology33
PLAC: Piecewise Linear Approximation Computation for All Nonlinear Unary Functions32
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse31
Uni-OPU: An FPGA-Based Uniform Accelerator for Convolutional and Transposed Convolutional Networks31
POLAR: A Pipelined/Overlapped FPGA-Based LSTM Accelerator31
Area-Efficient Nano-AES Implementation for Internet-of-Things Devices30
Design and Analysis of Approximate 4–2 Compressors for High-Accuracy Multipliers28
High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND28
In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands27
High-Performance Spintronic Nonvolatile Ternary Flip-Flop and Universal Shift Register27
Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory25
Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates25
SCOPE: Synthesis-Based Constant Propagation Attack on Logic Locking24
Design Exploration of Energy-Efficient Accuracy-Configurable Dadda Multipliers With Improved Lifetime Based on Voltage Overscaling24
GenMap: A Genetic Algorithmic Approach for Optimizing Spatial Mapping of Coarse-Grained Reconfigurable Architectures23
A 0.6-V Power-Efficient Active-RC Analog Low-Pass Filter With Cutoff Frequency Selection23
Designing Novel AAD Pooling in Hardware for a Convolutional Neural Network Accelerator23
Analysis of the Impact of Process Variations and Manufacturing Defects on the Performance of Carbon-Nanotube FETs22
A Twofold Lookup Table Architecture for Efficient Approximation of Activation Functions22
Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT21
Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes21
A 2–24-GHz 360° Full-Span Differential Vector Modulator Phase Rotator With Transformer-Based Poly-Phase Quadrature Network20
An Enhanced Input Differential Pair for Low-Voltage Bulk-Driven Amplifiers20
A 175.2-mW 4-Stage OTA With Wide Load Range (400 pF–12 nF) Using Active Parallel Compensation20
TxSim: Modeling Training of Deep Neural Networks on Resistive Crossbar Systems20
ADMM-Based Infinity-Norm Detection for Massive MIMO: Algorithm and VLSI Architecture20
TiM-DNN: Ternary In-Memory Accelerator for Deep Neural Networks20
SWM: A High-Performance Sparse-Winograd Matrix Multiplication CNN Accelerator19
DAD-FF: Hardening Designs by Delay-Adjustable D-Flip-Flop for Soft-Error-Rate Reduction19
Very Fast, High-Performance 5-2 and 7-2 Compressors in CMOS Process for Rapid Parallel Accumulations19
A Highly Unified Reconfigurable Multicore Architecture to Speed Up NTT/INTT for Homomorphic Polynomial Multiplication19
Unified Analog PUF and TRNG Based on Current-Steering DAC and VCO19
Computing-in-Memory for Performance and Energy-Efficient Homomorphic Encryption19
A 3.15-mW +16.0-dBm IIP3 22-dB CG Inductively Source Degenerated Balun-LNA Mixer With Integrated Transformer-Based Gate Inductor and IM2 Injection Technique19
Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System19
Efficient Architectures for Multigigabit CCSDS LDPC Encoders18
Real-Time SSDLite Object Detection on FPGA18
Low-Power Retentive True Single-Phase-Clocked Flip-Flop With Redundant-Precharge-Free Operation18
A 0.5-V Multiple-Input Bulk-Driven OTA in 0.18-μm CMOS18
ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators18
Heterogeneous Mixed-Signal Monolithic 3-D In-Memory Computing Using Resistive RAM18
Design of Approximate Booth Squarer for Error-Tolerant Computing18
Power Side-Channel Leakage Assessment Framework at Register-Transfer Level18
An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FGPA Implementation17
PCBChain: Lightweight Reconfigurable Blockchain Primitives for Secure IoT Applications17
SIXOR: Single-Cycle In-Memristor XOR17
PVHArray: An Energy-Efficient Reconfigurable Cryptographic Logic Array With Intelligent Mapping17
A 1036-F2/Bit High Reliability Temperature Compensated Cross-Coupled Comparator-Based PUF17
Efficient Mixed-Signal Neurocomputing Via Successive Integration and Rescaling17
Voltage Reference With Linear-Temperature-Dependent Power Consumption17
A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push–Pull SS-PD and a Fast-Locking FLL Achieving −82.2-dBc REF Spur and −255-dB FOM17
GH CORDIC-Based Architecture for Computing $N$ th Root of Single-Precision Floating-Point Number17
High-Performance COTS FPGA SoC for Parallel Hyperspectral Image Compression With CCSDS-123.0-B-117
Side-Channel Hardware Trojan for Provably-Secure SCA-Protected Implementations16
Physical Attack Protection Techniques for IC Chip Level Hardware Security16
SAT-Hard Cyclic Logic Obfuscation for Protecting the IP in the Manufacturing Supply Chain16
Gain-Cell Embedded DRAM Under Cryogenic Operation—A First Study16
Design and Implementation of Approximate DCT Architecture in Quantum-Dot Cellular Automata16
A 35-GHz TX and RX Front End With High TX Output Power for Ka-Band FMCW Phased-Array Radar Transceivers in CMOS Technology15
Reliable CRC-Based Error Detection Constructions for Finite Field Multipliers With Applications in Cryptography15
Memristive Computational Memory Using Memristor Overwrite Logic (MOL)15
A Highly Robust and Low-Power Real-Time Double Node Upset Self-Healing Latch for Radiation-Prone Applications15
Machine-Learning-Based Self-Tunable Design of Approximate Computing15
Parallel and Flexible 5G LDPC Decoder Architecture Targeting FPGA15
Dugdugi: An Optimal Fault Addressing Scheme for Octagon-Like On-Chip Communication Networks15
ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs15
Radiation-Hardened, Read-Disturbance-Free New-Quatro-10T Memory Cell for Aerospace Applications14
A 75-Gb/s/mm2 and Energy-Efficient LDPC Decoder Based on a Reduced Complexity Second Minimum Approximation Min-Sum Algorithm14
A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh14
Design Space Exploration for Chiplet-Assembly-Based Processors14
A Reinforcement Learning-Based Framework for Solving the IP Mapping Problem14
A Compact Low-Voltage True Random Number Generator Based on Inkjet Printing Technology14
FPGA Implementation of an Improved OMP for Compressive Sensing Reconstruction14
Securing Hardware Accelerators for CE Systems Using Biometric Fingerprinting14
An Algorithm–Hardware Co-Optimized Framework for Accelerating N:M Sparse Transformers14
Low Power Unsupervised Anomaly Detection by Nonparametric Modeling of Sensor Statistics14
High-Utilization, High-Flexibility Depth-First CNN Coprocessor for Image Pixel Processing on FPGA13
Multiple Sharing 7T1R Nonvolatile SRAM With an Improved Read/Write Margin and Reliable Restore Yield13
Fast Binary Counters and Compressors Generated by Sorting Network13
Soft Error Tolerant Convolutional Neural Networks on FPGAs With Ensemble Learning13
Background Calibration of Bit Weights in Pipelined-SAR ADCs Using Paired Comparators13
True Random Number Generation Using Latency Variations of FRAM13
A Second-Order Noise-Shaping SAR ADC Using Two Passive Integrators Separated by the Comparator13
Efficient Error Detection Architectures for Postquantum Signature Falcon’s Sampler and KEM SABER13
Power Distribution Attacks in Multitenant FPGAs13
An EEG-Based Hypnotic State Monitor for Patients During General Anesthesia13
High-Precision PLL Delay Matrix With Overclocking and Double Data Rate for Accurate FPGA Time-to-Digital Converters13
Performance and Accuracy Tradeoffs for Training Graph Neural Networks on ReRAM-Based Architectures12
Cache-Out: Leaking Cache Memory Using Hardware Trojan12
All-Digital Bandwidth Mismatch Calibration of TI-ADCs Based on Optimally Induced Minimization12
A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations12
High-Throughput/Low-Energy MTJ-Based True Random Number Generator Using a Multi-Voltage/Current Converter12
VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative12
Memristors Enabled Computing Correlation Parameter In-Memory System: A Potential Alternative to Von Neumann Architecture12
List-GRAND: A Practical Way to Achieve Maximum Likelihood Decoding12
A Multirate Fully Parallel LDPC Encoder for the IEEE 802.11n/ac/ax QC-LDPC Codes Based on Reduced Complexity XOR Trees12
A Timing Mismatch Background Calibration Algorithm With Improved Accuracy12
A New Hardware-Efficient Spectrum-Sensor VLSI Architecture for Data-Fusion-Based Cooperative Cognitive-Radio Network12
Multisymbol Architecture of the Entropy Coder for H.265/HEVC Video Encoders12
Radiation-Hardened 0.3–0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications12
Approximate Memory Compression11
A Hierarchical Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs11
All-Digital CMOS Time-to-Digital Converter With Temperature-Measuring Capability11
McPAT-Monolithic: An Area/Power/Timing Architecture Modeling Framework for 3-D Hybrid Monolithic Multicore Systems11
GreenTPU: Predictive Design Paradigm for Improving Timing Error Resilience of a Near-Threshold Tensor Processing Unit11
A Reconfigurable CMOS Rectifier With 14-dB Power Dynamic Range Achieving >36-dB/mm2 FoM for RF-Based Hybrid Energy Harvesting11
TSV-OCT: A Scalable Online Multiple-TSV Defects Localization for Real-Time 3-D-IC Systems11
A Three-Stage Comparator and Its Modified Version With Fast Speed and Low Kickback11
An IP Core Mapping Algorithm Based on Neural Networks11
Efficient Execution of Temporal Convolutional Networks for Embedded Keyword Spotting11
HarTBleed: Using Hardware Trojans for Data Leakage Exploits11
Improving TID Radiation Robustness of a CMOS OxRAM-Based Neuron Circuit by Using Enclosed Layout Transistors11
AdaTrust: Combinational Hardware Trojan Detection Through Adaptive Test Pattern Construction11
Anti-PVT-Variation Low-Power Time-to-Digital Converter Design Using 90-nm CMOS Process11
F-DNA: Fast Convolution Architecture for Deconvolutional Network Acceleration11
Breaking Analog Locking Techniques11
Low-Power, Low-Noise Edge-Race Comparator for SAR ADCs11
Area-Efficient Extended 3-D Inductor Based on TSV Technology for RF Applications11
Benchmark of the Compute-in-Memory-Based DNN Accelerator With Area Constraint11
Spreading Operation Frequency Ranges of Memristor Emulators via a New Sine-Based Method11
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation—Part I: CNFET Transistor Optimization11
AxPPA: Approximate Parallel Prefix Adders11
Verification of Scheduling of Conditional Behaviors in High-Level Synthesis10
Analysis of a Pipelined Architecture for Sparse DNNs on Embedded Systems10
FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators10
A Radiation-Hardened CMOS Full-Adder Based on Layout Selective Transistor Duplication10
A 14-bit 200-Ms/s SHA-Less Pipelined ADC With Aperture Error Reduction10
Analysis and Design of Unified Architectures for Zero-Attraction-Based Sparse Adaptive Filters10
A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n- and p-type Flip-Flops10
Applying Thermal Side-Channel Attacks on Asymmetric Cryptography10
Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits10
Recurrent Neural Networks With Column-Wise Matrix–Vector Multiplication on FPGAs10
A Multimode Configurable Physically Unclonable Function With Bit-Instability-Screening and Power-Gating Strategies10
Facial Biometric for Securing Hardware Accelerators10
Scheduling of Data Access for the Radix-2k FFT Processor Using Single-Port Memory10
A 2.4-GHz Area-Efficient and Fast-Locking Subharmonically Injection-Locked Type-I PLL10
Formal Modeling of Network-on-Chip Using CFSM and its Application in Detecting Deadlock10
Accurate On-Chip Temperature Sensing for Multicore Processors Using Embedded Thermal Sensors10
Time and Area Optimized Testing of Automotive ICs10
Integer Codes Correcting Double Errors and Triple-Adjacent Errors Within a Byte10
MeNTT: A Compact and Efficient Processing-in-Memory Number Theoretic Transform (NTT) Accelerator10
NeuPart: Using Analytical Models to Drive Energy-Efficient Partitioning of CNN Computations on Cloud-Connected Mobile Clients10
Designing Efficient and High-Performance AI Accelerators With Customized STT-MRAM10
Glitch-Optimized Circuit Blocks for Low-Power High-Performance Booth Multipliers10
A 215-F² Bistable Physically Unclonable Function With an ACF of <0.005 and a Native Bit Instability of 2.05% in 65-nm CMOS Process10
Inter-Tier Process-Variation-Aware Monolithic 3-D NoC Design Space Exploration9
Thermal-Aware Floorplanning and TSV-Planning for Mixed-Type Modules in a Fixed-Outline 3-D IC9
Hybrid Accumulator Factored Systolic Array for Machine Learning Acceleration9
Analog and Mixed-Signal Layout Automation Using Digital Place-and-Route Tools9
Nonscaling Adders and Subtracters for Stochastic Computing Using Markov Chains9
A 16-kb 9T Ultralow-Voltage SRAM With Column-Based Split Cell-VSS, Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28-nm FDSOI9
Performance and Security Analysis of Parameter-Obfuscated Analog Circuits9
An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power9
An Area-Efficient SAR ADC With Mismatch Error Shaping Technique Achieving 102-dB SFDR 90.2-dB SNDR Over 20-kHz Bandwidth9
Sub-1-V BGR and POR Hybrid Circuit With 2.25-μA Current Dissipation and Low Complexity9
A Configurable Floating-Point Multiple-Precision Processing Element for HPC and AI Converged Computing9
Ultralow-Power Localization of Insect-Scale Drones: Interplay of Probabilistic Filtering and Compute-in-Memory9
NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators9
Information Storage Bit-Flipping Decoder for LDPC Codes9
QEC: A Quantum Entropy Chip and Its Applications9
A Conversion Mode Reconfigurable SAR ADC for Multistandard Systems9
A High-Performance LDO Regulator Enabling Low-Power SoC With Voltage Scaling Approaches9
Interstice: Inverter-Based Memristive Neural Networks Discretization for Function Approximation Applications9
An Efficient Parallel DA-Based Fixed-Width Design for Approximate Inner-Product Computation9
A Programmable SoC-Based Accelerator for Privacy-Enhancing Technologies and Functional Encryption9
Detecting Hardware Trojans in PCBs Using Side Channel Loopbacks9
A 0.506-pJ 16-kb 8T SRAM With Vertical Read Wordlines and Selective Dual Split Power Lines9
RPE-TCAM: Reconfigurable Power-Efficient Ternary Content-Addressable Memory on FPGAs9
Analysis and Design of Current Mode Class-D Power Amplifiers With Finite Feeding Inductors9
A Power Analysis Attack Resistant Multicore Platform With Effective Randomization Techniques8
Programmable Daisychaining of Microelectrodes to Secure Bioassay IP in MEDA Biochips8
SCERPA Simulation of Clocked Molecular Field-Coupling Nanocomputing8
A High-Performance SIKE Hardware Accelerator8
Revisiting Stochastic Computing in the Era of Nanoscale Nonvolatile Technologies8
FN-CACTI: Advanced CACTI for FinFET and NC-FinFET Technologies8
Fast and Accurate Estimation of Statistical Eye Diagram for Nonlinear High-Speed Links8
Optimizing FPGA Logic Block Architectures for Arithmetic8
A 7.8-Gb/s 2.9-pJ/b Single-Ended Receiver With 20-Tap DFE for Highly Reflective Channels8
A Hybrid Miller-Cascode Compensation for Fast Settling in Two-Stage Operational Amplifiers8
A High-Speed Low-Noise Comparator With Auxiliary-Inverter-Based Common Mode-Self-Regulation for Low-Supply-Voltage SAR ADCs8
Low-Supply Sensitivity LC VCOs With Complementary Varactors8
A 23–36.8-GHz Low-Noise Frequency Synthesizer With a Fundamental Colpitts VCO Array in SiGe BiCMOS for 5G Applications8
VCO-Based Comparator: A Fully Adaptive Noise Scaling Comparator for High-Precision and Low-Power SAR ADCs8
A VLSI Majority-Logic Device Based on Spin Transfer Torque Mechanism for Brain-Inspired Computing Architecture8
A 3.85-Gb/s 8 × 8 Soft-Output MIMO Detector With Lattice-Reduction-Aided Channel Preprocessing8
A 32-Gb/s PAM-4 SST Transmitter With Four-Tap FFE Using High-Impedance Driver in 28-nm FDSOI8
A Fast Leakage-Aware Green’s-Function-Based Thermal Simulator for 3-D Chips8
Dataflow-Aware Macro Placement Based on Simulated Evolution Algorithm for Mixed-Size Designs8
Hardware Implementation of an OPC UA Server for Industrial Field Devices8
PWL-Based Architecture for the Logarithmic Computation of Floating-Point Numbers8
Optimizing FPGA Logic Circuitry for Variable Voltage Supplies8
An Area-Efficient High-Resolution Segmented ΣΔ-DAC for Built-In Self-Test Applications8
On Fast and Exact Computation of Error Metrics in Approximate LSB Adders7
A 300-mV Auto Shutdown Comparator-Based Continuous Time Δ∑ Modulator7
High-Performance Concatenation Decoding of Reed–Solomon Codes With SPC Codes7
IMCA: An Efficient In-Memory Convolution Accelerator7
High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors7
Golden-Free Hardware Trojan Detection Using Self-Referencing7
Communication-Aware Task Scheduling for Energy-Harvesting Nonvolatile Processors7
Cross-Layer Approximate Hardware Synthesis for Runtime Configurable Accuracy7
A 4.4-mA ESD-Safe 900-MHz LNA With 0.9-dB Noise Figure7
Optimization of Small-Delay Defects Test Quality by Clock Speed Selection and Proper Masking Based on the Weighted Slack Percentage7
Alternatives to Bicubic Interpolation Considering FPGA Hardware Resource Consumption7
A 0.3 nW, 0.093%/V Line Sensitivity, Temperature Compensated Bulk-Programmable Voltage Reference for Wireless Sensor Nodes7
SRAM Stability Analysis and Performance–Reliability Tradeoff for Different Cache Configurations7
An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC7
Hard-to-Detect Fault Analysis in FinFET SRAMs7
Development of a Short-Term to Long-Term Supervised Spiking Neural Network Processor7
CapCAM: A Multilevel Capacitive Content Addressable Memory for High-Accuracy and High-Scalability Search and Compute Applications7
A Multiring Julia Fractal Chaotic System With Separated-Scroll Attractors7
A Low-Power PAM4 Receiver With an Adaptive Variable-Gain Rectifier-Based Decoder7
A Generalized Power Supply Induced Jitter Model Based on Power Supply Rejection Ratio Response7
Variation-Aware Delay Fault Testing for Carbon-Nanotube FET Circuits7
Dynamic Workload Allocation for Edge Computing7
Secure XOR-CIM Engine: Compute-In-Memory SRAM Architecture With Embedded XOR Encryption7
Single-Layer Delay-Driven GNR Nontree Routing Under Resource Constraint for Yield Improvement7
A 12-Bit Two-Step Single-Slope ADC With a Constant Input-Common-Mode Level Resistor Ramp Generator7
An M-Cache-Based Security Monitoring and Fault Recovery Architecture for Embedded Processor7
An Optimized M-Term Karatsuba-Like Binary Polynomial Multiplier for Finite Field Arithmetic7
An Error Compensation Technique for Low-Voltage DNN Accelerators7
RNN-Based Radio Resource Management on Multicore RISC-V Accelerator Architectures7
A Time-Domain Reconfigurable Second-Order Noise Shaping ADC With Single Fan-Out Gated Delay Cells7
Differential Aging Sensor Using Subthreshold Leakage Current to Detect Recycled ICs7
Incremental Fault Analysis: Relaxing the Fault Model of Differential Fault Attacks7
Efficient Performance Modeling for Automated CMOS Analog Circuit Synthesis7
On Efficiency Enhancement of SHA-3 for FPGA-Based Multimodal Biometric Authentication7
A Pre-Activation, Golden IC Free, Hardware Trojan Detection Approach7
A Miniaturized Wideband Interdigital Bandpass Filter With High Out-Band Suppression Based on TSV Technology for W-Band Application6
A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI6
Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process6
A 64-Gb/s PAM-4 Optical Receiver With Amplitude/Phase Correction and Threshold Voltage/Data Level Calibration6
High-Dimensional Many-Objective Bayesian Optimization for LDE-Aware Analog IC Sizing6
SALE: Smartly Allocating Low-Cost Many-Bit ECC for Mitigating Read and Write Errors in STT-RAM Caches6
A Fast Settling Fractional-$N$ DPLL With Loop-Order Switching6
Approximation of Transcendental Functions With Guaranteed Algorithmic QoS by Multilayer Pareto Optimization6
pMOS Pass Gate Local Bitline SRAM Architecture With Virtual $V_{\mathrm{SS}}$ for Near-Threshold Operation6
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