IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Article	Citations
Cryptographic Accelerators for Digital Signature Based on Ed25519	72
An Efficient Hardware Accelerator for Structured Sparse Convolutional Neural Networks on FPGAs	72
Mixed-Signal Computing for Deep Neural Network Inference	62
Design Methodology for Distributed Large-Scale ERSFQ Bias Networks	51
FPnew: An Open-Source Multiformat Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing	49
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse	43
Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators	40
PLAC: Piecewise Linear Approximation Computation for All Nonlinear Unary Functions	38
Design and Analysis of Approximate 4–2 Compressors for High-Accuracy Multipliers	37
ASSURE: RTL Locking Against an Untrusted Foundry	37
Area-Efficient Nano-AES Implementation for Internet-of-Things Devices	35
Designing Novel AAD Pooling in Hardware for a Convolutional Neural Network Accelerator	33
SCOPE: Synthesis-Based Constant Propagation Attack on Logic Locking	32
High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND	31
High-Performance Spintronic Nonvolatile Ternary Flip-Flop and Universal Shift Register	30
Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates	29
Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes	29
A Twofold Lookup Table Architecture for Efficient Approximation of Activation Functions	29
Reliable Architectures for Finite Field Multipliers Using Cyclic Codes on FPGA Utilized in Classic and Post-Quantum Cryptography	28
Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory	28
GenMap: A Genetic Algorithmic Approach for Optimizing Spatial Mapping of Coarse-Grained Reconfigurable Architectures	25
A 0.5-V Multiple-Input Bulk-Driven OTA in 0.18-μm CMOS	25
A Highly Robust and Low-Power Real-Time Double Node Upset Self-Healing Latch for Radiation-Prone Applications	25
TxSim: Modeling Training of Deep Neural Networks on Resistive Crossbar Systems	24
A 2–24-GHz 360° Full-Span Differential Vector Modulator Phase Rotator With Transformer-Based Poly-Phase Quadrature Network	24

A 0.6-V Power-Efficient Active-RC Analog Low-Pass Filter With Cutoff Frequency Selection	23
Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT	23
A Highly Unified Reconfigurable Multicore Architecture to Speed Up NTT/INTT for Homomorphic Polynomial Multiplication	23
Unified Analog PUF and TRNG Based on Current-Steering DAC and VCO	23
Fast Binary Counters and Compressors Generated by Sorting Network	23
Parallel and Flexible 5G LDPC Decoder Architecture Targeting FPGA	22
ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators	22
An Enhanced Input Differential Pair for Low-Voltage Bulk-Driven Amplifiers	22
Computing-in-Memory for Performance and Energy-Efficient Homomorphic Encryption	22
An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FGPA Implementation	22
Low-Power Retentive True Single-Phase-Clocked Flip-Flop With Redundant-Precharge-Free Operation	22
SWM: A High-Performance Sparse-Winograd Matrix Multiplication CNN Accelerator	22
Power Side-Channel Leakage Assessment Framework at Register-Transfer Level	21
Physical Attack Protection Techniques for IC Chip Level Hardware Security	21
ADMM-Based Infinity-Norm Detection for Massive MIMO: Algorithm and VLSI Architecture	21
Efficient Error Detection Architectures for Postquantum Signature Falcon’s Sampler and KEM SABER	21
Real-Time SSDLite Object Detection on FPGA	21
An Algorithm–Hardware Co-Optimized Framework for Accelerating N:M Sparse Transformers	21
A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh	20
Heterogeneous Mixed-Signal Monolithic 3-D In-Memory Computing Using Resistive RAM	20
PCBChain: Lightweight Reconfigurable Blockchain Primitives for Secure IoT Applications	20
SIXOR: Single-Cycle In-Memristor XOR	20
Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System	20
High-Performance COTS FPGA SoC for Parallel Hyperspectral Image Compression With CCSDS-123.0-B-1	19
Memristors Enabled Computing Correlation Parameter In-Memory System: A Potential Alternative to Von Neumann Architecture	19
Reliable CRC-Based Error Detection Constructions for Finite Field Multipliers With Applications in Cryptography	19
FPGA Implementation of an Improved OMP for Compressive Sensing Reconstruction	19
Gain-Cell Embedded DRAM Under Cryogenic Operation—A First Study	19
A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push–Pull SS-PD and a Fast-Locking FLL Achieving −82.2-dBc REF Spur and −255-dB FOM	19
Memristive Computational Memory Using Memristor Overwrite Logic (MOL)	18
A Reconfigurable CMOS Rectifier With 14-dB Power Dynamic Range Achieving >36-dB/mm2 FoM for RF-Based Hybrid Energy Harvesting	18
A 35-GHz TX and RX Front End With High TX Output Power for Ka-Band FMCW Phased-Array Radar Transceivers in CMOS Technology	18
Design and Implementation of Approximate DCT Architecture in Quantum-Dot Cellular Automata	18
A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations	18
Machine-Learning-Based Self-Tunable Design of Approximate Computing	18
Securing Hardware Accelerators for CE Systems Using Biometric Fingerprinting	18
A Reinforcement Learning-Based Framework for Solving the IP Mapping Problem	17
Dugdugi: An Optimal Fault Addressing Scheme for Octagon-Like On-Chip Communication Networks	17
CRC-Based Error Detection Constructions for FLT and ITA Finite Field Inversions Over GF(2 m )	17
A New Hardware-Efficient Spectrum-Sensor VLSI Architecture for Data-Fusion-Based Cooperative Cognitive-Radio Network	16
High-Throughput/Low-Energy MTJ-Based True Random Number Generator Using a Multi-Voltage/Current Converter	16
A Timing Mismatch Background Calibration Algorithm With Improved Accuracy	16
Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS	16
Performance and Accuracy Tradeoffs for Training Graph Neural Networks on ReRAM-Based Architectures	15
True Random Number Generation Using Latency Variations of FRAM	15
A Multirate Fully Parallel LDPC Encoder for the IEEE 802.11n/ac/ax QC-LDPC Codes Based on Reduced Complexity XOR Trees	15
A Configurable Floating-Point Multiple-Precision Processing Element for HPC and AI Converged Computing	15
High-Utilization, High-Flexibility Depth-First CNN Coprocessor for Image Pixel Processing on FPGA	15
Power Distribution Attacks in Multitenant FPGAs	15
Sub-1-V BGR and POR Hybrid Circuit With 2.25-μA Current Dissipation and Low Complexity	14

VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative	14
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation—Part I: CNFET Transistor Optimization	14
A Second-Order Noise-Shaping SAR ADC Using Two Passive Integrators Separated by the Comparator	14
A Radiation-Hardened CMOS Full-Adder Based on Layout Selective Transistor Duplication	14
An EEG-Based Hypnotic State Monitor for Patients During General Anesthesia	14
Radiation-Hardened, Read-Disturbance-Free New-Quatro-10T Memory Cell for Aerospace Applications	14
Soft Error Tolerant Convolutional Neural Networks on FPGAs With Ensemble Learning	14
A Time-Domain Reconfigurable Second-Order Noise Shaping ADC With Single Fan-Out Gated Delay Cells	14
Low Power Unsupervised Anomaly Detection by Nonparametric Modeling of Sensor Statistics	14
Spreading Operation Frequency Ranges of Memristor Emulators via a New Sine-Based Method	14
List-GRAND: A Practical Way to Achieve Maximum Likelihood Decoding	14
F-DNA: Fast Convolution Architecture for Deconvolutional Network Acceleration	13
Ultralow-Power Localization of Insect-Scale Drones: Interplay of Probabilistic Filtering and Compute-in-Memory	13
Facial Biometric for Securing Hardware Accelerators	13
Designing Efficient and High-Performance AI Accelerators With Customized STT-MRAM	13
Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits	13
Anti-PVT-Variation Low-Power Time-to-Digital Converter Design Using 90-nm CMOS Process	13
A Three-Stage Comparator and Its Modified Version With Fast Speed and Low Kickback	13
Analog and Mixed-Signal Layout Automation Using Digital Place-and-Route Tools	13
NeuPart: Using Analytical Models to Drive Energy-Efficient Partitioning of CNN Computations on Cloud-Connected Mobile Clients	13
Breaking Analog Locking Techniques	13
A 12-Bit Two-Step Single-Slope ADC With a Constant Input-Common-Mode Level Resistor Ramp Generator	13
An IP Core Mapping Algorithm Based on Neural Networks	13
An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power	13
Hybrid Accumulator Factored Systolic Array for Machine Learning Acceleration	13
Recurrent Neural Networks With Column-Wise Matrix–Vector Multiplication on FPGAs	13
A −20-dBm Sensitivity RF Energy-Harvesting Rectifier Front End Using a Transformer IMN	12
Efficient Implementation of Dilithium Signature Scheme on FPGA SoC Platform	12
McPAT-Monolithic: An Area/Power/Timing Architecture Modeling Framework for 3-D Hybrid Monolithic Multicore Systems	12
Low-Power, Low-Noise Edge-Race Comparator for SAR ADCs	12
AdaTrust: Combinational Hardware Trojan Detection Through Adaptive Test Pattern Construction	12
Analysis of a Pipelined Architecture for Sparse DNNs on Embedded Systems	12
A 14-bit 200-Ms/s SHA-Less Pipelined ADC With Aperture Error Reduction	12
Detecting Hardware Trojans in PCBs Using Side Channel Loopbacks	12
All-Digital CMOS Time-to-Digital Converter With Temperature-Measuring Capability	12
NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators	12
Integer Codes Correcting Double Errors and Triple-Adjacent Errors Within a Byte	12
AxPPA: Approximate Parallel Prefix Adders	12
A 32-Gb/s PAM-4 SST Transmitter With Four-Tap FFE Using High-Impedance Driver in 28-nm FDSOI	12
A Hierarchical Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs	12
Improving TID Radiation Robustness of a CMOS OxRAM-Based Neuron Circuit by Using Enclosed Layout Transistors	12
Accurate On-Chip Temperature Sensing for Multicore Processors Using Embedded Thermal Sensors	12
Multisymbol Architecture of the Entropy Coder for H.265/HEVC Video Encoders	12
Cerebron: A Reconfigurable Architecture for Spatiotemporal Sparse Spiking Neural Networks	12
MeNTT: A Compact and Efficient Processing-in-Memory Number Theoretic Transform (NTT) Accelerator	12
A 2.4-GHz Area-Efficient and Fast-Locking Subharmonically Injection-Locked Type-I PLL	11
Applying Thermal Side-Channel Attacks on Asymmetric Cryptography	11
Benchmark of the Compute-in-Memory-Based DNN Accelerator With Area Constraint	11
A 16-kb 9T Ultralow-Voltage SRAM With Column-Based Split Cell-VSS, Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28-nm FDSOI	11
A 0.3-V 8.5-μ a Bulk-Driven OTA	11
Efficient Execution of Temporal Convolutional Networks for Embedded Keyword Spotting	11
Efficient Performance Modeling for Automated CMOS Analog Circuit Synthesis	11
On Efficiency Enhancement of SHA-3 for FPGA-Based Multimodal Biometric Authentication	11
FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators	11
A High-Performance and Low-Cost Single-Event Multiple-Node-Upsets Resilient Latch Design	11
Glitch-Optimized Circuit Blocks for Low-Power High-Performance Booth Multipliers	11
Area-Efficient Extended 3-D Inductor Based on TSV Technology for RF Applications	11
A 0.3 nW, 0.093%/V Line Sensitivity, Temperature Compensated Bulk-Programmable Voltage Reference for Wireless Sensor Nodes	11
A Multimode Configurable Physically Unclonable Function With Bit-Instability-Screening and Power-Gating Strategies	11
Design of DNN-Based Low-Power VLSI Architecture to Classify Atrial Fibrillation for Wearable Devices	10
A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n- and p-type Flip-Flops	10
Nonscaling Adders and Subtracters for Stochastic Computing Using Markov Chains	10
A Reconfigurable Multiple Transform Selection Architecture for VVC	10
An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC	10
A 3.85-Gb/s 8 × 8 Soft-Output MIMO Detector With Lattice-Reduction-Aided Channel Preprocessing	10
Thermal-Aware Floorplanning and TSV-Planning for Mixed-Type Modules in a Fixed-Outline 3-D IC	10
A High-Performance SIKE Hardware Accelerator	10
Hardware Implementation of an OPC UA Server for Industrial Field Devices	10
A Programmable SoC-Based Accelerator for Privacy-Enhancing Technologies and Functional Encryption	10
Time and Area Optimized Testing of Automotive ICs	10
A VLSI Majority-Logic Device Based on Spin Transfer Torque Mechanism for Brain-Inspired Computing Architecture	10
An Optimized M-Term Karatsuba-Like Binary Polynomial Multiplier for Finite Field Arithmetic	10
Low-Cost Online Convolution Checksum Checker	10
A High-Speed Low-Noise Comparator With Auxiliary-Inverter-Based Common Mode-Self-Regulation for Low-Supply-Voltage SAR ADCs	10
SCERPA Simulation of Clocked Molecular Field-Coupling Nanocomputing	10
A 215-F² Bistable Physically Unclonable Function With an ACF of <0.005 and a Native Bit Instability of 2.05% in 65-nm CMOS Process	10
Dynamic Workload Allocation for Edge Computing	10
Fast and Accurate Estimation of Statistical Eye Diagram for Nonlinear High-Speed Links	10
High-Dimensional Many-Objective Bayesian Optimization for LDE-Aware Analog IC Sizing	10
A Multiring Julia Fractal Chaotic System With Separated-Scroll Attractors	10

A 700-μm², Ring-Oscillator-Based Thermal Sensor in 16-nm FinFET	9
Golden-Free Hardware Trojan Detection Using Self-Referencing	9
Dataflow-Aware Macro Placement Based on Simulated Evolution Algorithm for Mixed-Size Designs	9
A 23–36.8-GHz Low-Noise Frequency Synthesizer With a Fundamental Colpitts VCO Array in SiGe BiCMOS for 5G Applications	9
VCO-Based Comparator: A Fully Adaptive Noise Scaling Comparator for High-Precision and Low-Power SAR ADCs	9
Secure XOR-CIM Engine: Compute-In-Memory SRAM Architecture With Embedded XOR Encryption	9
Information Storage Bit-Flipping Decoder for LDPC Codes	9
Analysis and Design of Magnetically Tuned W -Band Oscillators	9
A Hybrid Miller-Cascode Compensation for Fast Settling in Two-Stage Operational Amplifiers	9
Efficient Register Renaming Architectures for 8-bit AES Datapath at 0.55 pJ/bit in 16-nm FinFET	9
A 4.4-mA ESD-Safe 900-MHz LNA With 0.9-dB Noise Figure	9
An Area-Efficient SAR ADC With Mismatch Error Shaping Technique Achieving 102-dB SFDR 90.2-dB SNDR Over 20-kHz Bandwidth	9
Alternatives to Bicubic Interpolation Considering FPGA Hardware Resource Consumption	9
Performance and Security Analysis of Parameter-Obfuscated Analog Circuits	9
RPE-TCAM: Reconfigurable Power-Efficient Ternary Content-Addressable Memory on FPGAs	9
Golden Reference-Free Hardware Trojan Localization Using Graph Convolutional Network	9
A Conversion Mode Reconfigurable SAR ADC for Multistandard Systems	9
Compute-in-Memory Technologies and Architectures for Deep Learning Workloads	9
Revisiting Stochastic Computing in the Era of Nanoscale Nonvolatile Technologies	9
A More Accurate and Robust Binary Ring-LWE Decryption Scheme and Its Hardware Implementation for IoT Devices	9
Multiple-Mode-Supporting Floating-Point FMA Unit for Deep Learning Processors	9
ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator	9
An Area-Efficient High-Resolution Segmented ΣΔ-DAC for Built-In Self-Test Applications	8
IMCA: An Efficient In-Memory Convolution Accelerator	8
A Fast Leakage-Aware Green’s-Function-Based Thermal Simulator for 3-D Chips	8
A Low-Power PAM4 Receiver With an Adaptive Variable-Gain Rectifier-Based Decoder	8
ARXON: A Framework for Approximate Communication Over Photonic Networks-on-Chip	8
An Efficient CNN Accelerator Using Inter-Frame Data Reuse of Videos on FPGAs	8
A Fast Convergence Second-Order Compensation for Timing Skew in Time-Interleaved ADCs	8
A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI	8
Development of a Short-Term to Long-Term Supervised Spiking Neural Network Processor	8
THETA: A High-Efficiency Training Accelerator for DNNs With Triple-Side Sparsity Exploration	8
A Universal Efficient Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders	8
Differential Aging Sensor Using Subthreshold Leakage Current to Detect Recycled ICs	8
A High-Performance Dual-Topology CMOS Rectifier With 19.5-dB Power Dynamic Range for RF-Based Hybrid Energy Harvesting	8
PWL-Based Architecture for the Logarithmic Computation of Floating-Point Numbers	8
A Pre-Activation, Golden IC Free, Hardware Trojan Detection Approach	8
High-Performance Concatenation Decoding of Reed–Solomon Codes With SPC Codes	8
Low-Overhead Triple-Node-Upset-Tolerant Latch Design in 28-nm CMOS	8
A Ku-Band Eight-Element Phased-Array Transmitter With Built-in Self-Test Capability in 180-nm CMOS Technology	8
High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors	8
A 60-Mode High-Throughput Parallel-Processing FFT Processor for 5G/4G Applications	8
A Generalized Power Supply Induced Jitter Model Based on Power Supply Rejection Ratio Response	8
Digital Watermarking for Detecting Malicious Intellectual Property Cores in NoC Architectures	8
FN-CACTI: Advanced CACTI for FinFET and NC-FinFET Technologies	8
Machine Learning Attack Resistant Area-Efficient Reconfigurable Ising-PUF	7
ADIC: Anomaly Detection Integrated Circuit in 65-nm CMOS Utilizing Approximate Computing	7
Locking by Untuning: A Lock-Less Approach for Analog and Mixed-Signal IC Security	7
A 300-mV Auto Shutdown Comparator-Based Continuous Time Δ∑ Modulator	7
Approximate Softmax Functions for Energy-Efficient Deep Neural Networks	7
Hard-to-Detect Fault Analysis in FinFET SRAMs	7
Exploring the Design of Energy-Efficient Intermittently Powered Systems Using Reconfigurable Ferroelectric Transistors	7
CapCAM: A Multilevel Capacitive Content Addressable Memory for High-Accuracy and High-Scalability Search and Compute Applications	7
An Error Compensation Technique for Low-Voltage DNN Accelerators	7
Design and Evaluation of a Hybrid Chaotic-Bistable Ring PUF	7
Speed/Area-Efficient ECC Processor Implementation Over GF(2 m ) on FPGA via Novel Algorithm-Architecture Co-Design	7
A Multiband VCO Using a Switched Series Resonance for Fine Frequency Tuning Sensitivity and Phase Noise Improvement	7
FracTCAM: Fracturable LUTRAM-Based TCAM Emulation on Xilinx FPGAs	7
An Ultralow-Power OOK/BFSK/DBPSK Wake-Up Receiver Based on Injection-Locked Oscillator	7
Implementation of a Multipath Fully Differential OTA in 0.18-μm CMOS Process	7
An M-Cache-Based Security Monitoring and Fault Recovery Architecture for Embedded Processor	7
LEAP: Lightweight and Efficient Accelerator for Sparse Polynomial Multiplication of HQC	7
Cyclic Sparsely Connected Architectures for Compact Deep Convolutional Neural Networks	7
Fast Modular Multipliers for Supersingular Isogeny-Based Post-Quantum Cryptography	7
A MOS-DTMOS Implementation of Floating Memristor Emulator for High-Frequency Applications	7
Energy-Efficient Logarithmic Square Rooter for Error-Resilient Applications	7
SCARE: Side Channel Attack on In-Memory Computing for Reverse Engineering	7
Cascode Cross-Coupled Stage High-Speed Dynamic Comparator in 65 nm CMOS	7
Multiplierless MP-Kernel Machine for Energy-Efficient Edge Devices	7
A 0.0067-mm2 12-bit 20-MS/s SAR ADC Using Digital Place-and-Route Tools in 40-nm CMOS	7
A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMSJitter, −258.7-dB FOM, and −75.17-dBc Reference Spur	7
Variation-Aware Delay Fault Testing for Carbon-Nanotube FET Circuits	7
EM Side-Channel Countermeasure for Switched-Capacitor DC–DC Converters Based on Amplitude Modulation	7
A Wide-Range All-Digital Delay-Locked Loop for DDR1–DDR5 Applications	7
Design of FPGA-Implemented Reed–Solomon Erasure Code (RS-EC) Decoders With Fault Detection and Location on User Memory	7
EFFORT: A Comprehensive Technique to Tackle Timing Violations and Improve Energy Efficiency of Near-Threshold Tensor Processing Units	7
An 8-Bit in Resistive Memory Computing Core With Regulated Passive Neuron and Bitline Weight Mapping	7
Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process	7
RNN-Based Radio Resource Management on Multicore RISC-V Accelerator Architectures	7
A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks	7
Stochastic Computing Max & Min Architectures Using Markov Chains: Design, Analysis, and Implementation	7
A 2.56-GS/s 12-bit 8x-Interleaved ADC With 156.6-dB FoM S in 65-nm CMOS	7
Communication-Aware Task Scheduling for Energy-Harvesting Nonvolatile Processors	7
Configurable Memory With a Multilevel Shared Structure Enabling In-Memory Computing	6
Approximation of Transcendental Functions With Guaranteed Algorithmic QoS by Multilayer Pareto Optimization	6
Adaptable Approximate Multiplier Design Based on Input Distribution and Polarity	6
A Miniaturized Wideband Interdigital Bandpass Filter With High Out-Band Suppression Based on TSV Technology for W-Band Application	6
RASHT: A Partially Reconfigurable Architecture for Efficient Implementation of CNNs	6
Preprocessing of the Physical Leakage Information to Combine Side-Channel Distinguishers	6
Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches	6
Robust Security of Hardware Accelerators Using Protein Molecular Biometric Signature and Facial Biometric Encryption Key	6
R2F: A Remote Retraining Framework for AIoT Processors With Computing Errors	6
A Fully Digital SRAM-Based Four-Layer In-Memory Computing Unit Achieving Multiplication Operations and Results Store	6
A Reconfigurable Neural Network Processor With Tile-Grained Multicore Pipeline for Object Detection on FPGA	6
A 25–30-GHz RMS Error-Minimized 360° Continuous Analog Phase Shifter Using Closed-Loop Self-Tuning I/Q Generator	6