OOIR: Observatory of International Research

Papers

(The H4-Index of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is 26. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-08-01 to 2025-08-01.)

Article	Citations
Call for Applications and Nominations Search for the Editor-in-Chief of IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS	55
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	52
Behavioral Model for High-Speed SAR ADCs With On-Chip References	50
Hidden Costs of Analog Deobfuscation Attacks	50
Diagnostic Test Point Insertion and Test Compaction	49
ABS: Accumulation Bit-Width Scaling Method for Designing Low-Precision Tensor Core	48
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	41
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	41
HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization	41
Improved Step-GRAND: Low-Latency Soft-Input Guessing Random Additive Noise Decoding	40
Table of Contents	39
Protecting Parallel Data Encryption in Multi-Tenant FPGAs by Exploring Simple but Effective Clocking Methodologies	38
A High-Speed Dynamic Element Matching Decoder With Integrated Background Calibration Control	37
A Parallel Architecture and Implementation for Near-Lossless Hyperspectral Image Compression Based on CCSDS 123.0-B-2 With Scalable Data-Rate Performance	36
A Reconfigurable Neural Network Processor With Tile-Grained Multicore Pipeline for Object Detection on FPGA	35
High-Precision Low-Latency Method and Architecture for Computing Binary and Decimal Logarithms	35
A High-Performance SCNN Accelerator Using Parallel Sparsity Detection and Index-Oriented Computation Workflow	35
Highly Stable Reconfigurable TERO PUF Architecture for Hardware Security Applications	32
A Trifilar Transformer-Based Class-F₂₃ VCO With Noise-Circulating Technology	31
A 12-bit 2-GS/s Pipeline ADC in 28-nm CMOS With Linear-Error Self-Calibration	30
A Generic Dynamic Responding Mechanism and Secure Authentication Protocol for Strong PUFs	29
Built-In Self-Test of High-Density and Realistic ILV Layouts in Monolithic 3-D ICs	28
RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache Systems	27
Low-Overhead Triple-Node-Upset-Tolerant Latch Design in 28-nm CMOS	27
Signal and Power Integrity IO Buffer Modeling Under Separate Power and Ground Supply Voltage Variation of the Input and Output Stages	27

Analysis and Design of Magnetically Tuned W -Band Oscillators	26
Experimental Demonstration of Stochastic Bayesian Inference Using Müller C-Elements	26