OOIR: Observatory of International Research

Papers

(The H4-Index of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is 27. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-05-01 to 2025-05-01.)

Article	Citations
Call for Applications and Nominations Search for the Editor-in-Chief of IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS	104
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	51
RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache Systems	49
Behavioral Model for High-Speed SAR ADCs With On-Chip References	48
Hidden Costs of Analog Deobfuscation Attacks	45
HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization	44
A Parallel Architecture and Implementation for Near-Lossless Hyperspectral Image Compression Based on CCSDS 123.0-B-2 With Scalable Data-Rate Performance	41
ABS: Accumulation Bit-Width Scaling Method for Designing Low-Precision Tensor Core	38
Diagnostic Test Point Insertion and Test Compaction	38
A 12-bit 2-GS/s Pipeline ADC in 28-nm CMOS With Linear-Error Self-Calibration	37
Droplet Transportation in MEDA-Based Biochips: An Enhanced Technique for Intelligent Cross-Contamination Avoidance	37
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	36
Signal and Power Integrity IO Buffer Modeling Under Separate Power and Ground Supply Voltage Variation of the Input and Output Stages	36
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	35
Built-In Self-Test of High-Density and Realistic ILV Layouts in Monolithic 3-D ICs	34
Improved Step-GRAND: Low-Latency Soft-Input Guessing Random Additive Noise Decoding	33
Table of Contents	33
A Reconfigurable Neural Network Processor With Tile-Grained Multicore Pipeline for Object Detection on FPGA	32
Analysis and Design of Magnetically Tuned W -Band Oscillators	32
A Three-Stage Comparator and Its Modified Version With Fast Speed and Low Kickback	31
Protecting Parallel Data Encryption in Multi-Tenant FPGAs by Exploring Simple but Effective Clocking Methodologies	31
A High-Speed Dynamic Element Matching Decoder With Integrated Background Calibration Control	30
Low-Overhead Triple-Node-Upset-Tolerant Latch Design in 28-nm CMOS	30
A Generic Dynamic Responding Mechanism and Secure Authentication Protocol for Strong PUFs	29
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	29

Table of Contents	28
IEEE Transactions on Very Large Scale Integration (VLSI) Systems	28
High-Reliability and High-Throughput CIM 10T-SRAM for Multiplication and Accumulation Operations With 274.3 GOPS and 200–237.5 TOPS/W	27
SPICED+: Syntactical Bug Pattern Identification and Correction of Trojans in A/MS Circuits Using LLM-Enhanced Detection	27
IEEE Transactions on Very Large Scale Integration (VLSI) Systems	27
IEEE Women in Engineering	27