OOIR: Observatory of International Research

Papers

(The H4-Index of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is 31. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-08-01 to 2026-08-01.)

Article	Citations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	83
Call for Applications and Nominations Search for the Editor-in-Chief of IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS	72
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	71
A High-Performance SCNN Accelerator Using Parallel Sparsity Detection and Index-Oriented Computation Workflow	69
Table of Contents	66
Diagnostic Test Point Insertion and Test Compaction	65
ABS: Accumulation Bit-Width Scaling Method for Designing Low-Precision Tensor Core	58
High-Precision Low-Latency Method and Architecture for Computing Binary and Decimal Logarithms	51
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	50
Signal and Power Integrity IO Buffer Modeling Under Separate Power and Ground Supply Voltage Variation of the Input and Output Stages	48
FARMER: Online-Learning-Based Workload Consolidation on Large FPGAs Accelerated With Dynamic Partial Reconfiguration	48
An Efficient VLSI Architecture for Hammerstein-Type Spline Adaptive Filters	47
A High-Speed Dynamic Element Matching Decoder With Integrated Background Calibration Control	46
Hidden Costs of Analog Deobfuscation Attacks	45
ZuSE-KI-Mobil: AI Chip Design Platform for Automotive and Industrial Applications	44
A Parallel Architecture and Implementation for Near-Lossless Hyperspectral Image Compression Based on CCSDS 123.0-B-2 With Scalable Data-Rate Performance	43
Countering Side-Channel Attacks With a Dynamic S-Box Based on Affine Transformations and Gold Sequences	41
Protecting Parallel Data Encryption in Multi-Tenant FPGAs by Exploring Simple but Effective Clocking Methodologies	39
Efficient SoC Power Estimation With Machine Learning	37
A 12-bit 2-GS/s Pipeline ADC in 28-nm CMOS With Linear-Error Self-Calibration	37
VLSI Architecture for an Adaptive Transmission Estimation-Based Video Dehazing Method	36
A Fast and Energy-Efficient Level Shifter With Complementary Output Buffer for Energy-Constrained Systems	35
A Generalized Design Methodology for Multi-Input Collaborative-Flip Synchronized Switch Harvesting on Capacitors: From Theory to Optimization Strategy	35
ASTRA: Automated Insertion of Distributed Entropy Sources for Robust Authentication	35
FANE: FPGA-Based FP8 Approximate Neural Network Engine	35

Reconstructing Boolean Functions From MAGIC Logic-in-Memory Using Power Side-Channel Attacks	35
Defect-Aware Built-In Self-Test and Dynamic Repair for Fan-Out Wafer-Level Packaging	34
RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache Systems	34
Low-Overhead Triple-Node-Upset-Tolerant Latch Design in 28-nm CMOS	32
Built-In Self-Test of High-Density and Realistic ILV Layouts in Monolithic 3-D ICs	31
Highly Stable Reconfigurable TERO PUF Architecture for Hardware Security Applications	31
HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization	31