IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Papers
(The H4-Index of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is 25. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-03-01 to 2024-03-01.)
ArticleCitations
Architecture of Cobweb-Based Redundant TSV for Clustered Faults129
An Efficient Hardware Accelerator for Structured Sparse Convolutional Neural Networks on FPGAs67
High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell65
Cryptographic Accelerators for Digital Signature Based on Ed2551953
Flux-Controlled Memristor Emulator and Its Experimental Results50
Mixed-Signal Computing for Deep Neural Network Inference48
Low-Cost Stochastic Number Generators for Stochastic Computing45
FPnew: An Open-Source Multiformat Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing42
Stride 2 1-D, 2-D, and 3-D Winograd for Convolutional Neural Networks38
Novel Write-Enhanced and Highly Reliable RHPD-12T SRAM Cells for Space Applications36
Practical Implementation of Multichannel Filtered-x Least Mean Square Algorithm Based on the Multiple-Parallel-Branch With Folding Architecture for Large-Scale Active Noise Control35
Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators34
ASSURE: RTL Locking Against an Untrusted Foundry34
Design Methodology for Distributed Large-Scale ERSFQ Bias Networks33
PUF-Based Secure Chaotic Random Number Generator Design Methodology33
PLAC: Piecewise Linear Approximation Computation for All Nonlinear Unary Functions32
Uni-OPU: An FPGA-Based Uniform Accelerator for Convolutional and Transposed Convolutional Networks31
POLAR: A Pipelined/Overlapped FPGA-Based LSTM Accelerator31
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse31
Area-Efficient Nano-AES Implementation for Internet-of-Things Devices30
High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND28
Design and Analysis of Approximate 4–2 Compressors for High-Accuracy Multipliers28
In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands27
High-Performance Spintronic Nonvolatile Ternary Flip-Flop and Universal Shift Register27
Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates25
Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory25
0.035006046295166