OOIR: Observatory of International Research

Papers

(The H4-Index of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is 27. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-10-01 to 2025-10-01.)

Article	Citations
Call for Applications and Nominations Search for the Editor-in-Chief of IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS	60
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	57
Behavioral Model for High-Speed SAR ADCs With On-Chip References	57
Hidden Costs of Analog Deobfuscation Attacks	54
Diagnostic Test Point Insertion and Test Compaction	53
ABS: Accumulation Bit-Width Scaling Method for Designing Low-Precision Tensor Core	45
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	43
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	42
High-Precision Low-Latency Method and Architecture for Computing Binary and Decimal Logarithms	41
Experimental Demonstration of Stochastic Bayesian Inference Using Müller C-Elements	41
A Trifilar Transformer-Based Class-F₂₃ VCO With Noise-Circulating Technology	40
FARMER: Online-Learning-Based Workload Consolidation on Large FPGAs Accelerated With Dynamic Partial Reconfiguration	40
Improved Step-GRAND: Low-Latency Soft-Input Guessing Random Additive Noise Decoding	39
A High-Performance SCNN Accelerator Using Parallel Sparsity Detection and Index-Oriented Computation Workflow	39
A Parallel Architecture and Implementation for Near-Lossless Hyperspectral Image Compression Based on CCSDS 123.0-B-2 With Scalable Data-Rate Performance	38
Table of Contents	37
A Reconfigurable Neural Network Processor With Tile-Grained Multicore Pipeline for Object Detection on FPGA	37
Countering Side-Channel Attacks With a Dynamic S-Box Based on Affine Transformations and Gold Sequences	34
Protecting Parallel Data Encryption in Multi-Tenant FPGAs by Exploring Simple but Effective Clocking Methodologies	33
A 12-bit 2-GS/s Pipeline ADC in 28-nm CMOS With Linear-Error Self-Calibration	32
Built-In Self-Test of High-Density and Realistic ILV Layouts in Monolithic 3-D ICs	32
RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache Systems	30
A High-Speed Dynamic Element Matching Decoder With Integrated Background Calibration Control	28
Analysis and Design of Magnetically Tuned W -Band Oscillators	28
ZuSE-KI-Mobil: AI Chip Design Platform for Automotive and Industrial Applications	27

HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization	27
Signal and Power Integrity IO Buffer Modeling Under Separate Power and Ground Supply Voltage Variation of the Input and Output Stages	27