OOIR: Observatory of International Research

Papers

(The H4-Index of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is 25. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-11-01 to 2024-11-01.)

Article	Citations
Cryptographic Accelerators for Digital Signature Based on Ed25519	85
Mixed-Signal Computing for Deep Neural Network Inference	67
FPnew: An Open-Source Multiformat Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing	53
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse	53
Design Methodology for Distributed Large-Scale ERSFQ Bias Networks	51
Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators	45
ASSURE: RTL Locking Against an Untrusted Foundry	38
Design and Analysis of Approximate 4–2 Compressors for High-Accuracy Multipliers	38
Area-Efficient Nano-AES Implementation for Internet-of-Things Devices	37
Designing Novel AAD Pooling in Hardware for a Convolutional Neural Network Accelerator	37
SCOPE: Synthesis-Based Constant Propagation Attack on Logic Locking	34
High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND	34
High-Performance Spintronic Nonvolatile Ternary Flip-Flop and Universal Shift Register	32
Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes	31
A Twofold Lookup Table Architecture for Efficient Approximation of Activation Functions	31
Reliable Architectures for Finite Field Multipliers Using Cyclic Codes on FPGA Utilized in Classic and Post-Quantum Cryptography	31
Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates	29
Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory	28
GenMap: A Genetic Algorithmic Approach for Optimizing Spatial Mapping of Coarse-Grained Reconfigurable Architectures	28
A 2–24-GHz 360° Full-Span Differential Vector Modulator Phase Rotator With Transformer-Based Poly-Phase Quadrature Network	26
TxSim: Modeling Training of Deep Neural Networks on Resistive Crossbar Systems	26
A Highly Robust and Low-Power Real-Time Double Node Upset Self-Healing Latch for Radiation-Prone Applications	26
A 0.5-V Multiple-Input Bulk-Driven OTA in 0.18-μm CMOS	25
Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT	25
A Highly Unified Reconfigurable Multicore Architecture to Speed Up NTT/INTT for Homomorphic Polynomial Multiplication	25

An Enhanced Input Differential Pair for Low-Voltage Bulk-Driven Amplifiers	25
An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FGPA Implementation	25