OOIR: Observatory of International Research

Papers

(The H4-Index of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is 31. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-06-01 to 2026-06-01.)

Article	Citations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information	76
Call for Applications and Nominations Search for the Editor-in-Chief of IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS	72
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	67
A High-Performance SCNN Accelerator Using Parallel Sparsity Detection and Index-Oriented Computation Workflow	66
A Trifilar Transformer-Based Class-F₂₃ VCO With Noise-Circulating Technology	65
Behavioral Model for High-Speed SAR ADCs With On-Chip References	59
Table of Contents	59
Diagnostic Test Point Insertion and Test Compaction	55
ABS: Accumulation Bit-Width Scaling Method for Designing Low-Precision Tensor Core	52
HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization	49
High-Precision Low-Latency Method and Architecture for Computing Binary and Decimal Logarithms	46
Experimental Demonstration of Stochastic Bayesian Inference Using Müller C-Elements	45
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information	44
A Fast and Energy-Efficient Level Shifter With Complementary Output Buffer for Energy-Constrained Systems	44
FARMER: Online-Learning-Based Workload Consolidation on Large FPGAs Accelerated With Dynamic Partial Reconfiguration	43
Signal and Power Integrity IO Buffer Modeling Under Separate Power and Ground Supply Voltage Variation of the Input and Output Stages	43
ASTRA: Automated Insertion of Distributed Entropy Sources for Robust Authentication	42
An Efficient VLSI Architecture for Hammerstein-Type Spline Adaptive Filters	40
A High-Speed Dynamic Element Matching Decoder With Integrated Background Calibration Control	39
Hidden Costs of Analog Deobfuscation Attacks	38
Analysis and Design of Magnetically Tuned W -Band Oscillators	35
RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache Systems	35
Defect-Aware Built-In Self-Test and Dynamic Repair for Fan-Out Wafer-Level Packaging	35
Built-In Self-Test of High-Density and Realistic ILV Layouts in Monolithic 3-D ICs	35
Protecting Parallel Data Encryption in Multi-Tenant FPGAs by Exploring Simple but Effective Clocking Methodologies	34

A 12-bit 2-GS/s Pipeline ADC in 28-nm CMOS With Linear-Error Self-Calibration	32
Low-Overhead Triple-Node-Upset-Tolerant Latch Design in 28-nm CMOS	32
Efficient SoC Power Estimation With Machine Learning	32
A Generic Dynamic Responding Mechanism and Secure Authentication Protocol for Strong PUFs	31
FANE: FPGA-Based FP8 Approximate Neural Network Engine	31
A Parallel Architecture and Implementation for Near-Lossless Hyperspectral Image Compression Based on CCSDS 123.0-B-2 With Scalable Data-Rate Performance	31
ZuSE-KI-Mobil: AI Chip Design Platform for Automotive and Industrial Applications	31