OOIR: Observatory of International Research

Papers

(The TQCC of Journal of Electronic Testing-Theory and Applications is 2. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-11-01 to 2024-11-01.)

Article	Citations
Review of Manufacturing Process Defects and Their Effects on Memristive Devices	14
Spectrum Analyzer Based on a Dynamic Filter	14
Low-Cost Error Detection in Deep Neural Network Accelerators with Linear Algorithmic Checksums	13
SC-COTD: Hardware Trojan Detection Based on Sequential/Combinational Testability Features using Ensemble Classifier	13
Traxtor: An Automatic Software Test Suit Generation Method Inspired by Imperialist Competitive Optimization Algorithms	12
A Review of Various Defects in PCB	12
Design and Evaluation of XOR Arbiter Physical Unclonable Function and its Implementation on FPGA in Hardware Security Applications	10
A Source-code Aware Method for Software Mutation Testing Using Artificial Bee Colony Algorithm	10
Pre-Silicon Verification Using Multi-FPGA Platforms: A Review	10
Analysis of Security Vulnerability Levels of In-Vehicle Network Topologies Applying Graph Representations	9
Hardware Obfuscation for IP Protection of DSP Applications	9
Resistance of the Montgomery Ladder Against Simple SCA: Theory and Practice	9
Fault Diagnosis Method of Low Noise Amplifier Based on Support Vector Machine and Hidden Markov Model	7
Hardware Efficient Approximate Multiplier Architecture for Image Processing Applications	7
Fault Diagnosis of Linear Analog Electronic Circuit Based on Natural Response Specification using K-NN Algorithm	7
A Systematic Bit Selection Method for Robust SRAM PUFs	7
Novel Fault-Tolerant Processing in Memory Cell in Ternary Quantum-Dot Cellular Automata	7
Model Transferability from ImageNet to Lithography Hotspot Detection	7
Hardware Trojan Free Netlist Identification: A Clustering Approach	6
Aging Prediction and Tolerance for the SRAM Memory Cell and Sense Amplifier	6
A Low Power-Consumption Triple-Node-Upset-Tolerant Latch Design	5
Cross-PUF Attacks: Targeting FPGA Implementation of Arbiter-PUFs	5
A Novel Metaheuristic Based Method for Software Mutation Test Using the Discretized and Modified Forrest Optimization Algorithm	5
Retesting Defective Circuits to Allow Acceptable Faults for Yield Enhancement	5
Revisit to Histogram Method for ADC Linearity Test: Examination of Input Signal and Ratio of Input and Sampling Frequencies	5

Identifying Resistive Open Defects in Embedded Cells under Variations	5
Self Healing Controllers to Mitigate SEU in the Control Path of FPGA Based System: A Complete Intrinsic Evolutionary Approach	4
Design of Power Gated SRAM Cell for Reducing the NBTI Effect and Leakage Power Dissipation During the Hold Operation	4
Light Emission Tracking and Measurements for Analog Circuits Fault Diagnosis in Automotive Applications	4
Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications	4
Error-Efficient Approximate Multiplier Design using Rounding Based Approach for Image Smoothing Application	4
CMOS Implementation and Performance Analysis of Known Approximate 4:2 Compressors	4
Stress-Aware Periodic Test of Interconnects	4
Efficient Design of Rounding-Based Approximate Multiplier Using Modified Karatsuba Algorithm	4
Smell Detection Agent Optimization Approach to Path Generation in Automated Software Testing	4
AFIA: ATPG-Guided Fault Injection Attack on Secure Logic Locking	4
Parameterizable Real Number Models for Mixed-Signal Designs Using SystemVerilog	4
Research on the Reliability of Interconnected Solder Joints of Copper Pillars under Random Vibration	4
Reducing Aging Impacts in Digital Sensors via Run-Time Calibration	4
Automated Design Error Debugging of Digital VLSI Circuits	4
Neural Network-based Online Fault Diagnosis in Wireless-NoC Systems	3
Influence of Printed Circuit Board Dynamics on the Fretting Wear of Electronic Connectors: A Dynamic Analysis Approach	3
Investigation of the Impact of BTI Aging Phenomenon on Analog Amplifiers	3
A Survey of PCB Defect Detection Algorithms	3
Analysis and Detection of Open-gate Defects in Redundant Structures of a FinFET SRAM Cell	3
Multiple Retest Systems for Screening High-Quality Chips	3
Hardware Trojan Detection Method Based on Dual Discriminator Assisted Conditional Generation Adversarial Network	3
Single Particle Fault Injection Signal Generation Method Using Gaussian Cloud Model	3
A CatBoost Based Approach to Detect Label Flipping Poisoning Attack in Hardware Trojan Detection Systems	3
Design of INV/BUFF Logic Locking For Enhancing the Hardware Security	3
An Accurate Estimation Algorithm for Failure Probability of Logic Circuits Using Correlation Separation	3
Evaluation of a Two-Tier Adaptive Indirect Test Flow for a Front-End RF Circuit	3
Estimating Operational Age of an Integrated Circuit	2
Network-on-Chip and Photonic Network-on-Chip Basic Concepts: A Survey	2
On Reducing Test Data Volume for Circular Scan Architecture Using Modified Shuffled Shepherd Optimization	2
Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects	2
Soft Errors Sensitivity of SRAM Cells in Hold, Write, Read and Half-Selected Conditions	2
Method of Implanting Hardware Trojan Based on EHW in Part of Circuit	2
Low Area FPGA Implementation of AES Architecture with EPRNG for IoT Application	2
Applying Artificial Neural Networks to Logic Built-in Self-test: Improving Test Point Insertion	2
Effect of Sizing and Scaling on Power Dissipation and Resilience of an RHBD SRAM Circuit	2
Investigation of Single Event Effects in a Resistive RAM Memory Array by Coupling TCAD and SPICE Simulations	2
Fault-Aware Dependability Enhancement Techniques for Phase Change Memory	2
Deep Soft Error Propagation Modeling Using Graph Attention Network	2
A Bit-Error Rate Measurement and Error Analysis of Wireline Data Transmission using Current Source Model for Single Event Effect under Irradiation Environment	2
A New Neural Network Based on CNN for EMIS Identification	2
Comparison of the Output Parameters of the Memristor-based Op-amp Model and the Traditional Op-amp Model	2
A New Approximate 4-2 Compressor using Merged Sum and Carry	2
Achieving Agility in Projects Through Hierarchical Divisive Clustering Algorithm	2
Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits using Pipeline Stage Parallelism	2