Journal of Electronic Testing-Theory and Applications

Article	Citations
Read & Write Stability of CNTFET 6T SRAM Cell: A Comprehensive Analysis	20
Achieving Agility in Projects Through Hierarchical Divisive Clustering Algorithm	20
Using both Stable and Unstable SRAM Bits for the Physical Unclonable Function	15
Measurement and Simulation of the Near Magnetic Field Radiated by Integrated Magnetic Inductors	15
Comparison of Single Event Effect and Space Electrostatic Discharge Effect on FPGA Signal Transmission	15
Analysis of Combinational Circuit Failure Rate based on Graph Partitioning and Probabilistic Binomial Approach	14
Retesting Defective Circuits to Allow Acceptable Faults for Yield Enhancement	12
Design and Simulation of a Dependable Architecture Using Triple Modular Redundancy for Embedded Cyber-Physical Systems	12
Resistance of the Montgomery Ladder Against Simple SCA: Theory and Practice	11
On the Use of the Indirect Test Strategy for Lifetime Performance Monitoring of RF Circuits	10
Analysis of Security Vulnerability Levels of In-Vehicle Network Topologies Applying Graph Representations	10
Design and Verification of an Asynchronous NoC Router Architecture for GALS Systems	9
A Secure and Robust PUF-based Key Generation with Wiretap Polar Coset Codes	9
Spectrum Analyzer Based on a Dynamic Filter	8
Diagnosis of Analog and Digital Circuit Faults Using Exponential Deep Learning Neural Network	7
A Source-code Aware Method for Software Mutation Testing Using Artificial Bee Colony Algorithm	7
Smell Detection Agent Optimization Approach to Path Generation in Automated Software Testing	7
A New Approximate 4-2 Compressor using Merged Sum and Carry	6
Performance Efficient and Fault Tolerant Approximate Adder	6
Wafer-level Adaptive Testing Based on Dual-Predictor Collaborative Decision	6
Inherent Hardware Identifiers: Advancing IC Traceability and Provenance in the Multi-Die Era	6
Logic Locking Based Configurable Obfuscation Cell for Enhanced IC Security	6
Test Case Optimization using Machine Learning based Hybrid Meta-Heuristic Approach	5
The Newsletter of the Test Technology Technical Council of the IEEE Computer Society	5
Test Technology Newsletter	5

A Feature-Adaptive and Scalable Hardware Trojan Detection Framework For Third-party IPs Utilizing Multilevel Feature Analysis and Random Forest	5
Network-on-Chip and Photonic Network-on-Chip Basic Concepts: A Survey	5
Editorial	5
Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications	5
Investigation of Single Event Effects in a Resistive RAM Memory Array by Coupling TCAD and SPICE Simulations	5
Advancing Low Power BIST Architecture with GAN-Driven Test Pattern Optimization	5
Hardware Trojan Detection Method Based on Dual Discriminator Assisted Conditional Generation Adversarial Network	4
Cost-Effective Path Delay Defect Testing Using Voltage/Temperature Analysis Based on Pattern Permutation	4
CMOS Implementation and Performance Analysis of Known Approximate 4:2 Compressors	4
Neuro-Fuzzy Evaluation of the Software Reliability Models by Adaptive Neuro Fuzzy Inference System	4
A Flexible Concurrent Testing Scheme for Non-Feedback and Feedback Bridging Faults in Integrated Circuits	4
Comparison of the Output Parameters of the Memristor-based Op-amp Model and the Traditional Op-amp Model	4
Editorial	4
An End-to-End Mutually Exclusive Autoencoder Method for Analog Circuit Fault Diagnosis	4
Influence of Printed Circuit Board Dynamics on the Fretting Wear of Electronic Connectors: A Dynamic Analysis Approach	4
2021 JETTA-TTTC Best Paper Award	3
Self Healing Controllers to Mitigate SEU in the Control Path of FPGA Based System: A Complete Intrinsic Evolutionary Approach	3
Cross-PUF Attacks: Targeting FPGA Implementation of Arbiter-PUFs	3
Interleaved Counter Matrix Code in SRAM Memories for Continuous Adjacent Multiple Bit Upset Correction	3
Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift	3
2021 Reviewers	3
Editorial	3
Deep Soft Error Propagation Modeling Using Graph Attention Network	3
Development of a Simplified Programming Kit Based 16LF18856 for Embedded Systems Testing and Education in Developing Countries	3
2020 JETTA-TTTC Best Paper Award	3
2022 Reviewers	3
An Investigation into the Failure Characteristics of External PCB Traces with Different Angle Bends	3
Towards the Detection of Hardware Trojans with Cost Effective Test Vectors using Genetic Algorithm	2
Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits using Pipeline Stage Parallelism	2
Test Technology Newsletter	2
Instant Test and Repair for TSVs using Differential Signaling	2
Investigation of Silicon Aging Effects in Dopingless PUF for Reliable Security Solution	2
Multi-modal Pre-silicon Evaluation of Hardware Masking Styles	2
A Quadruple-Node Upsets Hardened Latch Design Based on Cross-Coupled Elements	2
Equivalent Circuit and Damage Threshold Study of Communication Interfaces under HEMP	2
A Tunable Concurrent BIST Design Based on Reconfigurable LFSR	2
New Second-order Threshold Implementation of Sm4 Block Cipher	2
Test Technology Newsletter	2
Syntactic and Semantic Analysis of Temporal Assertions to Support the Approximation of RTL Designs	2
Hardware Efficient Approximate Multiplier Architecture for Image Processing Applications	2
Automated Design Error Debugging of Digital VLSI Circuits	2
Research on the Mechanical Properties of Magnetorheological Damping and the Performance of Microprobe Test Process	2
Modular Test Kit – A Modular Approach for Efficient and Function-Oriented Testing	2
Online Diagnosis and Self-Recovery of Faulty Cells in Daisy-Chained MEDA Biochips Using Functional Actuation Patterns	1
Test Technology Newsletter	1
Structural and SCOAP Features Based Approach for Hardware Trojan Detection Using SHAP and Light Gradient Boosting Model	1
2023 JETTA-TTTC Best Paper Award	1
Hardware Trojan Free Netlist Identification: A Clustering Approach	1
Design and Verification of a SAR ADC SystemVerilog Real Number Model	1
Fault Detection and Diagnosis of DMFB Using Concurrent Electrodes Actuation	1

An Accurate Estimation Algorithm for Failure Probability of Logic Circuits Using Correlation Separation	1
Test Technology Newsletter	1
Design of INV/BUFF Logic Locking For Enhancing the Hardware Security	1
Design of Power Gated SRAM Cell for Reducing the NBTI Effect and Leakage Power Dissipation During the Hold Operation	1
An Analytical Model for Deposited Charge of Single Event Transient (SET) in FinFET	1
A Low Power-Consumption Triple-Node-Upset-Tolerant Latch Design	1
Editorial	1
Editorial	1
A Review of Various Defects in PCB	1
Non-Invasive Hardware Trojans Modeling and Insertion: A Formal Verification Approach	1
Editorial	1
Dynamic Smartcard Protection and SSELUR-GRU-Based Attack Stage Identification in Industrial IoT	1
Efficient Test and Characterization of Space Transmit-Receive Modules Using Scalable and Multipurpose Automated Test System	1
Hardware Obfuscation for IP Protection of DSP Applications	1
A Defect Detection Method of Mixed Wafer Map Using Neighborhood Path Filtering Clustering Algorithm	1
Analysis of the Lifecycles of Automotive Resistor Lead in Random Vibration	1
Investigating and Improving the Performance of Radiation-Hardened SRAM Cell with the Use of Multi-Voltage Transistors	1
Test Technology Newsletter	1
A High-Performance Quadruple-Node-Upset-Tolerant Latch Design and an Algorithm for Tolerance Verification of Hardened Latches	1
Incomplete Testing of SOC	1
Hybrid Ring Generators for In-System Testing	1
2023 JETTA Reviewers	1
A Low Bit Instability CMOS PUF Based on Current Mirrors and WTA Cells	1
Formal Verification of Universal Numbers using Theorem Proving	1
Editorial	1
Design and Evaluation of XOR Arbiter Physical Unclonable Function and its Implementation on FPGA in Hardware Security Applications	0
Test Technology Newsletter	0
Effect of Sizing and Scaling on Power Dissipation and Resilience of an RHBD SRAM Circuit	0
Reducing Aging Impacts in Digital Sensors via Run-Time Calibration	0
Editorial	0
YOLOv8-TDD: An Optimized YOLOv8 Algorithm for Targeted Defect Detection in Printed Circuit Boards	0
Editorial	0
Applying Artificial Neural Networks to Logic Built-in Self-test: Improving Test Point Insertion	0
TTTC Newsletter	0
Simulation-based Analysis of RPL Routing Attacks and Their Impact on IoT Network Performance	0
The Detection of Malicious Modifications in the FPGA	0
A Low-cost BIST Design Supporting Offline and Online Tests	0
FAMCroNA: Fault Analysis in Memristive Crossbars for Neuromorphic Applications	0
Phase Noise Analysis Performance Improvement, Testing and Stabilization of Microwave Frequency Source	0
Trade-off Mechanism Between Reliability and Performance for Data-flow Soft Error Detection	0
A Polynomial Transform Method for Hardware Systematic Error Identification and Correction in Semiconductor Multi-Site Testing	0
AFIA: ATPG-Guided Fault Injection Attack on Secure Logic Locking	0
Efficient Selective Image Fusion: A PCB Diagnosis Approach and Implementation	0
General Fault and Soft-Error Tolerant Phase-Locked Loop by Enhanced TMR using A Synchronization-before-Voting Scheme	0
BISCC: A Novel Approach to Built In State Consistency Checking For Quick Volume Validation of Mixed-Signal/RF Systems	0
Efficient Design of Rounding Based Static Segment Imprecise Multipliers for Error Tolerance Application	0
A Complete Design-for-Test Scheme for Reconfigurable Scan Networks	0
Modeling and Parasitic Extraction of the MM9 Transistor for GHz/THz CMOS RF Circuit Design	0
Test Technology Newsletter	0
Parameterizable Real Number Models for Mixed-Signal Designs Using SystemVerilog	0
Test Modules for Enhanced Testability of Single Flux Quantum Integrated Circuits	0
Fatigue Life Based Study of Electronic Package Mounting Locations on Printed Circuit Boards Subjected to Random Vibration Loads	0
Fault-Aware Test Case Prioritization in Software Testing Using Jaya Archimedes Optimization Algorithm	0
Evaluating the Reliability of Different Voting Schemes for Fault Tolerant Approximate Systems	0
Failure Mechanism and Sampling Frequency Dependency on TID Response of SAR ADCs	0
Light Emission Tracking and Measurements for Analog Circuits Fault Diagnosis in Automotive Applications	0
A SLvT Adaptive Test Method for Integrated Circuit Test Parameter Sets without Yield Loss	0
Generating Synthetic Layout Test Patterns using Deep Learning	0
A Survey of PCB Defect Detection Algorithms	0
Low Area FPGA Implementation of AES Architecture with EPRNG for IoT Application	0
Performances and Stability Analysis of a Novel 8T1R Non-Volatile SRAM (NVSRAM) versus Variability	0
Test Technology Newsletter	0
Editorial	0
Pebble Traversal-Based Fault Detection and Advanced Reconfiguration Technique for Digital Microfluidic Biochips	0
Review of Manufacturing Process Defects and Their Effects on Memristive Devices	0
An Automatic Software Testing Method to Discover Hard-to-Detect Faults Using Hybrid Olympiad Optimization Algorithm	0
Test Technology Newsletter	0
Effective Software Mutation-Test Using Program Instructions Classification	0
ADC Dynamic Parameter Testing Scheme Under Relaxed Conditions	0
Investigation of the Impact of BTI Aging Phenomenon on Analog Amplifiers	0
On Reducing Test Data Volume for Circular Scan Architecture Using Modified Shuffled Shepherd Optimization	0
Revisit to Histogram Method for ADC Linearity Test: Examination of Input Signal and Ratio of Input and Sampling Frequencies	0
Temperature and Humidity Controlled Test Bench for Temperature Sensor Characterization	0
Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits	0
Multiple Retest Systems for Screening High-Quality Chips	0
A Systematic Bit Selection Method for Robust SRAM PUFs	0
Identifying Resistive Open Defects in Embedded Cells under Variations	0
Efficient Design of Rounding-Based Approximate Multiplier Using Modified Karatsuba Algorithm	0
Synthesis of Reversible Circuits with Reduced Nearest-Neighbor Cost Using Kronecker Functional Decision Diagrams	0
Detection Method of Hardware Trojan Based on Attention Mechanism and Residual-Dense-Block under the Markov Transition Field	0

Intrinsic Based Self-healing Adder Design Using Chromosome Reconstruction Algorithm	0
Refined Self-calibration of an Inductorless Low-noise Amplifier with Non-intrusive Circuit	0
Verification and Validation with Prototype Chip Implemented with Layout Level Scan C-Elements	0
A CatBoost Based Approach to Detect Label Flipping Poisoning Attack in Hardware Trojan Detection Systems	0
DFS-KeyLevel: A Two-Layer Test Scenario Generation Approach for UML Activity Diagram	0
Editorial	0
A Survey and Recent Advances: Machine Intelligence in Electronic Testing	0
Editorial	0
Error-Efficient Approximate Multiplier Design using Rounding Based Approach for Image Smoothing Application	0
SEU Fault Injection Strategy for SRAM-based FPGA User Memory Based on Dual-Circuit Model	0
Editorial	0
Reactant and Waste Minimization during Sample Preparation on Micro-Electrode-Dot-Array Digital Microfluidic Biochips using Splitting Trees	0
Predicting Energy Dissipation in QCA-Based Layered-T Gates Under Cell Defects and Polarisation: A Study with Machine-Learning Models	0
Failure Probability due to Radiation-Induced Effects in FinFET SRAM Cells under Process Variations	0
Editorial	0
MATLAB-Open Source Tool Based Framework for Test Generation for Digital Circuits Using Evolutionary Algorithms	0
Radiation Hardened by Design-based Voltage Controlled Oscillator for Low Power Phase Locked Loop Application	0
Low Overhead and High Stability Radiation-Hardened Latch for Double/Triple Node Upsets	0
2024 Reviewers	0
Editorial	0
Design of a Low Noise Amplifier Based on Novel Monolayer Graphene FET	0
Research on the Reliability of Interconnected Solder Joints of Copper Pillars under Random Vibration	0
A Framework for Configurable Joint-Scan Design-for-Test Architecture	0
Traxtor: An Automatic Software Test Suit Generation Method Inspired by Imperialist Competitive Optimization Algorithms	0
Test Technology Newsletter	0
Sahand: A Software Fault-Prediction Method Using Autoencoder Neural Network and K-Means Algorithm	0
Journal of Electronic Testing: Theory and Applications New Editors – 2023	0
Editorial	0
PCB Defect Recognition by Image Analysis using Deep Convolutional Neural Network	0
Novel Fault-Tolerant Processing in Memory Cell in Ternary Quantum-Dot Cellular Automata	0
2022 JETTA-TTTC Best Paper Award	0
A Weighted-Bin Difference Method for Issue Site Identification in Analog and Mixed-Signal Multi-Site Testing	0
A Test Generation Method of R-2R Digital-to-Analog Converters Based on Genetic Algorithm	0
Analysis and Detection of Open-gate Defects in Redundant Structures of a FinFET SRAM Cell	0
Investigating and Reducing the Architectural Impact of Transient Faults in Special Function Units for GPUs	0
Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects	0
A Numeral System Based Framework for Improved One-Lambda Crosstalk Avoidance Code Using Recursive Symmetry Formula	0
Quantity Analysis Method for Text-Based Chip Test Datasets from Automated Test Equipment	0
Identification of Unknown Electromagnetic Interference Sources Based on Siamese-CNN	0
Multi-Objective Optimization Based Test Pattern Generation for Hardware Trojan Detection	0
Fault-Aware Dependability Enhancement Techniques for Phase Change Memory	0
A Bit-Error Rate Measurement and Error Analysis of Wireline Data Transmission using Current Source Model for Single Event Effect under Irradiation Environment	0
Formal Verification of a Dependable State Machine-Based Hardware Architecture for Safety-Critical Cyber-Physical Systems: Analysis, Design, and Implementation	0
E3C Techniques for Protecting NAND Flash Memories	0
A New Neural Network Based on CNN for EMIS Identification	0
A DfT Strategy for Guaranteeing ReRAM’s Quality after Manufacturing	0
Neural Network-based Online Fault Diagnosis in Wireless-NoC Systems	0
A Novel Two-Stage Model Based SCA against secAES	0
Editorial	0
Threshold Analysis Using Probabilistic Xgboost Classifier for Hardware Trojan Detection	0
Editorial	0
Stress-Aware Periodic Test of Interconnects	0
A Novel Metaheuristic Based Method for Software Mutation Test Using the Discretized and Modified Forrest Optimization Algorithm	0
Efficient Fault Detection by Test Case Prioritization via Test Case Selection	0
HVoC: a Hybrid Model Checking - Interactive Theorem Proving Approach for Functional Verification of Digital Circuits	0
Editorial	0
A Novel Framework For Optimal Test Case Generation and Prioritization Using Ent-LSOA And IMTRNN Techniques	0
Test Technology Newsletter	0
Experimental and Simulation Results of Wien Bridge Oscillator Circuıt Realized wıth Op-Amp Designed Using a Memristor	0
Reliability Analysis for a GaAs LNA with Temperature Stress	0
Editorial	0
New Editors – 2022	0
High-Dimensional Feature Fault Diagnosis Method Based on HEFS-LGBM	0
Research on Analog Integrated Circuit Test Parameter Set Reduction Based on XGBoost	0
SC-COTD: Hardware Trojan Detection Based on Sequential/Combinational Testability Features using Ensemble Classifier	0
Extreme Learning Machine Model For Multi-Fault Diagnosis of Analog Circuits	0
Editorial	0