Journal of Electronic Testing-Theory and Applications

Article	Citations
Using both Stable and Unstable SRAM Bits for the Physical Unclonable Function	36
Comparison of Single Event Effect and Space Electrostatic Discharge Effect on FPGA Signal Transmission	16
Achieving Agility in Projects Through Hierarchical Divisive Clustering Algorithm	15
Design and Simulation of a Dependable Architecture Using Triple Modular Redundancy for Embedded Cyber-Physical Systems	12
Analysis of Combinational Circuit Failure Rate based on Graph Partitioning and Probabilistic Binomial Approach	12
Artificial Neural Network Based Prediction Model for IR Drop Measurement in a VLSI Power Delivery Network	12
Read & Write Stability of CNTFET 6T SRAM Cell: A Comprehensive Analysis	12
Retesting Defective Circuits to Allow Acceptable Faults for Yield Enhancement	12
On the Use of the Indirect Test Strategy for Lifetime Performance Monitoring of RF Circuits	12
Analysis of Security Vulnerability Levels of In-Vehicle Network Topologies Applying Graph Representations	11
Design and Verification of an Asynchronous NoC Router Architecture for GALS Systems	9
A Source-code Aware Method for Software Mutation Testing Using Artificial Bee Colony Algorithm	9
Smell Detection Agent Optimization Approach to Path Generation in Automated Software Testing	9
Wafer-level Adaptive Testing Based on Dual-Predictor Collaborative Decision	8
Test Case Optimization using Machine Learning based Hybrid Meta-Heuristic Approach	8
Diagnosis of Analog and Digital Circuit Faults Using Exponential Deep Learning Neural Network	8
A New Approximate 4-2 Compressor using Merged Sum and Carry	7
A Feature-Adaptive and Scalable Hardware Trojan Detection Framework For Third-party IPs Utilizing Multilevel Feature Analysis and Random Forest	7
Logic Locking Based Configurable Obfuscation Cell for Enhanced IC Security	7
Inherent Hardware Identifiers: Advancing IC Traceability and Provenance in the Multi-Die Era	7
Performance Efficient and Fault Tolerant Approximate Adder	7
Investigation of Single Event Effects in a Resistive RAM Memory Array by Coupling TCAD and SPICE Simulations	7
The Newsletter of the Test Technology Technical Council of the IEEE Computer Society	6
A Flexible Concurrent Testing Scheme for Non-Feedback and Feedback Bridging Faults in Integrated Circuits	6
SFFHO: Development of Statistical Fitness-based Fire Hawk Optimizer for Software Testing and Maintenance Approach using Adaptive Deep Learning Method	6

Cost-Effective Path Delay Defect Testing Using Voltage/Temperature Analysis Based on Pattern Permutation	6
Editorial	6
Editorial	6
Network-on-Chip and Photonic Network-on-Chip Basic Concepts: A Survey	5
Development of a Simplified Programming Kit Based 16LF18856 for Embedded Systems Testing and Education in Developing Countries	5
An End-to-End Mutually Exclusive Autoencoder Method for Analog Circuit Fault Diagnosis	5
Advancing Low Power BIST Architecture with GAN-Driven Test Pattern Optimization	5
CMOS Implementation and Performance Analysis of Known Approximate 4:2 Compressors	5
Comparison of the Output Parameters of the Memristor-based Op-amp Model and the Traditional Op-amp Model	5
Hardware Trojan Detection Method Based on Dual Discriminator Assisted Conditional Generation Adversarial Network	5
Editorial	5
Firmware-Driven Adaptive Clock Tuning for Electromagnetic Interference Tolerance in Automotive Systems	4
2021 Reviewers	4
Self Healing Controllers to Mitigate SEU in the Control Path of FPGA Based System: A Complete Intrinsic Evolutionary Approach	4
2022 Reviewers	4
A Multi-Objective Test Scenario Prioritization Method Based on UML Activity Diagram	4
Influence of Printed Circuit Board Dynamics on the Fretting Wear of Electronic Connectors: A Dynamic Analysis Approach	4
2020 JETTA-TTTC Best Paper Award	4
Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits using Pipeline Stage Parallelism	4
Deep Soft Error Propagation Modeling Using Graph Attention Network	4
2021 JETTA-TTTC Best Paper Award	4
Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift	4
Interleaved Counter Matrix Code in SRAM Memories for Continuous Adjacent Multiple Bit Upset Correction	4
An Investigation into the Failure Characteristics of External PCB Traces with Different Angle Bends	4
Fault Diagnosis of Analog Circuits Using an Improved BiTCN Combined with BiLSTM	3
Instant Test and Repair for TSVs using Differential Signaling	3
A Quadruple-Node Upsets Hardened Latch Design Based on Cross-Coupled Elements	3
Chebyshev-based Algorithm: Achieving Fast ADC Static Parameter Testing Using a Low-precision Signal Source	3
A Method of Redundant Feature Suppression in Circuit Output Positions for Analog Circuit Soft and Hard Fault Diagnosis	3
Syntactic and Semantic Analysis of Temporal Assertions to Support the Approximation of RTL Designs	3
Real-time Embedded System Fault Injector Framework for Micro-architectural State Based Reliability Assessment	3
Hardware Efficient Approximate Multiplier Architecture for Image Processing Applications	3
Test Technology Newsletter	3
Towards the Detection of Hardware Trojans with Cost Effective Test Vectors using Genetic Algorithm	3
Cross-PUF Attacks: Targeting FPGA Implementation of Arbiter-PUFs	3
PrecIRisc: A High-Precision and Low-Bloat Dynamic Binary Instrumentation Tailored for RISC Architectures	2
Automated Design Error Debugging of Digital VLSI Circuits	2
New Second-order Threshold Implementation of Sm4 Block Cipher	2
Modular Test Kit – A Modular Approach for Efficient and Function-Oriented Testing	2
An Accurate Estimation Algorithm for Failure Probability of Logic Circuits Using Correlation Separation	2
Efficient Test and Characterization of Space Transmit-Receive Modules Using Scalable and Multipurpose Automated Test System	2
Equivalent Circuit and Damage Threshold Study of Communication Interfaces under HEMP	2
Research on the Mechanical Properties of Magnetorheological Damping and the Performance of Microprobe Test Process	2
A Tunable Concurrent BIST Design Based on Reconfigurable LFSR	2
Design of Power Gated SRAM Cell for Reducing the NBTI Effect and Leakage Power Dissipation During the Hold Operation	2
Formal Verification of Universal Numbers using Theorem Proving	2
Fault Detection and Diagnosis of DMFB Using Concurrent Electrodes Actuation	2
Test Technology Newsletter	2
Beyond Power Side Channels: Impedance as a Cryptographic Threat	2
Investigation of Silicon Aging Effects in Dopingless PUF for Reliable Security Solution	2

Multi-modal Pre-silicon Evaluation of Hardware Masking Styles	2
Hardware Obfuscation for IP Protection of DSP Applications	2
Dynamic Smartcard Protection and SSELUR-GRU-Based Attack Stage Identification in Industrial IoT	2
Design of INV/BUFF Logic Locking For Enhancing the Hardware Security	2
Analysis of the Lifecycles of Automotive Resistor Lead in Random Vibration	1
Verification and Validation with Prototype Chip Implemented with Layout Level Scan C-Elements	1
Editorial	1
A Low Power-Consumption Triple-Node-Upset-Tolerant Latch Design	1
A Survey and Recent Advances: Machine Intelligence in Electronic Testing	1
Test Technology Newsletter	1
Sushil Doranga Joins JETTA Editorial Board	1
PCB Defects: A Unified Survey of Trends, Detection Techniques, and Limitations through Systematic Literature Review	1
Editorial	1
An Analytical Model for Deposited Charge of Single Event Transient (SET) in FinFET	1
Hybrid Ring Generators for In-System Testing	1
A Low Bit Instability CMOS PUF Based on Current Mirrors and WTA Cells	1
On the Harmonic Locking of Ring Oscillators under Single ElectroMagnetic Pulsed Fault Injection in FPGAs	1
The Detection of Malicious Modifications in the FPGA	1
Structural and SCOAP Features Based Approach for Hardware Trojan Detection Using SHAP and Light Gradient Boosting Model	1
Small Delay Fault Testing with Multiple Voltages under Variations: Defect vs. Fault Coverage	1
BISCC: A Novel Approach to Built In State Consistency Checking For Quick Volume Validation of Mixed-Signal/RF Systems	1
Custom-Adaptive Kernel Strategies for Gaussian Process Regression in Wafer-Level Modeling and FPGA Delay Analysis	1
HT-Pred: An Extensive Methodology for Dataset Preparation and Hardware Trojan Prediction using Gate-Level Netlist	1
A High-Performance Quadruple-Node-Upset-Tolerant Latch Design and an Algorithm for Tolerance Verification of Hardened Latches	1
Incomplete Testing of SOC	1
Non-Invasive Hardware Trojans Modeling and Insertion: A Formal Verification Approach	1
Editorial	1
2023 JETTA Reviewers	1
2023 JETTA-TTTC Best Paper Award	1
A Polynomial Transform Method for Hardware Systematic Error Identification and Correction in Semiconductor Multi-Site Testing	1
Test Technology Newsletter	1
Investigating and Improving the Performance of Radiation-Hardened SRAM Cell with the Use of Multi-Voltage Transistors	1
Variability and Analog Parameter Characterization in Enclosed Layout Transistors	1
Efficient Design of Rounding-Based Approximate Multiplier Using Modified Karatsuba Algorithm	1
Enhanced Monte Carlo-Based Uncertainty Quantification in Electronic Circuits	1
A Review of Various Defects in PCB	1
Design and Verification of a SAR ADC SystemVerilog Real Number Model	1
Online Diagnosis and Self-Recovery of Faulty Cells in Daisy-Chained MEDA Biochips Using Functional Actuation Patterns	1
Editorial	1
A Defect Detection Method of Mixed Wafer Map Using Neighborhood Path Filtering Clustering Algorithm	1
Revisit to Histogram Method for ADC Linearity Test: Examination of Input Signal and Ratio of Input and Sampling Frequencies	0
Reliability Analysis for a GaAs LNA with Temperature Stress	0
Efficient Selective Image Fusion: A PCB Diagnosis Approach and Implementation	0
Stress-Aware Periodic Test of Interconnects	0
Editorial	0
Editorial	0
Predicting Energy Dissipation in QCA-Based Layered-T Gates Under Cell Defects and Polarisation: A Study with Machine-Learning Models	0
Calibration Impact on the Characterization of Components at Temperature	0
Uncertainty-Aware Crosstalk Predictors for Adaptive Reliability in Core Interconnects	0
Modelling, Simulation, and FPGA Implementation of an Augmented Memory Built-in Self-Test Based Design for Bit-Oriented Memory	0
Survey of Verification of RISC-V Processors	0
On Reducing Test Data Volume for Circular Scan Architecture Using Modified Shuffled Shepherd Optimization	0
Error-Efficient Approximate Multiplier Design using Rounding Based Approach for Image Smoothing Application	0
Evaluating the Reliability of Different Voting Schemes for Fault Tolerant Approximate Systems	0
Applying Artificial Neural Networks to Logic Built-in Self-test: Improving Test Point Insertion	0
Simulation-based Analysis of RPL Routing Attacks and Their Impact on IoT Network Performance	0
SNF-YOLOv8: A Lightweight PCB Defect Detection Algorithm base on Multiscale Feature Fusion and Attention Scale Sequence Fusion	0
Formal Verification of a Dependable State Machine-Based Hardware Architecture for Safety-Critical Cyber-Physical Systems: Analysis, Design, and Implementation	0
A Novel Defect Model Induced by a Single Dust Particle Contamination in the FinFET Gate Fingers	0
E3C Techniques for Protecting NAND Flash Memories	0
Research on Analog Integrated Circuit Test Parameter Set Reduction Based on XGBoost	0
A Complete Design-for-Test Scheme for Reconfigurable Scan Networks	0
Editorial	0
TTTC Newsletter	0
Novel Fault-Tolerant Processing in Memory Cell in Ternary Quantum-Dot Cellular Automata	0
Parameterizable Real Number Models for Mixed-Signal Designs Using SystemVerilog	0
Generating Synthetic Layout Test Patterns using Deep Learning	0
Editorial	0
A Bit-Error Rate Measurement and Error Analysis of Wireline Data Transmission using Current Source Model for Single Event Effect under Irradiation Environment	0
Fatigue Life Based Study of Electronic Package Mounting Locations on Printed Circuit Boards Subjected to Random Vibration Loads	0
Experimental and Simulation Results of Wien Bridge Oscillator Circuıt Realized wıth Op-Amp Designed Using a Memristor	0
A Novel Two-Stage Model Based SCA against secAES	0
Reactant and Waste Minimization during Sample Preparation on Micro-Electrode-Dot-Array Digital Microfluidic Biochips using Splitting Trees	0
Test Technology Newsletter	0
Fault-Aware Test Case Prioritization in Software Testing Using Jaya Archimedes Optimization Algorithm	0
Editorial	0
Design of a Low Noise Amplifier Based on Novel Monolayer Graphene FET	0
2022 JETTA-TTTC Best Paper Award	0
Low Overhead and High Stability Radiation-Hardened Latch for Double/Triple Node Upsets	0
A Low-cost BIST Design Supporting Offline and Online Tests	0

Traxtor: An Automatic Software Test Suit Generation Method Inspired by Imperialist Competitive Optimization Algorithms	0
Test Technology Newsletter	0
Low Area FPGA Implementation of AES Architecture with EPRNG for IoT Application	0
Efficient Design of Rounding Based Static Segment Imprecise Multipliers for Error Tolerance Application	0
Editorial	0
Editorial	0
Test Technology Newsletter	0
Temperature and Humidity Controlled Test Bench for Temperature Sensor Characterization	0
2024 Reviewers	0
PCB Defect Recognition by Image Analysis using Deep Convolutional Neural Network	0
Dynamic Fault Mitigation for Space Radiation Using Fault Injection and Machine Learning	0
A Test Generation Method of R-2R Digital-to-Analog Converters Based on Genetic Algorithm	0
Refined Self-calibration of an Inductorless Low-noise Amplifier with Non-intrusive Circuit	0
MATLAB-Open Source Tool Based Framework for Test Generation for Digital Circuits Using Evolutionary Algorithms	0
Editorial	0
FAMCroNA: Fault Analysis in Memristive Crossbars for Neuromorphic Applications	0
Identifying Resistive Open Defects in Embedded Cells under Variations	0
Editorial	0
Detection Method of Hardware Trojan Based on Attention Mechanism and Residual-Dense-Block under the Markov Transition Field	0
Trade-off Mechanism Between Reliability and Performance for Data-flow Soft Error Detection	0
New Editors – 2022	0
AFIA: ATPG-Guided Fault Injection Attack on Secure Logic Locking	0
Intrinsic Based Self-healing Adder Design Using Chromosome Reconstruction Algorithm	0
Identification of Unknown Electromagnetic Interference Sources Based on Siamese-CNN	0
Test Technology Newsletter	0
A New Neural Network Based on CNN for EMIS Identification	0
Light Emission Tracking and Measurements for Analog Circuits Fault Diagnosis in Automotive Applications	0
DFS-KeyLevel: A Two-Layer Test Scenario Generation Approach for UML Activity Diagram	0
Test Technology Newsletter	0
Editorial	0
YOLOv8-TDD: An Optimized YOLOv8 Algorithm for Targeted Defect Detection in Printed Circuit Boards	0
SEU Fault Injection Strategy for SRAM-based FPGA User Memory Based on Dual-Circuit Model	0
A Weighted-Bin Difference Method for Issue Site Identification in Analog and Mixed-Signal Multi-Site Testing	0
Editorial	0
A Novel Framework For Optimal Test Case Generation and Prioritization Using Ent-LSOA And IMTRNN Techniques	0
Synthesis of Reversible Circuits with Reduced Nearest-Neighbor Cost Using Kronecker Functional Decision Diagrams	0
High-Dimensional Feature Fault Diagnosis Method Based on HEFS-LGBM	0
Investigating and Reducing the Architectural Impact of Transient Faults in Special Function Units for GPUs	0
Effective Software Mutation-Test Using Program Instructions Classification	0
Failure Analysis and Power-on Sequence Optimization for InP DHBT Stacked Amplifiers	0
Journal of Electronic Testing: Theory and Applications New Editors – 2023	0
Analysis and Modeling of Single Event Transient Generation in Standard Combinational Cells	0
A Systematic Bit Selection Method for Robust SRAM PUFs	0
Editorial	0
Test Technology Newsletter	0
Editorial	0
A Framework for Configurable Joint-Scan Design-for-Test Architecture	0
Reducing Aging Impacts in Digital Sensors via Run-Time Calibration	0
ADC Dynamic Parameter Testing Scheme Under Relaxed Conditions	0
Sahand: A Software Fault-Prediction Method Using Autoencoder Neural Network and K-Means Algorithm	0
Test Modules for Enhanced Testability of Single Flux Quantum Integrated Circuits	0
Multiple Retest Systems for Screening High-Quality Chips	0
Multi-Objective Optimization Based Test Pattern Generation for Hardware Trojan Detection	0
Design and Evaluation of XOR Arbiter Physical Unclonable Function and its Implementation on FPGA in Hardware Security Applications	0
Phase Noise Analysis Performance Improvement, Testing and Stabilization of Microwave Frequency Source	0
Quantity Analysis Method for Text-Based Chip Test Datasets from Automated Test Equipment	0
Analyzing the Effectiveness of Various NMOS Layouts for Total Ionizing Dose Hardening in 180nm CMOS	0
Radiation Hardened by Design-based Voltage Controlled Oscillator for Low Power Phase Locked Loop Application	0
A CatBoost Based Approach to Detect Label Flipping Poisoning Attack in Hardware Trojan Detection Systems	0
General Fault and Soft-Error Tolerant Phase-Locked Loop by Enhanced TMR using A Synchronization-before-Voting Scheme	0
Pebble Traversal-Based Fault Detection and Advanced Reconfiguration Technique for Digital Microfluidic Biochips	0
Research on the Reliability of Interconnected Solder Joints of Copper Pillars under Random Vibration	0
Threshold Analysis Using Probabilistic Xgboost Classifier for Hardware Trojan Detection	0
Editorial	0
An Automatic Software Testing Method to Discover Hard-to-Detect Faults Using Hybrid Olympiad Optimization Algorithm	0
A Survey of PCB Defect Detection Algorithms	0
A YOLOv9: Deep Learning-based Framework Defect Detection Method for PCBs	0
Modeling and Parasitic Extraction of the MM9 Transistor for GHz/THz CMOS RF Circuit Design	0
Efficient Fault Detection by Test Case Prioritization via Test Case Selection	0
Editorial	0
A Novel Metaheuristic Based Method for Software Mutation Test Using the Discretized and Modified Forrest Optimization Algorithm	0
Cross-Domain Multi-Label Prediction of Metamorphic Relation Patterns Leveraging Multimodal Features	0
Failure Probability due to Radiation-Induced Effects in FinFET SRAM Cells under Process Variations	0
Effect of Sizing and Scaling on Power Dissipation and Resilience of an RHBD SRAM Circuit	0
A SLvT Adaptive Test Method for Integrated Circuit Test Parameter Sets without Yield Loss	0
A DfT Strategy for Guaranteeing ReRAM’s Quality after Manufacturing	0
Extreme Learning Machine Model For Multi-Fault Diagnosis of Analog Circuits	0