OOIR: Observatory of International Research

Papers

(The median citation count of Journal of Electronic Testing-Theory and Applications is 1. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-01-01 to 2026-01-01.)

Article	Citations
Using both Stable and Unstable SRAM Bits for the Physical Unclonable Function	39
Comparison of Single Event Effect and Space Electrostatic Discharge Effect on FPGA Signal Transmission	19
Achieving Agility in Projects Through Hierarchical Divisive Clustering Algorithm	16
On the Use of the Indirect Test Strategy for Lifetime Performance Monitoring of RF Circuits	13
Analysis of Combinational Circuit Failure Rate based on Graph Partitioning and Probabilistic Binomial Approach	13
Read & Write Stability of CNTFET 6T SRAM Cell: A Comprehensive Analysis	13
Design and Verification of an Asynchronous NoC Router Architecture for GALS Systems	12
Artificial Neural Network Based Prediction Model for IR Drop Measurement in a VLSI Power Delivery Network	12
Smell Detection Agent Optimization Approach to Path Generation in Automated Software Testing	12
Design and Simulation of a Dependable Architecture Using Triple Modular Redundancy for Embedded Cyber-Physical Systems	12
A Source-code Aware Method for Software Mutation Testing Using Artificial Bee Colony Algorithm	10
A New Approximate 4-2 Compressor using Merged Sum and Carry	9
Test Case Optimization using Machine Learning based Hybrid Meta-Heuristic Approach	9
Performance Efficient and Fault Tolerant Approximate Adder	8
Diagnosis of Analog and Digital Circuit Faults Using Exponential Deep Learning Neural Network	8
Logic Locking Based Configurable Obfuscation Cell for Enhanced IC Security	8
Investigation of Single Event Effects in a Resistive RAM Memory Array by Coupling TCAD and SPICE Simulations	8
Inherent Hardware Identifiers: Advancing IC Traceability and Provenance in the Multi-Die Era	8
A Feature-Adaptive and Scalable Hardware Trojan Detection Framework For Third-party IPs Utilizing Multilevel Feature Analysis and Random Forest	7
The Newsletter of the Test Technology Technical Council of the IEEE Computer Society	7
A Program-Output Estimator for Software Testing Using Program Analysis and Deep Learning Algorithms	7
Wafer-level Adaptive Testing Based on Dual-Predictor Collaborative Decision	7
Enhanced Moth Flame Optimization Algorithm Entropy-Based Centroid SVM-Based Software Defect Prediction	7
Editorial	6
Editorial	6

SFFHO: Development of Statistical Fitness-based Fire Hawk Optimizer for Software Testing and Maintenance Approach using Adaptive Deep Learning Method	6
Advancing Low Power BIST Architecture with GAN-Driven Test Pattern Optimization	5
Editorial	5
Network-on-Chip and Photonic Network-on-Chip Basic Concepts: A Survey	5
Comparison of the Output Parameters of the Memristor-based Op-amp Model and the Traditional Op-amp Model	5
Cost-Effective Path Delay Defect Testing Using Voltage/Temperature Analysis Based on Pattern Permutation	5
Development of a Simplified Programming Kit Based 16LF18856 for Embedded Systems Testing and Education in Developing Countries	5
Hardware Trojan Detection Method Based on Dual Discriminator Assisted Conditional Generation Adversarial Network	5
A Flexible Concurrent Testing Scheme for Non-Feedback and Feedback Bridging Faults in Integrated Circuits	5
Firmware-Driven Adaptive Clock Tuning for Electromagnetic Interference Tolerance in Automotive Systems	5
An End-to-End Mutually Exclusive Autoencoder Method for Analog Circuit Fault Diagnosis	5
Influence of Printed Circuit Board Dynamics on the Fretting Wear of Electronic Connectors: A Dynamic Analysis Approach	4
2021 Reviewers	4
A Multi-Objective Test Scenario Prioritization Method Based on UML Activity Diagram	4
An Investigation into the Failure Characteristics of External PCB Traces with Different Angle Bends	4
CMOS Implementation and Performance Analysis of Known Approximate 4:2 Compressors	4
Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift	4
Interleaved Counter Matrix Code in SRAM Memories for Continuous Adjacent Multiple Bit Upset Correction	4
Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits using Pipeline Stage Parallelism	4
2021 JETTA-TTTC Best Paper Award	4
Self Healing Controllers to Mitigate SEU in the Control Path of FPGA Based System: A Complete Intrinsic Evolutionary Approach	4
2022 Reviewers	4
Chebyshev-based Algorithm: Achieving Fast ADC Static Parameter Testing Using a Low-precision Signal Source	3
Real-time Embedded System Fault Injector Framework for Micro-architectural State Based Reliability Assessment	3
Instant Test and Repair for TSVs using Differential Signaling	3
Cross-PUF Attacks: Targeting FPGA Implementation of Arbiter-PUFs	3
Deep Soft Error Propagation Modeling Using Graph Attention Network	3
Hardware Efficient Approximate Multiplier Architecture for Image Processing Applications	3
Syntactic and Semantic Analysis of Temporal Assertions to Support the Approximation of RTL Designs	3
A Quadruple-Node Upsets Hardened Latch Design Based on Cross-Coupled Elements	3
Fault Diagnosis of Analog Circuits Using an Improved BiTCN Combined with BiLSTM	3
Test Technology Newsletter	3
A Method of Redundant Feature Suppression in Circuit Output Positions for Analog Circuit Soft and Hard Fault Diagnosis	3
Dynamic Smartcard Protection and SSELUR-GRU-Based Attack Stage Identification in Industrial IoT	2
Fault Detection and Diagnosis of DMFB Using Concurrent Electrodes Actuation	2
Design of Power Gated SRAM Cell for Reducing the NBTI Effect and Leakage Power Dissipation During the Hold Operation	2
New Second-order Threshold Implementation of Sm4 Block Cipher	2
Equivalent Circuit and Damage Threshold Study of Communication Interfaces under HEMP	2
Beyond Power Side Channels: Impedance as a Cryptographic Threat	2
Modular Test Kit – A Modular Approach for Efficient and Function-Oriented Testing	2
An Accurate Estimation Algorithm for Failure Probability of Logic Circuits Using Correlation Separation	2
Design of INV/BUFF Logic Locking For Enhancing the Hardware Security	2
A Low Bit Instability CMOS PUF Based on Current Mirrors and WTA Cells	2
A Tunable Concurrent BIST Design Based on Reconfigurable LFSR	2
Investigation of Silicon Aging Effects in Dopingless PUF for Reliable Security Solution	2
Towards the Detection of Hardware Trojans with Cost Effective Test Vectors using Genetic Algorithm	2
Multi-modal Pre-silicon Evaluation of Hardware Masking Styles	2
Efficient Test and Characterization of Space Transmit-Receive Modules Using Scalable and Multipurpose Automated Test System	2
Formal Verification of Universal Numbers using Theorem Proving	2
A Defect Detection Method of Mixed Wafer Map Using Neighborhood Path Filtering Clustering Algorithm	2

2023 JETTA Reviewers	2
Test Technology Newsletter	2
Research on the Mechanical Properties of Magnetorheological Damping and the Performance of Microprobe Test Process	2
PrecIRisc: A High-Precision and Low-Bloat Dynamic Binary Instrumentation Tailored for RISC Architectures	2
Automated Design Error Debugging of Digital VLSI Circuits	2
Hardware Obfuscation for IP Protection of DSP Applications	2
A New Neural Network Based on CNN for EMIS Identification	1
HT-Pred: An Extensive Methodology for Dataset Preparation and Hardware Trojan Prediction using Gate-Level Netlist	1
BISCC: A Novel Approach to Built In State Consistency Checking For Quick Volume Validation of Mixed-Signal/RF Systems	1
A Low Power-Consumption Triple-Node-Upset-Tolerant Latch Design	1
Investigating and Improving the Performance of Radiation-Hardened SRAM Cell with the Use of Multi-Voltage Transistors	1
Incomplete Testing of SOC	1
Custom-Adaptive Kernel Strategies for Gaussian Process Regression in Wafer-Level Modeling and FPGA Delay Analysis	1
A High-Performance Quadruple-Node-Upset-Tolerant Latch Design and an Algorithm for Tolerance Verification of Hardened Latches	1
On the Harmonic Locking of Ring Oscillators under Single ElectroMagnetic Pulsed Fault Injection in FPGAs	1
Online Diagnosis and Self-Recovery of Faulty Cells in Daisy-Chained MEDA Biochips Using Functional Actuation Patterns	1
Hybrid Ring Generators for In-System Testing	1
Editorial	1
Efficient Design of Rounding-Based Approximate Multiplier Using Modified Karatsuba Algorithm	1
Verification and Validation with Prototype Chip Implemented with Layout Level Scan C-Elements	1
Enhanced Monte Carlo-Based Uncertainty Quantification in Electronic Circuits	1
Editorial	1
Analysing the Energy and Power Consumption Impact of Selective Forwarding Attacks on 6LoWPANs: A Detailed Evaluation of MRHOF and OF0 Objective Functions	1
2023 JETTA-TTTC Best Paper Award	1
PCB Defects: A Unified Survey of Trends, Detection Techniques, and Limitations through Systematic Literature Review	1
Design and Verification of a SAR ADC SystemVerilog Real Number Model	1
Analysis of the Lifecycles of Automotive Resistor Lead in Random Vibration	1
An Analytical Model for Deposited Charge of Single Event Transient (SET) in FinFET	1
Test Technology Newsletter	1
Structural and SCOAP Features Based Approach for Hardware Trojan Detection Using SHAP and Light Gradient Boosting Model	1
Sushil Doranga Joins JETTA Editorial Board	1
A Polynomial Transform Method for Hardware Systematic Error Identification and Correction in Semiconductor Multi-Site Testing	1
The Detection of Malicious Modifications in the FPGA	1
Small Delay Fault Testing with Multiple Voltages under Variations: Defect vs. Fault Coverage	1
Non-Invasive Hardware Trojans Modeling and Insertion: A Formal Verification Approach	1
A Review of Various Defects in PCB	1
Editorial	1
Test Technology Newsletter	1
Editorial	1
Threshold Analysis Using Probabilistic Xgboost Classifier for Hardware Trojan Detection	1