Journal of Electronic Testing-Theory and Applications

Article	Citations
LoBA: A Leading One Bit Based Imprecise Multiplier for Efficient Image Processing	21
Soft Error Hardened Asymmetric 10T SRAM Cell for Aerospace Applications	19
Spectrum Analyzer Based on a Dynamic Filter	13
Aging-Resilient SRAM-based True Random Number Generator for Lightweight Devices	12
Low-Cost Error Detection in Deep Neural Network Accelerators with Linear Algorithmic Checksums	10
Hardware Obfuscation for IP Protection of DSP Applications	9
SC-COTD: Hardware Trojan Detection Based on Sequential/Combinational Testability Features using Ensemble Classifier	8
Design and Optimization Methodology of Coplanar Waveguide Test Structures for Dielectric Characterization of Thin Films	7
A Review of Various Defects in PCB	7
An Efficient Algorithm for Optimizing the Test Path of Digital Microfluidic Biochips	7
Analysis of Security Vulnerability Levels of In-Vehicle Network Topologies Applying Graph Representations	7
Remaining Useful Life Prediction of Analog Circuit Using Improved Unscented Particle Filter	7
Review of Manufacturing Process Defects and Their Effects on Memristive Devices	7
Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults	7
Aging Prediction and Tolerance for the SRAM Memory Cell and Sense Amplifier	6
Resistance of the Montgomery Ladder Against Simple SCA: Theory and Practice	6
Traxtor: An Automatic Software Test Suit Generation Method Inspired by Imperialist Competitive Optimization Algorithms	6
Pre-Silicon Verification Using Multi-FPGA Platforms: A Review	6
Fault Diagnosis of Linear Analog Electronic Circuit Based on Natural Response Specification using K-NN Algorithm	6
Investigations on the Use of Ensemble Methods for Specification-Oriented Indirect Test of RF Circuits	6
Maximal Connectivity Test with Channel-Open Faults in On-Chip Communication Networks	5
Model Transferability from ImageNet to Lithography Hotspot Detection	5
Comprehensive Analysis and Optimization of Reliable Viterbi Decoder Circuits Implemented in Modular VLSI Design Logic Styles	5
Hardware Efficient Approximate Multiplier Architecture for Image Processing Applications	5
Fault Diagnosis Method of Low Noise Amplifier Based on Support Vector Machine and Hidden Markov Model	5

CMOS Implementation and Performance Analysis of Known Approximate 4:2 Compressors	4
Thermal-aware Test Data Compression for System-on-Chip Based on Modified Bitmask Based Methods	4
Reducing Aging Impacts in Digital Sensors via Run-Time Calibration	4
Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications	4
Retesting Defective Circuits to Allow Acceptable Faults for Yield Enhancement	4
Self Healing Controllers to Mitigate SEU in the Control Path of FPGA Based System: A Complete Intrinsic Evolutionary Approach	4
Design of Power Gated SRAM Cell for Reducing the NBTI Effect and Leakage Power Dissipation During the Hold Operation	4
A Systematic Bit Selection Method for Robust SRAM PUFs	4
Smell Detection Agent Optimization Approach to Path Generation in Automated Software Testing	4
Design and Evaluation of XOR Arbiter Physical Unclonable Function and its Implementation on FPGA in Hardware Security Applications	4
A Fault Verification Method Based on the Substitution Theorem and Voltage-Current Phase Relationship	4
Revisit to Histogram Method for ADC Linearity Test: Examination of Input Signal and Ratio of Input and Sampling Frequencies	4
Novel Fault-Tolerant Processing in Memory Cell in Ternary Quantum-Dot Cellular Automata	4
A Source-code Aware Method for Software Mutation Testing Using Artificial Bee Colony Algorithm	4
A Low Power-Consumption Triple-Node-Upset-Tolerant Latch Design	4
Hardware Trojan Free Netlist Identification: A Clustering Approach	4
An Efficient VLSI Test Data Compression Scheme for Circular Scan Architecture Based on Modified Ant Colony Meta-heuristic	4
Single Particle Fault Injection Signal Generation Method Using Gaussian Cloud Model	3
Analysis and Detection of Open-gate Defects in Redundant Structures of a FinFET SRAM Cell	3
Comparing the Impact of Power Supply Voltage on CMOS- and FinFET-Based SRAMs in the Presence of Resistive Defects	3
Error-Efficient Approximate Multiplier Design using Rounding Based Approach for Image Smoothing Application	3
Neural Network-based Online Fault Diagnosis in Wireless-NoC Systems	3
Co-Optimization of Test Wrapper Length and TSV for TSV Based 3D SOCs	3
Part I: Evaluation for Hardware Trojan Detection Based on Electromagnetic Radiation	3
AFIA: ATPG-Guided Fault Injection Attack on Secure Logic Locking	3
Tipping Point Analysis of Electrical Resistance Data with Early Warning Signals of Failure for Predictive Maintenance	3
Design of INV/BUFF Logic Locking For Enhancing the Hardware Security	2
A probability density estimation algorithm on multiwavelet for the high-resolution ADC	2
Testable Architecture Design for Programmable Cellular Automata on FPGA Using Run-Time Dynamically Reconfigurable Look-Up Tables	2
Evaluation of a Two-Tier Adaptive Indirect Test Flow for a Front-End RF Circuit	2
Diagnosis of Incipient Faults in Nonlinear Analog Circuits Based on High Order Moment Fractional Transform	2
Novel MEMS Piezoresistive Sensor with Hair-Pin Structure to Enhance Tensile and Compressive Sensitivity and Correct Non-Linearity	2
Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits using Pipeline Stage Parallelism	2
Multiple Retest Systems for Screening High-Quality Chips	2
Estimating Operational Age of an Integrated Circuit	2
On Reducing Test Data Volume for Circular Scan Architecture Using Modified Shuffled Shepherd Optimization	2
Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects	2
Identifying Resistive Open Defects in Embedded Cells under Variations	2
TRAP-GATE: A Probabilistic Approach to Enhance Hardware Trojan Detection and its Game Theoretic Analysis	2
Cross-PUF Attacks: Targeting FPGA Implementation of Arbiter-PUFs	2
A Bit-Error Rate Measurement and Error Analysis of Wireline Data Transmission using Current Source Model for Single Event Effect under Irradiation Environment	2
A New Neural Network Based on CNN for EMIS Identification	2
Parameterizable Real Number Models for Mixed-Signal Designs Using SystemVerilog	2
Investigation of the Impact of BTI Aging Phenomenon on Analog Amplifiers	2
Soft Computing Techniques Based CAD Approach for Power Supply Noise Reduction in System-on-Chip	2
A Novel Approach of Data Content Zeroization Under Memory Attacks	2
Soft Errors Sensitivity of SRAM Cells in Hold, Write, Read and Half-Selected Conditions	2
Deep Soft Error Propagation Modeling Using Graph Attention Network	2
Decoupling Capacitor Estimation and Allocation using Optimization Techniques for Power Supply Noise Reduction in System-on-Chip	1
Method of Implanting Hardware Trojan Based on EHW in Part of Circuit	1

An Accurate Estimation Algorithm for Failure Probability of Logic Circuits Using Correlation Separation	1
An Analytic Model for Predicting Single Event (SE) Crosstalk of Nanometer CMOS Circuits	1
Hardware Trojan Detection Method Based on Dual Discriminator Assisted Conditional Generation Adversarial Network	1
Comparison of the Output Parameters of the Memristor-based Op-amp Model and the Traditional Op-amp Model	1
Role of the Pulse Repetition Rate when Assessing Electromagnetic Immunity of Electronic Devices	1
Modular Test Kit – A Modular Approach for Efficient and Function-Oriented Testing	1
A Tunable Concurrent BIST Design Based on Reconfigurable LFSR	1
Synthesis of Reversible Circuits with Reduced Nearest-Neighbor Cost Using Kronecker Functional Decision Diagrams	1
A Low-cost BIST Design Supporting Offline and Online Tests	1
Design of an Integrated System for On-line Test and Diagnosis of Rotary Actuators	1
Measurement and Simulation of the Near Magnetic Field Radiated by Integrated Magnetic Inductors	1
Low Area FPGA Implementation of AES Architecture with EPRNG for IoT Application	1
Evaluation of Ionizing Radiation Effects on Device Modules Used in Wireless-Based Monitoring Systems	1
Applying Artificial Neural Networks to Logic Built-in Self-test: Improving Test Point Insertion	1
Efficient Designs of Reversible Majority Voters	1
Stress-Aware Periodic Test of Interconnects	1
A Polynomial Transform Method for Hardware Systematic Error Identification and Correction in Semiconductor Multi-Site Testing	1
A Methodology for Identification of Internal Nets for Improving Fault Coverage in Analog and Mixed Signal Circuits	1
Fault-Aware Dependability Enhancement Techniques for Phase Change Memory	1
Temperature and Humidity Controlled Test Bench for Temperature Sensor Characterization	1
Investigation of Single Event Effects in a Resistive RAM Memory Array by Coupling TCAD and SPICE Simulations	1
A Secure and Robust PUF-based Key Generation with Wiretap Polar Coset Codes	1
Detection and Diagnosis of Multi-Fault for through Silicon Vias in 3D IC	1
Single Event Upset Evaluation for a 28-nm FDSOI SRAM Type Buffer in an ARM Processor	1
Achieving Agility in Projects Through Hierarchical Divisive Clustering Algorithm	1
Area-Efficient and Reliable Error Correcting Code Circuit Based on Hybrid CMOS/Memristor Circuit	1
Impact of Worst-Case Excitation for DDR interface Signal and Power Integrity Co-Simulation	1
Low-Power Area-Efficient Fault Tolerant Adder in Current Mode Multi Valued Logic Using Berger Codes	1
Network-on-Chip and Photonic Network-on-Chip Basic Concepts: A Survey	1
Radiation Tolerant SRAM Cell Design in 65nm Technology	1
Efficient Design of Rounding-Based Approximate Multiplier Using Modified Karatsuba Algorithm	1
Design Development and Testing of High Performance Microwave Frequency Up-Converter	1
A New Approximate 4-2 Compressor using Merged Sum and Carry	1
Automated Design Error Debugging of Digital VLSI Circuits	1
Speed-Up in Test Methods Using Probabilistic Merit Indicators	1
A Complete Design-for-Test Scheme for Reconfigurable Scan Networks	1
Testing and Diagnosis of Digital Microfluidic Biochips using Multiple Droplets	1
DFS-KeyLevel: A Two-Layer Test Scenario Generation Approach for UML Activity Diagram	0
Research on the Reliability of Interconnected Solder Joints of Copper Pillars under Random Vibration	0
Time Complexity Comparison of Stopping at First Failure and Completely Running the Test	0
A Numeral System Based Framework for Improved One-Lambda Crosstalk Avoidance Code Using Recursive Symmetry Formula	0
Diagnosis of Analog and Digital Circuit Faults Using Exponential Deep Learning Neural Network	0
A Survey of PCB Defect Detection Algorithms	0
A Quadruple-Node Upsets Hardened Latch Design Based on Cross-Coupled Elements	0
A Test Generation Method of R-2R Digital-to-Analog Converters Based on Genetic Algorithm	0
Efficient Design of Rounding Based Static Segment Imprecise Multipliers for Error Tolerance Application	0
E3C Techniques for Protecting NAND Flash Memories	0
Test Technology Newsletter	0
Performances and Stability Analysis of a Novel 8T1R Non-Volatile SRAM (NVSRAM) versus Variability	0
An Investigation into the Failure Characteristics of External PCB Traces with Different Angle Bends	0
Detection Method of Hardware Trojan Based on Attention Mechanism and Residual-Dense-Block under the Markov Transition Field	0
Proton Beam Validation of a New Single Event Transient Mitigation Technique	0
Editorial	0
Multi-Objective Optimization Based Test Pattern Generation for Hardware Trojan Detection	0
Test Technology Newsletter	0
Formal Verification of ECCs for Memories Using ACL2	0
2020 JETTA Reviewers	0
Editorial	0
A CatBoost Based Approach to Detect Label Flipping Poisoning Attack in Hardware Trojan Detection Systems	0
Neuro-Fuzzy Evaluation of the Software Reliability Models by Adaptive Neuro Fuzzy Inference System	0
Test Technology Newsletter	0
Editorial	0
Library Characterization of Arithmetic Circuits for Reliability-Aware Designs in SRAM-Based FPGAs	0
The Newsletter of the Test Technology Technical Council of the IEEE Computer Society	0
Test Technology Newsletter	0
Diagnosis and Compensation of Control Program, Sensor and Actuator Failures in Nonlinear Systems Using Hierarchical State Space Checks	0
Test Technology Newsletter	0
Design and Verification of an Asynchronous NoC Router Architecture for GALS Systems	0
Failure Mechanism and Sampling Frequency Dependency on TID Response of SAR ADCs	0
Threshold Analysis Using Probabilistic Xgboost Classifier for Hardware Trojan Detection	0
Editorial	0
Test Technology Newsletter	0
Test Technology Newsletter	0
A Low Bit Instability CMOS PUF Based on Current Mirrors and WTA Cells	0
Test Technology Newsletter	0
Editorial	0
BISCC: A Novel Approach to Built In State Consistency Checking For Quick Volume Validation of Mixed-Signal/RF Systems	0
A Flexible Concurrent Testing Scheme for Non-Feedback and Feedback Bridging Faults in Integrated Circuits	0
Editorial	0
High Performance Approximate Memories for Image Processing Applications	0

Test Technology Newsletter	0
New Second-order Threshold Implementation of Sm4 Block Cipher	0
Editorial	0
A Low-Cost, Robust and Tolerant, Digital Scheme for Post-Bond Testing and Diagnosis of TSVs	0
Research on Analog Integrated Circuit Test Parameter Set Reduction Based on XGBoost	0
Experimental and Simulation Results of Wien Bridge Oscillator Circuıt Realized wıth Op-Amp Designed Using a Memristor	0
Trade-off Mechanism Between Reliability and Performance for Data-flow Soft Error Detection	0
2019 JETTA-TTTC Best Paper Award	0
Light Emission Tracking and Measurements for Analog Circuits Fault Diagnosis in Automotive Applications	0
Online Diagnosis and Self-Recovery of Faulty Cells in Daisy-Chained MEDA Biochips Using Functional Actuation Patterns	0
Effective Software Mutation-Test Using Program Instructions Classification	0
Influence of Printed Circuit Board Dynamics on the Fretting Wear of Electronic Connectors: A Dynamic Analysis Approach	0
Test Technology Newsletter	0
A Weighted-Bin Difference Method for Issue Site Identification in Analog and Mixed-Signal Multi-Site Testing	0
Low Overhead and High Stability Radiation-Hardened Latch for Double/Triple Node Upsets	0
Test Technology Newsletter	0
Automated Bug Resistant Test Intent with Register Header Database for Optimized Verification	0
Incomplete Testing of SOC	0
FAMCroNA: Fault Analysis in Memristive Crossbars for Neuromorphic Applications	0
Editorial	0
High Resolution Pulse Propagation Driven Trojan Detection in Digital Systems	0
Refined Self-calibration of an Inductorless Low-noise Amplifier with Non-intrusive Circuit	0
2020 JETTA-TTTC Best Paper Award	0
Editorial	0
Editorial	0
Stuck-At Fault Mitigation of Emerging Technologies Based Switching Lattices	0
2021 JETTA-TTTC Best Paper Award	0
Editorial	0
New Editors – 2022	0
2021 Reviewers	0
Journal of Electronic Testing: Theory and Applications New Editors – 2023	0
MATLAB-Open Source Tool Based Framework for Test Generation for Digital Circuits Using Evolutionary Algorithms	0
Fault Tolerant Lanczos Eigensolver via an Invariant Checking Method	0
Efficient Test and Characterization of Space Transmit-Receive Modules Using Scalable and Multipurpose Automated Test System	0
Editorial	0
Test Technology Newsletter	0
Editorial	0
Development of a Simplified Programming Kit Based 16LF18856 for Embedded Systems Testing and Education in Developing Countries	0
Editorial	0
Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits	0
Identification of Logic Paths Influenced by Severe Coupling Capacitances	0
Test Technology Newsletter	0
HVoC: a Hybrid Model Checking - Interactive Theorem Proving Approach for Functional Verification of Digital Circuits	0
Editorial	0
Evaluating the Reliability of Different Voting Schemes for Fault Tolerant Approximate Systems	0
Performance Efficient and Fault Tolerant Approximate Adder	0
Analysis of the Lifecycles of Automotive Resistor Lead in Random Vibration	0
Fault Detection and Diagnosis of DMFB Using Concurrent Electrodes Actuation	0
Editorial	0
General Fault and Soft-Error Tolerant Phase-Locked Loop by Enhanced TMR using A Synchronization-before-Voting Scheme	0
Tolerating Soft Errors with Horizontal-Vertical-Diagonal-N-Queen (HVDNQ) Parity	0
Failure Probability due to Radiation-Induced Effects in FinFET SRAM Cells under Process Variations	0
2022 Reviewers	0
Efficient Fault Detection by Test Case Prioritization via Test Case Selection	0
New Method for Determining and Predicting Test Interconnect Pin Current Carrying Capacity	0
Reducing Library Characterization Time for Cell-aware Test while Maintaining Test Quality	0
Test Technology Newsletter	0
Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift	0
Editorial	0
Editorial	0
Using both Stable and Unstable SRAM Bits for the Physical Unclonable Function	0
Test Technology Newsletter	0
Identification of Unknown Electromagnetic Interference Sources Based on Siamese-CNN	0
Research on the Mechanical Properties of Magnetorheological Damping and the Performance of Microprobe Test Process	0
A Framework for Configurable Joint-Scan Design-for-Test Architecture	0
Test Technology Newsletter	0
Cost-Effective Path Delay Defect Testing Using Voltage/Temperature Analysis Based on Pattern Permutation	0
Editorial	0
Test Technology Newsletter	0
A Cascaded Multicasting Architecture for Test Data Compression	0
Structural and SCOAP Features Based Approach for Hardware Trojan Detection Using SHAP and Light Gradient Boosting Model	0
Test Technology Newsletter	0
Editorial	0
Intrinsic Based Self-healing Adder Design Using Chromosome Reconstruction Algorithm	0
Test Technology Newsletter	0
On-Line Test of Pin-Constrained Digital Microfluidic Biochips with Connect-5 Structure	0
2022 JETTA-TTTC Best Paper Award	0
TTTC Newsletter	0
Editorial	0
A Novel Metaheuristic Based Method for Software Mutation Test Using the Discretized and Modified Forrest Optimization Algorithm	0
Effect of Sizing and Scaling on Power Dissipation and Resilience of an RHBD SRAM Circuit	0
The Detection of Malicious Modifications in the FPGA	0
On the Use of the Indirect Test Strategy for Lifetime Performance Monitoring of RF Circuits	0