OOIR: Observatory of International Research

Papers

(The median citation count of Journal of Electronic Testing-Theory and Applications is 1. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-08-01 to 2026-08-01.)

Article	Citations
Using both Stable and Unstable SRAM Bits for the Physical Unclonable Function	54
Achieving Agility in Projects Through Hierarchical Divisive Clustering Algorithm	22
Analysis of Combinational Circuit Failure Rate based on Graph Partitioning and Probabilistic Binomial Approach	19
Comparison of Single Event Effect and Space Electrostatic Discharge Effect on FPGA Signal Transmission	18
Read & Write Stability of CNTFET 6T SRAM Cell: A Comprehensive Analysis	16
On the Use of the Indirect Test Strategy for Lifetime Performance Monitoring of RF Circuits	16
Artificial Neural Network Based Prediction Model for IR Drop Measurement in a VLSI Power Delivery Network	12
Design and Simulation of a Dependable Architecture Using Triple Modular Redundancy for Embedded Cyber-Physical Systems	11
Design and Verification of an Asynchronous NoC Router Architecture for GALS Systems	11
Smell Detection Agent Optimization Approach to Path Generation in Automated Software Testing	10
Wafer-level Adaptive Testing Based on Dual-Predictor Collaborative Decision	10
Diagnosis of Analog and Digital Circuit Faults Using Exponential Deep Learning Neural Network	9
Logic Locking Based Configurable Obfuscation Cell for Enhanced IC Security	9
Investigation of Single Event Effects in a Resistive RAM Memory Array by Coupling TCAD and SPICE Simulations	8
Inherent Hardware Identifiers: Advancing IC Traceability and Provenance in the Multi-Die Era	8
A Program-Output Estimator for Software Testing Using Program Analysis and Deep Learning Algorithms	8
A Feature-Adaptive and Scalable Hardware Trojan Detection Framework For Third-party IPs Utilizing Multilevel Feature Analysis and Random Forest	8
The Newsletter of the Test Technology Technical Council of the IEEE Computer Society	7
Performance Efficient and Fault Tolerant Approximate Adder	7
Enhanced Moth Flame Optimization Algorithm Entropy-Based Centroid SVM-Based Software Defect Prediction	7
Test Case Optimization using Machine Learning based Hybrid Meta-Heuristic Approach	7
A New Approximate 4-2 Compressor using Merged Sum and Carry	7
Hardware Trojan Detection Method Based on Dual Discriminator Assisted Conditional Generation Adversarial Network	6
Network-on-Chip and Photonic Network-on-Chip Basic Concepts: A Survey	6
Editorial	6

An End-to-End Mutually Exclusive Autoencoder Method for Analog Circuit Fault Diagnosis	6
Cost-Effective Path Delay Defect Testing Using Voltage/Temperature Analysis Based on Pattern Permutation	6
A Flexible Concurrent Testing Scheme for Non-Feedback and Feedback Bridging Faults in Integrated Circuits	6
Editorial	6
SFFHO: Development of Statistical Fitness-based Fire Hawk Optimizer for Software Testing and Maintenance Approach using Adaptive Deep Learning Method	6
Influence of Printed Circuit Board Dynamics on the Fretting Wear of Electronic Connectors: A Dynamic Analysis Approach	5
2021 JETTA-TTTC Best Paper Award	5
A Multi-Objective Test Scenario Prioritization Method Based on UML Activity Diagram	5
Development of a Simplified Programming Kit Based 16LF18856 for Embedded Systems Testing and Education in Developing Countries	5
GHOST: Graph-based Hardware Ownership Security through Traceability	5
Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift	5
Advancing Low Power BIST Architecture with GAN-Driven Test Pattern Optimization	5
Firmware-Driven Adaptive Clock Tuning for Electromagnetic Interference Tolerance in Automotive Systems	5
Fault Modeling and Countermeasures for DRAM–Targeted Electromagnetic Fault Injection	5
Self Healing Controllers to Mitigate SEU in the Control Path of FPGA Based System: A Complete Intrinsic Evolutionary Approach	5
Editorial	5
2022 Reviewers	4
Real-time Embedded System Fault Injector Framework for Micro-architectural State Based Reliability Assessment	4
Test Technology Newsletter	4
A Method of Redundant Feature Suppression in Circuit Output Positions for Analog Circuit Soft and Hard Fault Diagnosis	4
A Quadruple-Node Upsets Hardened Latch Design Based on Cross-Coupled Elements	4
An Investigation into the Failure Characteristics of External PCB Traces with Different Angle Bends	4
PrecIRisc: A High-Precision and Low-Bloat Dynamic Binary Instrumentation Tailored for RISC Architectures	4
Instant Test and Repair for TSVs using Differential Signaling	4
Interleaved Counter Matrix Code in SRAM Memories for Continuous Adjacent Multiple Bit Upset Correction	4
Chebyshev-based Algorithm: Achieving Fast ADC Static Parameter Testing Using a Low-precision Signal Source	4
Fault Diagnosis of Analog Circuits Using an Improved BiTCN Combined with BiLSTM	4
Syntactic and Semantic Analysis of Temporal Assertions to Support the Approximation of RTL Designs	4
Beyond Power Side Channels: Impedance as a Cryptographic Threat	3
A Tunable Concurrent BIST Design Based on Reconfigurable LFSR	3
A Design for Single Event Transient Pulse Width Measurement in CMOS Technology	3
Efficient Test and Characterization of Space Transmit-Receive Modules Using Scalable and Multipurpose Automated Test System	3
Multi-modal Pre-silicon Evaluation of Hardware Masking Styles	3
Modular Test Kit – A Modular Approach for Efficient and Function-Oriented Testing	3
Automated Design Error Debugging of Digital VLSI Circuits	3
Investigation of Silicon Aging Effects in Dopingless PUF for Reliable Security Solution	3
ATPG Optimization for Bridging Faults in Incomplete Testing of SoCs	3
Design of INV/BUFF Logic Locking For Enhancing the Hardware Security	3
Equivalent Circuit and Damage Threshold Study of Communication Interfaces under HEMP	3
Towards the Detection of Hardware Trojans with Cost Effective Test Vectors using Genetic Algorithm	3
New Second-order Threshold Implementation of Sm4 Block Cipher	3
Dynamic Smartcard Protection and SSELUR-GRU-Based Attack Stage Identification in Industrial IoT	3
Formal Verification of Universal Numbers using Theorem Proving	3
2023 JETTA-TTTC Best Paper Award	2
Robust Adaptive DLBIST for Delay Fault Testing: Minimizing PVT Variability with Zero Temperature Coefficient (ZTC) Voltage	2
A Defect Detection Method of Mixed Wafer Map Using Neighborhood Path Filtering Clustering Algorithm	2
Editorial	2
Comparative Design and Analysis of RHBD SRAM Cells for Space Applications	2
Average Relative SNR: New Metric to Evaluate the Attack Performance of Non-Profiled Side-Channel Traces	2
On the Harmonic Locking of Ring Oscillators under Single ElectroMagnetic Pulsed Fault Injection in FPGAs	2

PCB Defects: A Unified Survey of Trends, Detection Techniques, and Limitations through Systematic Literature Review	2
SRAM PUF Preselection Method Based on Neighboring Spatial Majority Voting	2
Hybrid Ring Generators for In-System Testing	2
Fault Detection and Diagnosis of DMFB Using Concurrent Electrodes Actuation	2
2023 JETTA Reviewers	2
Incomplete Testing of SOC	2
Structural and SCOAP Features Based Approach for Hardware Trojan Detection Using SHAP and Light Gradient Boosting Model	2
Non-Invasive Hardware Trojans Modeling and Insertion: A Formal Verification Approach	2
A Review of Various Defects in PCB	2
Online Diagnosis and Self-Recovery of Faulty Cells in Daisy-Chained MEDA Biochips Using Functional Actuation Patterns	2
An Analytical Model for Deposited Charge of Single Event Transient (SET) in FinFET	2
SAF-YOLO: a Semantic-Aware Lightweight Framework for Fine-Grained PCB Defect Detection	2
A Low Bit Instability CMOS PUF Based on Current Mirrors and WTA Cells	2
Design and Verification of a SAR ADC SystemVerilog Real Number Model	2
Analysis of the Lifecycles of Automotive Resistor Lead in Random Vibration	2
Editorial	2
A High-Performance Quadruple-Node-Upset-Tolerant Latch Design and an Algorithm for Tolerance Verification of Hardened Latches	2
Cross-Domain Multi-Label Prediction of Metamorphic Relation Patterns Leveraging Multimodal Features	1
Efficient Fault Detection by Test Case Prioritization via Test Case Selection	1
BISCC: A Novel Approach to Built In State Consistency Checking For Quick Volume Validation of Mixed-Signal/RF Systems	1
A Survey and Recent Advances: Machine Intelligence in Electronic Testing	1
Custom-Adaptive Kernel Strategies for Gaussian Process Regression in Wafer-Level Modeling and FPGA Delay Analysis	1
Error Resilient Transformers: A Novel Soft Error Vulnerability Guided Approach to Error Checking and Suppression	1
Editorial	1
Exploring Differential Evolution Algorithms in Search of Best Test Vector for Digital Circuit Testing	1
Efficient Design of Rounding-Based Approximate Multiplier Using Modified Karatsuba Algorithm	1
Verification and Validation with Prototype Chip Implemented with Layout Level Scan C-Elements	1
A Weighted-Bin Difference Method for Issue Site Identification in Analog and Mixed-Signal Multi-Site Testing	1
Reactant and Waste Minimization during Sample Preparation on Micro-Electrode-Dot-Array Digital Microfluidic Biochips using Splitting Trees	1
SD2CI: A Structure-driven Approach for Detecting Silent Data Corruption Instructions	1
Test Technology Newsletter	1
A Dynamic-Centroid-Guided Method for Efficient Multi-Parameter Trimming of Integrated Chips	1
HT-Pred: An Extensive Methodology for Dataset Preparation and Hardware Trojan Prediction using Gate-Level Netlist	1
Editorial	1
An Efficient Cybersecurity Method to Detect Phishing Attacks Integrating Heuristic-Driven Feature Optimizer and Deep Learning Algorithms	1
Enhanced Monte Carlo-Based Uncertainty Quantification in Electronic Circuits	1
ResNeSt Wafer Map Defect Pattern Recognition Based on the Multi-attention Mechanism and Enhanced Activation Function	1
Threshold Analysis Using Probabilistic Xgboost Classifier for Hardware Trojan Detection	1
Editorial	1
Variability and Analog Parameter Characterization in Enclosed Layout Transistors	1
Analysing the Energy and Power Consumption Impact of Selective Forwarding Attacks on 6LoWPANs: A Detailed Evaluation of MRHOF and OF0 Objective Functions	1
A Polynomial Transform Method for Hardware Systematic Error Identification and Correction in Semiconductor Multi-Site Testing	1
Investigating and Improving the Performance of Radiation-Hardened SRAM Cell with the Use of Multi-Voltage Transistors	1
Small Delay Fault Testing with Multiple Voltages under Variations: Defect vs. Fault Coverage	1
Sushil Doranga Joins JETTA Editorial Board	1
Correction: Enhancing Digital VLSI Circuit Debugging with Unified Neighbor aware Graph Neural Network Based Automated Error Detection	1