Journal of Electronic Testing-Theory and Applications

Article	Citations
Spectrum Analyzer Based on a Dynamic Filter	14
Review of Manufacturing Process Defects and Their Effects on Memristive Devices	14
Low-Cost Error Detection in Deep Neural Network Accelerators with Linear Algorithmic Checksums	13
SC-COTD: Hardware Trojan Detection Based on Sequential/Combinational Testability Features using Ensemble Classifier	13
A Review of Various Defects in PCB	12
Traxtor: An Automatic Software Test Suit Generation Method Inspired by Imperialist Competitive Optimization Algorithms	12
Pre-Silicon Verification Using Multi-FPGA Platforms: A Review	10
Design and Evaluation of XOR Arbiter Physical Unclonable Function and its Implementation on FPGA in Hardware Security Applications	10
A Source-code Aware Method for Software Mutation Testing Using Artificial Bee Colony Algorithm	10
Resistance of the Montgomery Ladder Against Simple SCA: Theory and Practice	9
Analysis of Security Vulnerability Levels of In-Vehicle Network Topologies Applying Graph Representations	9
Hardware Obfuscation for IP Protection of DSP Applications	9
Novel Fault-Tolerant Processing in Memory Cell in Ternary Quantum-Dot Cellular Automata	7
Model Transferability from ImageNet to Lithography Hotspot Detection	7
Fault Diagnosis Method of Low Noise Amplifier Based on Support Vector Machine and Hidden Markov Model	7
Hardware Efficient Approximate Multiplier Architecture for Image Processing Applications	7
Fault Diagnosis of Linear Analog Electronic Circuit Based on Natural Response Specification using K-NN Algorithm	7
A Systematic Bit Selection Method for Robust SRAM PUFs	7
Aging Prediction and Tolerance for the SRAM Memory Cell and Sense Amplifier	6
Hardware Trojan Free Netlist Identification: A Clustering Approach	6
Retesting Defective Circuits to Allow Acceptable Faults for Yield Enhancement	5
Revisit to Histogram Method for ADC Linearity Test: Examination of Input Signal and Ratio of Input and Sampling Frequencies	5
Identifying Resistive Open Defects in Embedded Cells under Variations	5
A Low Power-Consumption Triple-Node-Upset-Tolerant Latch Design	5
Cross-PUF Attacks: Targeting FPGA Implementation of Arbiter-PUFs	5

A Novel Metaheuristic Based Method for Software Mutation Test Using the Discretized and Modified Forrest Optimization Algorithm	5
AFIA: ATPG-Guided Fault Injection Attack on Secure Logic Locking	4
Parameterizable Real Number Models for Mixed-Signal Designs Using SystemVerilog	4
Research on the Reliability of Interconnected Solder Joints of Copper Pillars under Random Vibration	4
Reducing Aging Impacts in Digital Sensors via Run-Time Calibration	4
Automated Design Error Debugging of Digital VLSI Circuits	4
Self Healing Controllers to Mitigate SEU in the Control Path of FPGA Based System: A Complete Intrinsic Evolutionary Approach	4
Design of Power Gated SRAM Cell for Reducing the NBTI Effect and Leakage Power Dissipation During the Hold Operation	4
Light Emission Tracking and Measurements for Analog Circuits Fault Diagnosis in Automotive Applications	4
Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications	4
Error-Efficient Approximate Multiplier Design using Rounding Based Approach for Image Smoothing Application	4
CMOS Implementation and Performance Analysis of Known Approximate 4:2 Compressors	4
Stress-Aware Periodic Test of Interconnects	4
Efficient Design of Rounding-Based Approximate Multiplier Using Modified Karatsuba Algorithm	4
Smell Detection Agent Optimization Approach to Path Generation in Automated Software Testing	4
A CatBoost Based Approach to Detect Label Flipping Poisoning Attack in Hardware Trojan Detection Systems	3
Design of INV/BUFF Logic Locking For Enhancing the Hardware Security	3
An Accurate Estimation Algorithm for Failure Probability of Logic Circuits Using Correlation Separation	3
Evaluation of a Two-Tier Adaptive Indirect Test Flow for a Front-End RF Circuit	3
Neural Network-based Online Fault Diagnosis in Wireless-NoC Systems	3
Influence of Printed Circuit Board Dynamics on the Fretting Wear of Electronic Connectors: A Dynamic Analysis Approach	3
Investigation of the Impact of BTI Aging Phenomenon on Analog Amplifiers	3
A Survey of PCB Defect Detection Algorithms	3
Analysis and Detection of Open-gate Defects in Redundant Structures of a FinFET SRAM Cell	3
Multiple Retest Systems for Screening High-Quality Chips	3
Hardware Trojan Detection Method Based on Dual Discriminator Assisted Conditional Generation Adversarial Network	3
Single Particle Fault Injection Signal Generation Method Using Gaussian Cloud Model	3
Deep Soft Error Propagation Modeling Using Graph Attention Network	2
A Bit-Error Rate Measurement and Error Analysis of Wireline Data Transmission using Current Source Model for Single Event Effect under Irradiation Environment	2
A New Neural Network Based on CNN for EMIS Identification	2
Comparison of the Output Parameters of the Memristor-based Op-amp Model and the Traditional Op-amp Model	2
A New Approximate 4-2 Compressor using Merged Sum and Carry	2
Achieving Agility in Projects Through Hierarchical Divisive Clustering Algorithm	2
Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits using Pipeline Stage Parallelism	2
Estimating Operational Age of an Integrated Circuit	2
Network-on-Chip and Photonic Network-on-Chip Basic Concepts: A Survey	2
On Reducing Test Data Volume for Circular Scan Architecture Using Modified Shuffled Shepherd Optimization	2
Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects	2
Soft Errors Sensitivity of SRAM Cells in Hold, Write, Read and Half-Selected Conditions	2
Method of Implanting Hardware Trojan Based on EHW in Part of Circuit	2
Low Area FPGA Implementation of AES Architecture with EPRNG for IoT Application	2
Applying Artificial Neural Networks to Logic Built-in Self-test: Improving Test Point Insertion	2
Effect of Sizing and Scaling on Power Dissipation and Resilience of an RHBD SRAM Circuit	2
Investigation of Single Event Effects in a Resistive RAM Memory Array by Coupling TCAD and SPICE Simulations	2
Fault-Aware Dependability Enhancement Techniques for Phase Change Memory	2
The Detection of Malicious Modifications in the FPGA	1
Performance Efficient and Fault Tolerant Approximate Adder	1
Temperature and Humidity Controlled Test Bench for Temperature Sensor Characterization	1
Design and Verification of an Asynchronous NoC Router Architecture for GALS Systems	1
Non-Invasive Hardware Trojans Modeling and Insertion: A Formal Verification Approach	1

A Low-cost BIST Design Supporting Offline and Online Tests	1
Simulation-based Analysis of RPL Routing Attacks and Their Impact on IoT Network Performance	1
FAMCroNA: Fault Analysis in Memristive Crossbars for Neuromorphic Applications	1
Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift	1
Decoupling Capacitor Estimation and Allocation using Optimization Techniques for Power Supply Noise Reduction in System-on-Chip	1
Cost-Effective Path Delay Defect Testing Using Voltage/Temperature Analysis Based on Pattern Permutation	1
Radiation Tolerant SRAM Cell Design in 65nm Technology	1
Modular Test Kit – A Modular Approach for Efficient and Function-Oriented Testing	1
Reducing Library Characterization Time for Cell-aware Test while Maintaining Test Quality	1
A Methodology for Identification of Internal Nets for Improving Fault Coverage in Analog and Mixed Signal Circuits	1
Structural and SCOAP Features Based Approach for Hardware Trojan Detection Using SHAP and Light Gradient Boosting Model	1
A Secure and Robust PUF-based Key Generation with Wiretap Polar Coset Codes	1
Detection and Diagnosis of Multi-Fault for through Silicon Vias in 3D IC	1
Detection Method of Hardware Trojan Based on Attention Mechanism and Residual-Dense-Block under the Markov Transition Field	1
Measurement and Simulation of the Near Magnetic Field Radiated by Integrated Magnetic Inductors	1
A Complete Design-for-Test Scheme for Reconfigurable Scan Networks	1
Single Event Upset Evaluation for a 28-nm FDSOI SRAM Type Buffer in an ARM Processor	1
Efficient Designs of Reversible Majority Voters	1
Identification of Unknown Electromagnetic Interference Sources Based on Siamese-CNN	1
Neuro-Fuzzy Evaluation of the Software Reliability Models by Adaptive Neuro Fuzzy Inference System	1
Experimental and Simulation Results of Wien Bridge Oscillator Circuıt Realized wıth Op-Amp Designed Using a Memristor	1
Radiation Hardened by Design-based Voltage Controlled Oscillator for Low Power Phase Locked Loop Application	1
Performances and Stability Analysis of a Novel 8T1R Non-Volatile SRAM (NVSRAM) versus Variability	1
A Tunable Concurrent BIST Design Based on Reconfigurable LFSR	1
Synthesis of Reversible Circuits with Reduced Nearest-Neighbor Cost Using Kronecker Functional Decision Diagrams	1
A DfT Strategy for Guaranteeing ReRAM’s Quality after Manufacturing	1
Testing and Diagnosis of Digital Microfluidic Biochips using Multiple Droplets	1
Diagnosis and Compensation of Control Program, Sensor and Actuator Failures in Nonlinear Systems Using Hierarchical State Space Checks	1
Effective Software Mutation-Test Using Program Instructions Classification	1
An Analytical Model for Deposited Charge of Single Event Transient (SET) in FinFET	1
Intrinsic Based Self-healing Adder Design Using Chromosome Reconstruction Algorithm	1
A Polynomial Transform Method for Hardware Systematic Error Identification and Correction in Semiconductor Multi-Site Testing	1
Low Overhead and High Stability Radiation-Hardened Latch for Double/Triple Node Upsets	0
PCB Defect Recognition by Image Analysis using Deep Convolutional Neural Network	0
Proton Beam Validation of a New Single Event Transient Mitigation Technique	0
Analysis of the Lifecycles of Automotive Resistor Lead in Random Vibration	0
Test Technology Newsletter	0
Test Technology Newsletter	0
2022 JETTA-TTTC Best Paper Award	0
New Editors – 2022	0
Reactant and Waste Minimization during Sample Preparation on Micro-Electrode-Dot-Array Digital Microfluidic Biochips using Splitting Trees	0
Syntactic and Semantic Analysis of Temporal Assertions to Support the Approximation of RTL Designs	0
Formal Verification of a Dependable State Machine-Based Hardware Architecture for Safety-Critical Cyber-Physical Systems: Analysis, Design, and Implementation	0
Incomplete Testing of SOC	0
2021 JETTA-TTTC Best Paper Award	0
Editorial	0
Editorial	0
Failure Mechanism and Sampling Frequency Dependency on TID Response of SAR ADCs	0
Towards the Detection of Hardware Trojans with Cost Effective Test Vectors using Genetic Algorithm	0
The Newsletter of the Test Technology Technical Council of the IEEE Computer Society	0
Using both Stable and Unstable SRAM Bits for the Physical Unclonable Function	0
Pebble Traversal-Based Fault Detection and Advanced Reconfiguration Technique for Digital Microfluidic Biochips	0
2021 Reviewers	0
Editorial	0
Editorial	0
Editorial	0
Wafer-level Adaptive Testing Based on Dual-Predictor Collaborative Decision	0
Efficient Test and Characterization of Space Transmit-Receive Modules Using Scalable and Multipurpose Automated Test System	0
Test Technology Newsletter	0
Journal of Electronic Testing: Theory and Applications New Editors – 2023	0
HVoC: a Hybrid Model Checking - Interactive Theorem Proving Approach for Functional Verification of Digital Circuits	0
Verification and Validation with Prototype Chip Implemented with Layout Level Scan C-Elements	0
TTTC Newsletter	0
Editorial	0
Identification of Logic Paths Influenced by Severe Coupling Capacitances	0
Editorial	0
Editorial	0
Test Technology Newsletter	0
E3C Techniques for Protecting NAND Flash Memories	0
A Flexible Concurrent Testing Scheme for Non-Feedback and Feedback Bridging Faults in Integrated Circuits	0
Diagnosis of Analog and Digital Circuit Faults Using Exponential Deep Learning Neural Network	0
Formal Verification of Universal Numbers using Theorem Proving	0
An Investigation into the Failure Characteristics of External PCB Traces with Different Angle Bends	0
Predicting Energy Dissipation in QCA-Based Layered-T Gates Under Cell Defects and Polarisation: A Study with Machine-Learning Models	0
Research on the Mechanical Properties of Magnetorheological Damping and the Performance of Microprobe Test Process	0
A Test Generation Method of R-2R Digital-to-Analog Converters Based on Genetic Algorithm	0
A Weighted-Bin Difference Method for Issue Site Identification in Analog and Mixed-Signal Multi-Site Testing	0
Reliability Analysis for a GaAs LNA with Temperature Stress	0
Editorial	0
Investigating and Reducing the Architectural Impact of Transient Faults in Special Function Units for GPUs	0

Editorial	0
2020 JETTA-TTTC Best Paper Award	0
MATLAB-Open Source Tool Based Framework for Test Generation for Digital Circuits Using Evolutionary Algorithms	0
Editorial	0
Test Technology Newsletter	0
2023 JETTA Reviewers	0
Instant Test and Repair for TSVs using Differential Signaling	0
ADC Dynamic Parameter Testing Scheme Under Relaxed Conditions	0
Test Technology Newsletter	0
Test Technology Newsletter	0
Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits	0
An End-to-End Mutually Exclusive Autoencoder Method for Analog Circuit Fault Diagnosis	0
Fault Tolerant Lanczos Eigensolver via an Invariant Checking Method	0
Test Technology Newsletter	0
Editorial	0
Editorial	0
Investigating and Improving the Performance of Radiation-Hardened SRAM Cell with the Use of Multi-Voltage Transistors	0
A Novel Two-Stage Model Based SCA against secAES	0
A Numeral System Based Framework for Improved One-Lambda Crosstalk Avoidance Code Using Recursive Symmetry Formula	0
Phase Noise Analysis Performance Improvement, Testing and Stabilization of Microwave Frequency Source	0
Editorial	0
Development of a Simplified Programming Kit Based 16LF18856 for Embedded Systems Testing and Education in Developing Countries	0
Editorial	0
Failure Probability due to Radiation-Induced Effects in FinFET SRAM Cells under Process Variations	0
A Defect Detection Method of Mixed Wafer Map Using Neighborhood Path Filtering Clustering Algorithm	0
Online Diagnosis and Self-Recovery of Faulty Cells in Daisy-Chained MEDA Biochips Using Functional Actuation Patterns	0
Test Technology Newsletter	0
Efficient Design of Rounding Based Static Segment Imprecise Multipliers for Error Tolerance Application	0
BISCC: A Novel Approach to Built In State Consistency Checking For Quick Volume Validation of Mixed-Signal/RF Systems	0
A Framework for Configurable Joint-Scan Design-for-Test Architecture	0
New Second-order Threshold Implementation of Sm4 Block Cipher	0
Fault Detection and Diagnosis of DMFB Using Concurrent Electrodes Actuation	0
Design and Verification of a SAR ADC SystemVerilog Real Number Model	0
Test Technology Newsletter	0
2020 JETTA Reviewers	0
Tolerating Soft Errors with Horizontal-Vertical-Diagonal-N-Queen (HVDNQ) Parity	0
Refined Self-calibration of an Inductorless Low-noise Amplifier with Non-intrusive Circuit	0
High-Dimensional Feature Fault Diagnosis Method Based on HEFS-LGBM	0
Test Technology Newsletter	0
2019 JETTA-TTTC Best Paper Award	0
A Quadruple-Node Upsets Hardened Latch Design Based on Cross-Coupled Elements	0
Efficient Fault Detection by Test Case Prioritization via Test Case Selection	0
Equivalent Circuit and Damage Threshold Study of Communication Interfaces under HEMP	0
A Survey and Recent Advances: Machine Intelligence in Electronic Testing	0
General Fault and Soft-Error Tolerant Phase-Locked Loop by Enhanced TMR using A Synchronization-before-Voting Scheme	0
Test Technology Newsletter	0
Sahand: A Software Fault-Prediction Method Using Autoencoder Neural Network and K-Means Algorithm	0
An Automatic Software Testing Method to Discover Hard-to-Detect Faults Using Hybrid Olympiad Optimization Algorithm	0
Multi-Objective Optimization Based Test Pattern Generation for Hardware Trojan Detection	0
Library Characterization of Arithmetic Circuits for Reliability-Aware Designs in SRAM-Based FPGAs	0
Editorial	0
Efficient Selective Image Fusion: A PCB Diagnosis Approach and Implementation	0
Trade-off Mechanism Between Reliability and Performance for Data-flow Soft Error Detection	0
On the Use of the Indirect Test Strategy for Lifetime Performance Monitoring of RF Circuits	0
Editorial	0
On-Line Test of Pin-Constrained Digital Microfluidic Biochips with Connect-5 Structure	0
Investigation of Silicon Aging Effects in Dopingless PUF for Reliable Security Solution	0
Editorial	0
A High-Performance Quadruple-Node-Upset-Tolerant Latch Design and an Algorithm for Tolerance Verification of Hardened Latches	0
A Cascaded Multicasting Architecture for Test Data Compression	0
Test Technology Newsletter	0
Generating Synthetic Layout Test Patterns using Deep Learning	0
A Low Bit Instability CMOS PUF Based on Current Mirrors and WTA Cells	0
A Low-Cost, Robust and Tolerant, Digital Scheme for Post-Bond Testing and Diagnosis of TSVs	0
Test Technology Newsletter	0
Editorial	0
Dynamic Smartcard Protection and SSELUR-GRU-Based Attack Stage Identification in Industrial IoT	0
Editorial	0
High Resolution Pulse Propagation Driven Trojan Detection in Digital Systems	0
Threshold Analysis Using Probabilistic Xgboost Classifier for Hardware Trojan Detection	0
Interleaved Counter Matrix Code in SRAM Memories for Continuous Adjacent Multiple Bit Upset Correction	0
Editorial	0
Editorial	0
DFS-KeyLevel: A Two-Layer Test Scenario Generation Approach for UML Activity Diagram	0
Comparison of Single Event Effect and Space Electrostatic Discharge Effect on FPGA Signal Transmission	0
Evaluating the Reliability of Different Voting Schemes for Fault Tolerant Approximate Systems	0
A Novel Framework For Optimal Test Case Generation and Prioritization Using Ent-LSOA And IMTRNN Techniques	0
Analysis of Combinational Circuit Failure Rate based on Graph Partitioning and Probabilistic Binomial Approach	0
Test Modules for Enhanced Testability of Single Flux Quantum Integrated Circuits	0
Research on Analog Integrated Circuit Test Parameter Set Reduction Based on XGBoost	0
Test Technology Newsletter	0
2022 Reviewers	0