IEEE Transactions on Semiconductor Manufacturing

Papers
(The H4-Index of IEEE Transactions on Semiconductor Manufacturing is 18. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-03-01 to 2024-03-01.)
ArticleCitations
A Deep Convolutional Neural Network for Wafer Defect Identification on an Imbalanced Dataset in Semiconductor Manufacturing Processes107
Deformable Convolutional Networks for Efficient Mixed-Type Wafer Defect Pattern Recognition81
A Light-Weight Neural Network for Wafer Map Classification Based on Data Augmentation52
Deep Learning-Based Domain Adaptation Method for Fault Diagnosis in Semiconductor Manufacturing46
Active Learning of Convolutional Neural Network for Cost-Effective Wafer Map Pattern Classification36
Self-Supervised Representation Learning for Wafer Bin Map Defect Pattern Classification34
Semi-Supervised Multi-Label Learning for Classification of Wafer Bin Maps With Mixed-Type Defect Patterns33
SMT2020—A Semiconductor Manufacturing Testbed31
Memory-Augmented Convolutional Neural Networks With Triplet Loss for Imbalanced Wafer Defect Pattern Classification28
Machine Learning-Based Detection Method for Wafer Test Induced Defects27
Model-Free Adaptive Iterative Learning Control Method for the Czochralski Silicon Monocrystalline Batch Process27
Data-Driven Framework for Tool Health Monitoring and Maintenance Strategy for Smart Manufacturing26
Variational Deep Clustering of Wafer Map Patterns26
Applying Data Augmentation and Mask R-CNN-Based Instance Segmentation Method for Mixed-Type Wafer Maps Defect Patterns Classification22
Advanced Quality Control (AQC) of Silicon Wafer Specifications for Yield Enhancement for Smart Manufacturing21
Support Weighted Ensemble Model for Open Set Recognition of Wafer Map Defects21
Deep Learning Approach to Inverse Grain Pattern of Nanosized Metal Gate for Multichannel Gate-All-Around Silicon Nanosheet MOSFETs18
CNNs Combined With a Conditional GAN for Mura Defect Classification in TFT-LCDs18
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