OOIR: Observatory of International Research

Papers

(The median citation count of International Journal of Parallel Programming is 1. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-11-01 to 2024-11-01.)

Article	Citations
DeeperThings: Fully Distributed CNN Inference on Resource-Constrained Edge Devices	30
SkePU 3: Portable High-Level Programming of Heterogeneous Systems and HPC Clusters	13
Algorithmic Skeletons and Parallel Design Patterns in Mainstream Parallel Programming	9
A Comparative Survey of Big Data Computing and HPC: From a Parallel Programming Model to a Cluster Architecture	9
High-Level Parallel Ant Colony Optimization with Algorithmic Skeletons	8
Distributed-Memory FastFlow Building Blocks	8
Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments	8
A Profile-Based AI-Assisted Dynamic Scheduling Approach for Heterogeneous Architectures	6
RDMA-Based Apache Storm for High-Performance Stream Data Processing	6
Fault-Tolerant and Unicast Performances of the Data Center Network HSDC	6
Location-based and Time-aware Service Recommendation in Mobile Edge Computing	6
DRAMSys4.0: An Open-Source Simulation Framework for In-depth DRAM Analyses	5
Accelerating DES and AES Algorithms for a Heterogeneous Many-core Processor	5
The Celerity High-level API: C++20 for Accelerator Clusters	5
Statistical Analysis Based Intrusion Detection System for Ultra-High-Speed Software Defined Network	5
A Map-Reduce Approach for the Dijkstra Algorithm in SDN Over Osmotic Computing Systems	4
Enabling Near-Data Accelerators Adoption by Through Investigation of Datapath Solutions	4
Stencil Calculations with Algorithmic Skeletons for Heterogeneous Computing Environments	4
Assessing Application Efficiency and Performance Portability in Single-Source Programming for Heterogeneous Parallel Systems	3
Portable C++ Code that can Look and Feel Like Fortran Code with Yet Another Kernel Launcher (YAKL)	3
Accelerating Computation of Steiner Trees on GPUs	3
iDocChip: A Configurable Hardware Architecture for Historical Document Image Processing	3
A Hybrid Machine Learning Model for Code Optimization	3
Predicting the Soft Error Vulnerability of Parallel Applications Using Machine Learning	3
Energy-Efficient Partial-Duplication Task Mapping Under Multiple DVFS Schemes	3

Segmented Merge: A New Primitive for Parallel Sparse Matrix Computations	3
Parallelization of Swarm Intelligence Algorithms: Literature Review	3
A Scalable Similarity Join Algorithm Based on MapReduce and LSH	3
High-performance Migration Tool for Live Container in a Workflow	3
Bounds Checking on GPU	3
Fine-Grained Power Modeling of Multicore Processors Using FFNNs	2
A Quantitative Study of Locality in GPU Caches for Memory-Divergent Workloads	2
DSParLib: A C++ Template Library for Distributed Stream Parallelism	2
Accelerating OCaml Programs on FPGA	2
Access Interval Prediction by Partial Matching for Tightly Coupled Memory Systems	2
Scaling the Maximum Flow Computation on GPUs	2
M-DRL: Deep Reinforcement Learning Based Coflow Traffic Scheduler with MLFQ Threshold Adaption	2
A Parallel Skeleton for Divide-and-conquer Unbalanced and Deep Problems	2
DynaCo: Dynamic Coherence Management for Tiled Manycore Architectures	2
A Methodology for Efficient Tile Size Selection for Affine Loop Kernels	2
Parallel Computation of Discrete Orthogonal Moment on Block Represented Images Using OpenMP	2
Orchestration Extensions for Interference- and Heterogeneity-Aware Placement for Data-Analytics	1
Guest Editorial: Special Issue on 2020 IEEE International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS 2020)	1
Monoparametric Tiling of Polyhedral Programs	1
An Improved/Optimized Practical Non-Blocking PageRank Algorithm for Massive Graphs*	1
Fortress Abstractions in X10 Framework	1
Declarative Data Flow in a Graph-Based Distributed Memory Runtime System	1
DySHARQ: Dynamic Software-Defined Hardware-Managed Queues for Tile-Based Architectures	1
Yet Another Lock-Free Atom Table Design for Scalable Symbol Management in Prolog	1
Compiler-assisted Operator Template Library for DNN Accelerators	1
ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation	1
A Power-Aware Hybrid Cache for Chip-Multi Processors Based on Neural Network Prediction Technique	1
Hardware-Aware Evolutionary Explainable Filter Pruning for Convolutional Neural Networks	1