IEEE Transactions on Computer-Aided Design of Integrated Circuits and

Article	Citations
DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training	98
RowHammer: A Retrospective	95
Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs	89
Approximation Attacks on Strong PUFs	87
Hardware/Software Co-Exploration of Neural Architectures	82
A Memristive Synapse Control Method to Generate Diversified Multistructure Chaotic Attractors	74
High-Level Synthesis Design Space Exploration: Past, Present, and Future	65
MRIMA: An MRAM-Based In-Memory Accelerator	64
Keynote: A Disquisition on Logic Locking	63
Noise-Aware DVFS for Efficient Transitions on Battery-Powered IoT Devices	62
An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools	58
An Artificial Neural Network Assisted Optimization System for Analog Design Space Exploration	56
LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults	55
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement	55
RxNN: A Framework for Evaluating Deep Neural Networks on Resistive Crossbars	54
DNNVM: End-to-End Compiler Leveraging Heterogeneous Optimizations on FPGA-Based CNN Accelerators	54
High-Throughput CNN Inference on Embedded ARM Big.LITTLE Multicore Processors	53
SIMPLER MAGIC: Synthesis and Mapping of In-Memory Logic Executed in a Single Row to Improve Throughput	52
CKFO: Convolution Kernel First Operated Algorithm With Applications in Memristor-Based Convolutional Neural Network	52
SearcHD: A Memory-Centric Hyperdimensional Computing With Stochastic Training	45
GAN-OPC: Mask Optimization With Lithography-Guided Generative Adversarial Nets	43
Throughput-Conscious Energy Allocation and Reliability-Aware Task Assignment for Renewable Powered In-Situ Server Systems	42
High-Performance Accurate and Approximate Multipliers for FPGA-Based Hardware Accelerators	40
Real-Time Detection and Localization of Distributed DoS Attacks in NoC-Based SoCs	40
Truly Stripping Functionality for Logic Locking: A Fault-Based Perspective	39

QuantHD: A Quantization Framework for Hyperdimensional Computing	39
Standing on the Shoulders of Giants: Hardware and Neural Architecture Co-Search With Hot Start	39
Low Bit-Width Convolutional Neural Network on RRAM	38
A Novel Memristive Chaotic Neuron Circuit and Its Application in Chaotic Neural Networks for Associative Memory	37
Advanced Equivalence Checking for Quantum Circuits	36
A Modeling Attack Resistant Deception Technique for Securing Lightweight-PUF-Based Authentication	36
Thwarting All Logic Locking Attacks: Dishonest Oracle With Truly Random Logic Locking	36
High Frequency Meminductor Emulator Employing VDTA and its Application	36
Performance Modeling for CNN Inference Accelerators on FPGA	34
Exploring Renewable-Adaptive Computation Offloading for Hierarchical QoS Optimization in Fog Computing	34
NPU Thermal Management	32
FSpiNN: An Optimization Framework for Memory-Efficient and Energy-Efficient Spiking Neural Networks	31
Quantum Circuit Transformation Based on Simulated Annealing and Heuristic Search	31
X-CGRA: An Energy-Efficient Approximate Coarse-Grained Reconfigurable Architecture	31
Chaotic Weights: A Novel Approach to Protect Intellectual Property of Deep Neural Networks	30
A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC	29
AccuReD: High Accuracy Training of CNNs on ReRAM/GPU Heterogeneous 3-D Architecture	29
INDRA: Intrusion Detection Using Recurrent Autoencoders in Automotive Embedded Systems	29
Memristive Circuit Implementation of Context-Dependent Emotional Learning Network and Its Application in Multitask	29
Energy-Efficient Real-Time UAV Object Detection on Embedded Platforms	29
Client Scheduling and Resource Management for Efficient Training in Heterogeneous IoT-Edge Federated Learning	28
OpenTimer v2: A New Parallel Incremental Timing Analysis Engine	28
Efficient Federated Learning for Cloud-Based AIoT Applications	28
SAT-Based Exact Synthesis: Encodings, Topology Families, and Parallelism	28
Scalable Activation of Rare Triggers in Hardware Trojans by Repeated Maximal Clique Sampling	28
Flux Controlled Floating Memristor Employing VDTA: Incremental or Decremental Operation	28
LESS-MICS: A Low Energy Standby-Sparing Scheme for Mixed-Criticality Systems	28
ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs	28
MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper	28
Eva-CiM: A System-Level Performance and Energy Evaluation Framework for Computing-in-Memory Architectures	27
An Efficient Batch-Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multiobjective Acquisition Ensemble	27
StereoEngine: An FPGA-Based Accelerator for Real-Time High-Quality Stereo Estimation With Binary Neural Network	26
AdaMD: Adaptive Mapping and DVFS for Energy-Efficient Heterogeneous Multicores	26
WinoNN: Optimizing FPGA-Based Convolutional Neural Network Accelerators Using Sparse Winograd Algorithm	25
Compact-2D: A Physical Design Methodology to Build Two-Tier Gate-Level 3-D ICs	25
OMNI: A Framework for Integrating Hardware and Software Optimizations for Sparse CNNs	25
Performance Modeling and Directives Optimization for High-Level Synthesis on FPGA	25
Timing-Driven Flow-Channel Network Construction for Continuous-Flow Microfluidic Biochips	25
Peak-Power-Aware Energy Management for Periodic Real-Time Applications	25
Handling Stuck-at-Fault Defects Using Matrix Transformation for Robust Inference of DNNs	25
An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization	25
Dynamic DAG Scheduling on Multiprocessor Systems: Reliability, Energy, and Makespan	24
SoFI: Security Property-Driven Vulnerability Assessments of ICs Against Fault-Injection Attacks	24
RTL to Transistor Level Power Modeling and Estimation Techniques for FPGA and ASIC: A Survey	24
Everything Leaves Footprints: Hardware Accelerated Intermittent Deep Inference	23
The Software/Hardware Co-Design and Implementation of SM2/3/4 Encryption/Decryption and Digital Signature System	23
Toward an Efficient Deep Pipelined Template-Based Architecture for Accelerating the Entire 2-D and 3-D CNNs on FPGA	23
Physically Unclonable and Reconfigurable Computing System (PURCS) for Hardware Security Applications	23
Using Error Modes Aware LDPC to Improve Decoding Performance of 3-D TLC NAND Flash	23
A Triple-Memristor Hopfield Neural Network With Space Multistructure Attractors and Space Initial-Offset Behaviors	23

Timing-Aware Layer Assignment for Advanced Process Technologies Considering via Pillars	22
Fusion-Catalyzed Pruning for Optimizing Deep Learning on Intelligent Edge Devices	22
Boosting Bit-Error Resilience of DNN Accelerators Through Median Feature Selection	22
Multilayer Memristive Neural Network Circuit Based on Online Learning for License Plate Detection	21
Multicontrol: Advanced Control-Logic Synthesis for Flow-Based Microfluidic Biochips	21
Exploring Edge Computing for Multitier Industrial Control	21
Runtime Task Scheduling Using Imitation Learning for Heterogeneous Many-Core Systems	21
A Memristive Spiking Neural Network Circuit With Selective Supervised Attention Algorithm	21
Power-Aware Runtime Scheduler for Mixed-Criticality Systems on Multicore Platform	21
High-Dimensional Uncertainty Quantification of Electronic and Photonic IC With Non-Gaussian Correlated Process Variations	21
Rubik: A Hierarchical Architecture for Efficient Graph Neural Network Training	21
Enabling On-Device CNN Training by Self-Supervised Instance Filtering and Error Map Pruning	20
Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging	20
Timing and Resource-Aware Mapping of Quantum Circuits to Superconducting Processors	20
Block Convolution: Toward Memory-Efficient Inference of Large-Scale CNNs on FPGA	20
Understanding Algebraic Rewriting for Arithmetic Circuit Verification: A Bit-Flow Model	20
Memristor Model Optimization Based on Parameter Extraction From Device Characterization Data	19
GNN-RE: Graph Neural Networks for Reverse Engineering of Gate-Level Netlists	19
A Computationally Efficient Tensor Regression Network-Based Modeling Attack on XOR Arbiter PUF and Its Variants	19
Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning Attacks	19
Enhancing Network-on-Chip Performance by Reusing Trace Buffers	18
Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design	18
DSP-Efficient Hardware Acceleration of Convolutional Neural Network Inference on FPGAs	18
Eh?Predictor: A Deep Learning Framework to Identify Detailed Routing Short Violations From a Placed Netlist	18
A Streaming Dataflow Engine for Sparse Matrix-Vector Multiplication Using High-Level Synthesis	18
Energy-Aware Mixed-criticality Sporadic Task Scheduling Algorithm	18
An Automated Topology Synthesis Framework for Analog Integrated Circuits	18
A Physical Design Flow Against Front-Side Probing Attacks by Internal Shielding	18
DCSA: Distributed Channel-Storage Architecture for Flow-Based Microfluidic Biochips	18
Cross-Layer Co-Optimization of Network Design and Chiplet Placement in 2.5-D Systems	18
LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments	18
UltraTrail: A Configurable Ultralow-Power TC-ResNet AI Accelerator for Efficient Keyword Spotting	17
Practical Attacks on Deep Neural Networks by Memory Trojaning	17
Improved Mapping of Quantum Circuits to IBM QX Architectures	17
TritonRoute: The Open-Source Detailed Router	17
A Dynamic Look-Ahead Heuristic for the Qubit Mapping Problem of NISQ Computers	17
An Efficient Hardware Design for Accelerating Sparse CNNs With NAS-Based Models	17
Mathematical Modeling Analysis of Strong Physical Unclonable Functions	17
Exact Synthesis of Nearest Neighbor Compliant Quantum Circuits in 2-D Architecture and Its Application to Large-Scale Circuits	17
H₂O-Cloud: A Resource and Quality of Service-Aware Task Scheduling Framework for Warehouse-Scale Data Centers	17
Optimizing Energy in Non-Preemptive Mixed-Criticality Scheduling by Exploiting Probabilistic Information	17
Analog and Mixed-Signal IC Security via Sizing Camouflaging	17
Optimized Selection of Reliable and Cost-Effective Safety-Critical System Architectures	17
RevSCA-2.0: SCA-Based Formal Verification of Nontrivial Multipliers Using Reverse Engineering and Local Vanishing Removal	17
Dr. CU: Detailed Routing by Sparse Grid Graph and Minimum-Area-Captured Path Search	17
Asymptotically Optimal Circuit Depth for Quantum State Preparation and General Unitary Synthesis	17
Taskflow: A General-Purpose Parallel and Heterogeneous Task Programming System	17
A Guaranteed Secure Scan Design Based on Test Data Obfuscation by Cryptographic Hash	16
DeepPrefetcher: A Deep Learning Framework for Data Prefetching in Flash Storage Devices	16
NeuADC: Neural Network-Inspired Synthesizable Analog-to-Digital Conversion	16
High Performance Modular Multiplication for SIDH	16
Leakage-Aware Predictive Thermal Management for Multicore Systems Using Echo State Network	16
Efficient Scheduling of Irregular Network Structures on CNN Accelerators	16
Cpp-Taskflow: A General-Purpose Parallel Task Programming System at Scale	16
Logic Synthesis of Approximate Circuits	16
Fast DRAM PUFs on Commodity Devices	16
GoodFloorplan: Graph Convolutional Network and Reinforcement Learning-Based Floorplanning	16
Leveraging Prior Knowledge for Effective Design-Space Exploration in High-Level Synthesis	15
Multilabel Deep Learning-Based Side-Channel Attack	15
Modeling and Simulating Electromagnetic Fault Injection	15
Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime	15
A DVFS-Weakly Dependent Energy-Efficient Scheduling Approach for Deadline-Constrained Parallel Applications on Heterogeneous Systems	15
A Fast Semi-Analytic Approach for Combined Electromigration and Thermomigration Analysis for General Multisegment Interconnects	15
ITT-RNA: Imperfection Tolerable Training for RRAM-Crossbar-Based Deep Neural-Network Accelerator	15
AnyHLS: High-Level Synthesis With Partial Evaluation	15
ECG-Based Authentication Using Timing-Aware Domain-Specific Architecture	15
VoltJockey: A New Dynamic Voltage Scaling-Based Fault Injection Attack on Intel SGX	15
Diagonal Matrix Regression Layer: Training Neural Networks on Resistive Crossbars With Interconnect Resistance Effect	15
Optrone: Maximizing Performance and Energy Resources of Drone Batteries	15
Hardware Memory Management for Future Mobile Hybrid Memory Systems	14
Combating Enhanced Thermal Covert Channel in Multi-/Many-Core Systems With Channel-Aware Jamming	14
Clock-Aware Placement for Large-Scale Heterogeneous FPGAs	14
Improving Combinational Circuit Reliability Against Multiple Event Transients via a Partition and Restructuring Approach	14
Defect-Oriented Test: Effectiveness in High Volume Manufacturing	14
Retention Correlated Read Disturb Errors in 3-D Charge Trap NAND Flash Memory: Observations, Analysis, and Solutions	14
A Novel Area-Power Efficient Design for Approximated Small-Point FFT Architecture	14
On Error Injection for NoC Platforms: A UVM-Based Generic Verification Environment	14
Skydiver: A Spiking Neural Network Accelerator Exploiting Spatio-Temporal Workload Balance	14
Test and Yield Loss Reduction of AI and Deep Learning Accelerators	14
QuCTS—Single-Flux Quantum Clock Tree Synthesis	14

SALT: Provably Good Routing Topology by a Novel Steiner Shallow-Light Tree Algorithm	14
SCANN: Synthesis of Compact and Accurate Neural Networks	14
Memristor-Based Edge Computing of ShuffleNetV2 for Image Classification	14
LoCoMOBO: A Local Constrained Multiobjective Bayesian Optimization for Analog Circuit Sizing	14
Approaches for Assigning Offsets to Signals for Improving Frame Packing in CAN-FD	14
From IC Layout to Die Photograph: A CNN-Based Data-Driven Approach	13
ChordMap: Automated Mapping of Streaming Applications Onto CGRA	13
A Lightweight Full Entropy TRNG With On-Chip Entropy Assurance	13
SPINBIS: Spintronics-Based Bayesian Inference System With Stochastic Computing	13
Robust Deep Reservoir Computing Through Reliable Memristor With Improved Heat Dissipation Capability	13
HPE: Hierarchical Page Eviction Policy for Unified Memory in GPUs	13
Attack-Aware Detection and Defense to Resist Adversarial Examples	13
A Design Framework for Invertible Logic	13
An Analog Circuit Design and Optimization System With Rule-Guided Genetic Algorithm	13
C-Testing and Efficient Fault Localization for AI Accelerators	13
CRIMSON: Compute-Intensive Loop Acceleration by Randomized Iterative Modulo Scheduling and Optimized Mapping on CGRAs	13
Semisupervised Hotspot Detection With Self-Paced Multitask Learning	13
Optimizing Sensor Deployment and Maintenance Costs for Large-Scale Environmental Monitoring	13
Unary Coding and Variation-Aware Optimal Mapping Scheme for Reliable ReRAM-Based Neuromorphic Computing	13
Advanced Functional Decomposition Using Majority and Its Applications	13
Cambricon-G: A Polyvalent Energy-Efficient Accelerator for Dynamic Graph Neural Networks	13
Impact of Thermal Boundary Resistance on the Performance and Scaling of Phase-Change Memory Device	13
ParRA: A Shared Memory Parallel FPGA Router Using Hybrid Partitioning Approach	13
BlockHammer: Improving Flash Reliability by Exploiting Process Variation Aware Proactive Failure Prediction	13
SAFARI: Automatic Synthesis of Fault-Attack Resistant Block Cipher Implementations	13
Simulation and Experimental Demonstration of the Importance of IR-Drops During Laser Fault Injection	13
Online Signal Monitoring With Bounded Lag	13
Hardware Assisted Buffer Protection Mechanisms for Embedded RISC-V	13
CAMON: Low-Cost Silicon Photonic Chiplet for Manycore Processors	13
Hardware Trojan Detection using Graph Neural Networks	13
Energy-Constrained Data Freshness Optimization in Self-Powered Networked Embedded Systems	13
Hardware Trojan Detection Using Backside Optical Imaging	13
Enabling Failure-Resilient Intermittent Systems Without Runtime Checkpointing	13
Logic Bug Detection and Localization Using Symbolic Quick Error Detection	12
IronMan-Pro: Multiobjective Design Space Exploration in HLS via Reinforcement Learning and Graph Neural Network-Based Modeling	12
Patch-Based Data Management for Dual-Copy Buffers in RAID-Enabled SSDs	12
RANC: Reconfigurable Architecture for Neuromorphic Computing	12
Faster Region-Based Hotspot Detection	12
MacLeR: Machine Learning-Based Runtime Hardware Trojan Detection in Resource-Constrained IoT Edge Devices	12
ABCFI: Fast and Lightweight Fine-Grained Hardware-Assisted Control-Flow Integrity	12
Detecting Failures and Attacks via Digital Sensors	12
CNN-on-AWS: Efficient Allocation of Multikernel Applications on Multi-FPGA Platforms	12
BonnCell: Automatic Cell Layout in the 7-nm Era	12
Bridging the Gap Between Layout Pattern Sampling and Hotspot Detection via Batch Active Learning	12
LOOPLock: Logic Optimization-Based Cyclic Logic Locking	12
Toward Hardware-Efficient Optical Neural Networks: Beyond FFT Architecture via Joint Learnability	12
Deep H-GCN: Fast Analog IC Aging-Induced Degradation Estimation	12
Microfluidic Design for Concentration Gradient Generation Using Artificial Neural Network	12
Pin-Accessible Legalization for Mixed-Cell-Height Circuits	12
3D-ICE 3.0: Efficient Nonlinear MPSoC Thermal Simulation With Pluggable Heat Sink Models	12
Toward a High-Performance and Low-Loss Clos–Benes-Based Optical Network-on-Chip Architecture	12
Maximal Independent Fault Set for Gate-Exhaustive Faults	12
GRASS: Graph Spectral Sparsification Leveraging Scalable Spectral Perturbation Analysis	12
Fast Lagrangian Relaxation-Based Multithreaded Gate Sizing Using Simple Timing Calibrations	12
Efficient and Robust RRAM-Based Convolutional Weight Mapping With Shifted and Duplicated Kernel	12
Security-Aware Obfuscated Priority Assignment for CAN FD Messages in Real-Time Parallel Automotive Applications	12
An Interlayer Interconnect BIST and Diagnosis Solution for Monolithic 3-D ICs	11
Silicon Photonic Microring Resonators: A Comprehensive Design-Space Exploration and Optimization Under Fabrication-Process Variations	11
Deterministic Stellar BIST for Automotive ICs	11
GAN-SRAF: Subresolution Assist Feature Generation Using Generative Adversarial Networks	11
Divide and Slide: Layer-Wise Refinement for Output Range Analysis of Deep Neural Networks	11
Assume–Guarantee Distributed Synthesis	11
Temperature-Aware Persistent Data Management for LSM-Tree on 3-D NAND Flash Memory	11
Dynamic Memory Bandwidth Allocation for Real-Time GPU-Based SoC Platforms	11
ViA: A Novel Vision-Transformer Accelerator Based on FPGA	11
EM-Fuzz: Augmented Firmware Fuzzing via Memory Checking	11
Improving Reliability of Soft Real-Time Embedded Systems on Integrated CPU and GPU Platforms	11
Safe Overclocking for CNN Accelerators Through Algorithm-Level Error Detection	11
Multitarget Sample Preparation Using MEDA Biochips	11
FLAM-PUF: A Response–Feedback-Based Lightweight Anti-Machine-Learning-Attack PUF	11
Reconfigurable and Low-Complexity Accelerator for Convolutional and Generative Networks Over Finite Fields	11
Swallow: A Versatile Accelerator for Sparse Neural Networks	11
elfPlace: Electrostatics-Based Placement for Large-Scale Heterogeneous FPGAs	11
RLPlace: Using Reinforcement Learning and Smart Perturbations to Optimize FPGA Placement	11
Toward the Design of Fault-Tolerance-Aware and Peak-Power-Aware Multicore Mixed-Criticality Systems	11
Contention-Aware Routing for Thermal-Reliable Optical Networks-on-Chip	11
Detecting Hardware Trojans Using Combined Self-Testing and Imaging	11
Learning-Based Quality Management for Approximate Communication in Network-on-Chips	11
A New Compact MOSFET Model Based on Artificial Neural Network With Unique Data Preprocessing and Sampling Techniques	11
System-Level Energy-Aware Design Methodology Towards End-To-End Response Time Optimization	11
Resistorless Memristor Emulators: Floating and Grounded Using OTA and VDBA for High-Frequency Applications	11
SRAF Insertion via Supervised Dictionary Learning	11
Power Delivery Exploration Methodology Based on Constrained Optimization	11
LeGO: A Learning-Guided Obfuscation Framework for Hardware IP Protection	11
eWASM: Practical Software Fault Isolation for Reliable Embedded Devices	11
From C/C++ Code to High-Performance Dataflow Circuits	11
When Storage Response Time Catches Up With Overall Context Switch Overhead, What Is Next?	11
SP&R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes	11
Addressing a New Class of Reliability Threats in 3-D Network-on-Chips	11
READY: Reliability- and Deadline-Aware Power-Budgeting for Heterogeneous Multicore Systems	11
A Lightweight Nonlinear Methodology to Accurately Model Multicore Processor Power	11
Exploiting Process Variations to Secure Photonic NoC Architectures From Snooping Attacks	10
Defending Hardware-Based Malware Detectors Against Adversarial Attacks	10
Reduced Worst-Case Communication Latency Using Single-Cycle Multihop Traversal Network-on-Chip	10
Multiagent Reinforcement Learning for Hyperparameter Optimization of Convolutional Neural Networks	10