IEEE Transactions on Computer-Aided Design of Integrated Circuits and

Article	Citations
DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training	124
Hardware/Software Co-Exploration of Neural Architectures	89
A Memristive Synapse Control Method to Generate Diversified Multistructure Chaotic Attractors	88
An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools	78
RxNN: A Framework for Evaluating Deep Neural Networks on Resistive Crossbars	66
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement	64
CKFO: Convolution Kernel First Operated Algorithm With Applications in Memristor-Based Convolutional Neural Network	61
A Triple-Memristor Hopfield Neural Network With Space Multistructure Attractors and Space Initial-Offset Behaviors	56
High-Performance Accurate and Approximate Multipliers for FPGA-Based Hardware Accelerators	52
Client Scheduling and Resource Management for Efficient Training in Heterogeneous IoT-Edge Federated Learning	50
Advanced Equivalence Checking for Quantum Circuits	48
Truly Stripping Functionality for Logic Locking: A Fault-Based Perspective	48
Throughput-Conscious Energy Allocation and Reliability-Aware Task Assignment for Renewable Powered In-Situ Server Systems	46
Thwarting All Logic Locking Attacks: Dishonest Oracle With Truly Random Logic Locking	46
Real-Time Detection and Localization of Distributed DoS Attacks in NoC-Based SoCs	46
Standing on the Shoulders of Giants: Hardware and Neural Architecture Co-Search With Hot Start	45
A Modeling Attack Resistant Deception Technique for Securing Lightweight-PUF-Based Authentication	43
A Novel Memristive Chaotic Neuron Circuit and Its Application in Chaotic Neural Networks for Associative Memory	41
An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization	41
MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper	40
A Memristive Spiking Neural Network Circuit With Selective Supervised Attention Algorithm	39
Quantum Circuit Transformation Based on Simulated Annealing and Heuristic Search	37
Efficient Federated Learning for Cloud-Based AIoT Applications	37
An Efficient Batch-Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multiobjective Acquisition Ensemble	36
Chaotic Weights: A Novel Approach to Protect Intellectual Property of Deep Neural Networks	35

Dynamic DAG Scheduling on Multiprocessor Systems: Reliability, Energy, and Makespan	35
QuCTS—Single-Flux Quantum Clock Tree Synthesis	35
NPU Thermal Management	35
Flux Controlled Floating Memristor Employing VDTA: Incremental or Decremental Operation	35
INDRA: Intrusion Detection Using Recurrent Autoencoders in Automotive Embedded Systems	35
Memristive Circuit Implementation of Context-Dependent Emotional Learning Network and Its Application in Multitask	34
FSpiNN: An Optimization Framework for Memory-Efficient and Energy-Efficient Spiking Neural Networks	34
AccuReD: High Accuracy Training of CNNs on ReRAM/GPU Heterogeneous 3-D Architecture	33
ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs	33
OpenTimer v2: A New Parallel Incremental Timing Analysis Engine	33
SoFI: Security Property-Driven Vulnerability Assessments of ICs Against Fault-Injection Attacks	33
Scalable Activation of Rare Triggers in Hardware Trojans by Repeated Maximal Clique Sampling	31
Eva-CiM: A System-Level Performance and Energy Evaluation Framework for Computing-in-Memory Architectures	31
A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC	30
GNN-RE: Graph Neural Networks for Reverse Engineering of Gate-Level Netlists	30
OMNI: A Framework for Integrating Hardware and Software Optimizations for Sparse CNNs	29
Timing-Aware Layer Assignment for Advanced Process Technologies Considering via Pillars	29
StereoEngine: An FPGA-Based Accelerator for Real-Time High-Quality Stereo Estimation With Binary Neural Network	28
ViA: A Novel Vision-Transformer Accelerator Based on FPGA	28
RTL to Transistor Level Power Modeling and Estimation Techniques for FPGA and ASIC: A Survey	28
LESS-MICS: A Low Energy Standby-Sparing Scheme for Mixed-Criticality Systems	28
WinoNN: Optimizing FPGA-Based Convolutional Neural Network Accelerators Using Sparse Winograd Algorithm	27
Fusion-Catalyzed Pruning for Optimizing Deep Learning on Intelligent Edge Devices	27
Asymptotically Optimal Circuit Depth for Quantum State Preparation and General Unitary Synthesis	27
Rubik: A Hierarchical Architecture for Efficient Graph Neural Network Training	27
Boosting Bit-Error Resilience of DNN Accelerators Through Median Feature Selection	26
Everything Leaves Footprints: Hardware Accelerated Intermittent Deep Inference	26
An Analog Circuit Design and Optimization System With Rule-Guided Genetic Algorithm	26
Multilayer Memristive Neural Network Circuit Based on Online Learning for License Plate Detection	25
Timing and Resource-Aware Mapping of Quantum Circuits to Superconducting Processors	25
Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning Attacks	25
Modeling and Simulating Electromagnetic Fault Injection	25
Physically Unclonable and Reconfigurable Computing System (PURCS) for Hardware Security Applications	25
Block Convolution: Toward Memory-Efficient Inference of Large-Scale CNNs on FPGA	25
Runtime Task Scheduling Using Imitation Learning for Heterogeneous Many-Core Systems	24
Exploring Edge Computing for Multitier Industrial Control	24
A Computationally Efficient Tensor Regression Network-Based Modeling Attack on XOR Arbiter PUF and Its Variants	23
LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments	23
Cross-Layer Co-Optimization of Network Design and Chiplet Placement in 2.5-D Systems	22
Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging	22
DSP-Efficient Hardware Acceleration of Convolutional Neural Network Inference on FPGAs	22
Hardware Trojan Detection using Graph Neural Networks	22
Leveraging Prior Knowledge for Effective Design-Space Exploration in High-Level Synthesis	21
DCSA: Distributed Channel-Storage Architecture for Flow-Based Microfluidic Biochips	21
A Dynamic Look-Ahead Heuristic for the Qubit Mapping Problem of NISQ Computers	21
UltraTrail: A Configurable Ultralow-Power TC-ResNet AI Accelerator for Efficient Keyword Spotting	21
Enabling On-Device CNN Training by Self-Supervised Instance Filtering and Error Map Pruning	21
Power-Aware Runtime Scheduler for Mixed-Criticality Systems on Multicore Platform	21
Fast DRAM PUFs on Commodity Devices	20
A DVFS-Weakly Dependent Energy-Efficient Scheduling Approach for Deadline-Constrained Parallel Applications on Heterogeneous Systems	20

Energy-Aware Mixed-criticality Sporadic Task Scheduling Algorithm	20
H2Learn: High-Efficiency Learning Accelerator for High-Accuracy Spiking Neural Networks	20
RevSCA-2.0: SCA-Based Formal Verification of Nontrivial Multipliers Using Reverse Engineering and Local Vanishing Removal	20
Multilabel Deep Learning-Based Side-Channel Attack	19
An Efficient Hardware Design for Accelerating Sparse CNNs With NAS-Based Models	19
An Automated Topology Synthesis Framework for Analog Integrated Circuits	19
Efficient Scheduling of Irregular Network Structures on CNN Accelerators	19
Mathematical Modeling Analysis of Strong Physical Unclonable Functions	19
IronMan-Pro: Multiobjective Design Space Exploration in HLS via Reinforcement Learning and Graph Neural Network-Based Modeling	19
GoodFloorplan: Graph Convolutional Network and Reinforcement Learning-Based Floorplanning	19
A Guaranteed Secure Scan Design Based on Test Data Obfuscation by Cryptographic Hash	18
Diagonal Matrix Regression Layer: Training Neural Networks on Resistive Crossbars With Interconnect Resistance Effect	18
Test and Yield Loss Reduction of AI and Deep Learning Accelerators	18
Swarm Intelligence-Based Task Scheduling for Enhancing Security for IoT Devices	18
DeepPrefetcher: A Deep Learning Framework for Data Prefetching in Flash Storage Devices	18
Optrone: Maximizing Performance and Energy Resources of Drone Batteries	18
ITT-RNA: Imperfection Tolerable Training for RRAM-Crossbar-Based Deep Neural-Network Accelerator	18
An Edge 3D CNN Accelerator for Low-Power Activity Recognition	18
TritonRoute: The Open-Source Detailed Router	18
Analog and Mixed-Signal IC Security via Sizing Camouflaging	18
Practical Attacks on Deep Neural Networks by Memory Trojaning	18
MURLAV: A Multiple-Node-Upset Recovery Latch and Algorithm-Based Verification Method	18
Skydiver: A Spiking Neural Network Accelerator Exploiting Spatio-Temporal Workload Balance	17
Optimizing Energy in Non-Preemptive Mixed-Criticality Scheduling by Exploiting Probabilistic Information	17
Optimizing Sensor Deployment and Maintenance Costs for Large-Scale Environmental Monitoring	17
LoCoMOBO: A Local Constrained Multiobjective Bayesian Optimization for Analog Circuit Sizing	17
AnyHLS: High-Level Synthesis With Partial Evaluation	17
Hardware Memory Management for Future Mobile Hybrid Memory Systems	17
VoltJockey: A New Dynamic Voltage Scaling-Based Fault Injection Attack on Intel SGX	17
Error Detection Architectures for Hardware/Software Co-Design Approaches of Number-Theoretic Transform	17
A Fast Semi-Analytic Approach for Combined Electromigration and Thermomigration Analysis for General Multisegment Interconnects	17
SATA: Sparsity-Aware Training Accelerator for Spiking Neural Networks	17
RANC: Reconfigurable Architecture for Neuromorphic Computing	17
Efficient and Robust RRAM-Based Convolutional Weight Mapping With Shifted and Duplicated Kernel	17
Taskflow: A General-Purpose Parallel and Heterogeneous Task Programming System	17
Reconfigurable and Low-Complexity Accelerator for Convolutional and Generative Networks Over Finite Fields	17
Retention Correlated Read Disturb Errors in 3-D Charge Trap NAND Flash Memory: Observations, Analysis, and Solutions	17
Cpp-Taskflow: A General-Purpose Parallel Task Programming System at Scale	16
Clock-Aware Placement for Large-Scale Heterogeneous FPGAs	16
A Content-Based Ransomware Detection and Backup Solid-State Drive for Ransomware Defense	16
HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction	16
RLPlace: Using Reinforcement Learning and Smart Perturbations to Optimize FPGA Placement	16
GNN4REL: Graph Neural Networks for Predicting Circuit Reliability Degradation	16
Memristor-Based Edge Computing of ShuffleNetV2 for Image Classification	16
Neural-ILT 2.0: Migrating ILT to Domain-Specific and Multitask-Enabled Neural Network	16
3D-ICE 3.0: Efficient Nonlinear MPSoC Thermal Simulation With Pluggable Heat Sink Models	16
Assume–Guarantee Distributed Synthesis	16
ECG-Based Authentication Using Timing-Aware Domain-Specific Architecture	16
Combating Enhanced Thermal Covert Channel in Multi-/Many-Core Systems With Channel-Aware Jamming	16
Deep H-GCN: Fast Analog IC Aging-Induced Degradation Estimation	16
ChordMap: Automated Mapping of Streaming Applications Onto CGRA	16
Defect-Oriented Test: Effectiveness in High Volume Manufacturing	16
Automated Design of Analog Circuits Using Reinforcement Learning	16
Analog Integrated Circuit Topology Synthesis With Deep Reinforcement Learning	16
LOOPLock 2.0: An Enhanced Cyclic Logic Locking Approach	15
Explainable Machine Learning for Intrusion Detection via Hardware Performance Counters	15
MacLeR: Machine Learning-Based Runtime Hardware Trojan Detection in Resource-Constrained IoT Edge Devices	15
Unary Coding and Variation-Aware Optimal Mapping Scheme for Reliable ReRAM-Based Neuromorphic Computing	15
Cambricon-G: A Polyvalent Energy-Efficient Accelerator for Dynamic Graph Neural Networks	15
Patch-Based Data Management for Dual-Copy Buffers in RAID-Enabled SSDs	15
A Design Framework for Invertible Logic	15
BlockHammer: Improving Flash Reliability by Exploiting Process Variation Aware Proactive Failure Prediction	15
AdaPT: Fast Emulation of Approximate DNN Accelerators in PyTorch	15
A Lightweight Full Entropy TRNG With On-Chip Entropy Assurance	15
Enabling Failure-Resilient Intermittent Systems Without Runtime Checkpointing	15
CRIMSON: Compute-Intensive Loop Acceleration by Randomized Iterative Modulo Scheduling and Optimized Mapping on CGRAs	15
FLAM-PUF: A Response–Feedback-Based Lightweight Anti-Machine-Learning-Attack PUF	15
SCANN: Synthesis of Compact and Accurate Neural Networks	14
Detecting Failures and Attacks via Digital Sensors	14
Pin-Accessible Legalization for Mixed-Cell-Height Circuits	14
Resistorless Memristor Emulators: Floating and Grounded Using OTA and VDBA for High-Frequency Applications	14
DAMO: Deep Agile Mask Optimization for Full-Chip Scale	14
SP&R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes	14
From C/C++ Code to High-Performance Dataflow Circuits	14
Improving Fault Tolerance for Reliable DNN Using Boundary-Aware Activation	14
EM-Fuzz: Augmented Firmware Fuzzing via Memory Checking	14
READY: Reliability- and Deadline-Aware Power-Budgeting for Heterogeneous Multicore Systems	14
Logic Bug Detection and Localization Using Symbolic Quick Error Detection	14
High-Dimensional Bayesian Optimization for Analog Integrated Circuit Sizing Based on Dropout and gm/ID Methodology	14
CNN-on-AWS: Efficient Allocation of Multikernel Applications on Multi-FPGA Platforms	14

Energon: Toward Efficient Acceleration of Transformers Using Dynamic Sparse Attention	14
Temperature-Aware Persistent Data Management for LSM-Tree on 3-D NAND Flash Memory	14
On the Stability of Analog ReLU Networks	14
Bridging the Gap Between Layout Pattern Sampling and Hotspot Detection via Batch Active Learning	14
From IC Layout to Die Photograph: A CNN-Based Data-Driven Approach	14
ABCFI: Fast and Lightweight Fine-Grained Hardware-Assisted Control-Flow Integrity	14
The Implementation and Optimization of Neuromorphic Hardware for Supporting Spiking Neural Networks With MLP and CNN Topologies	14
Hardware Assisted Buffer Protection Mechanisms for Embedded RISC-V	14
TRAVERSAL: A Fast and Adaptive Graph-Based Placement and Routing for CGRAs	14
Hardware Trojan Detection Using Backside Optical Imaging	14
Error Diluting: Exploiting 3-D nand Flash Process Variation for Efficient Read on LDPC-Based SSDs	14
FPGA-Based Acceleration for Bayesian Convolutional Neural Networks	14
A Novel Area-Power Efficient Design for Approximated Small-Point FFT Architecture	14
GRASS: Graph Spectral Sparsification Leveraging Scalable Spectral Perturbation Analysis	14
Contention-Aware Routing for Thermal-Reliable Optical Networks-on-Chip	13
Safety Analysis of Embedded Controllers Under Implementation Platform Timing Uncertainties	13
C-Testing and Efficient Fault Localization for AI Accelerators	13
FLASH: Fast, Parallel, and Accurate Simulator for HLS	13
Security-Aware Obfuscated Priority Assignment for CAN FD Messages in Real-Time Parallel Automotive Applications	13
Attack-Aware Detection and Defense to Resist Adversarial Examples	13
Fast Attack-Resilient Distributed State Estimator for Cyber-Physical Systems	13
Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation	13
TritonRoute-WXL: The Open-Source Router With Integrated DRC Engine	13
A New Compact MOSFET Model Based on Artificial Neural Network With Unique Data Preprocessing and Sampling Techniques	13
Robust Deep Reservoir Computing Through Reliable Memristor With Improved Heat Dissipation Capability	13
PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced Nodes	13
PTPT: Physical Design Tool Parameter Tuning via Multi-Objective Bayesian Optimization	13
Toward a High-Performance and Low-Loss Clos–Benes-Based Optical Network-on-Chip Architecture	13
Detecting Hardware Trojans Using Combined Self-Testing and Imaging	13
Toward Hardware-Efficient Optical Neural Networks: Beyond FFT Architecture via Joint Learnability	13
PathDriver+: Enhanced Path-Driven Architecture Design for Flow-Based Microfluidic Biochips	13
Online Signal Monitoring With Bounded Lag	13
A Probabilistic Machine Learning Approach for the Uncertainty Quantification of Electronic Circuits Based on Gaussian Process Regression	13
On-Chip Trust Evaluation Utilizing TDC-Based Parameter-Adjustable Security Primitive	13
Ferroelectric Ternary Content Addressable Memories for Energy-Efficient Associative Search	12
MNSIM 2.0: A Behavior-Level Modeling Tool for Processing-In-Memory Architectures	12
eWASM: Practical Software Fault Isolation for Reliable Embedded Devices	12
Equivalence Checking of Sequential Quantum Circuits	12
Dynamic Memory Bandwidth Allocation for Real-Time GPU-Based SoC Platforms	12
elfPlace: Electrostatics-Based Placement for Large-Scale Heterogeneous FPGAs	12
PAC Model Checking of Black-Box Continuous-Time Dynamical Systems	12
Energy-Efficient Image Recognition System for Marine Life	12
LightNAS: On Lightweight and Scalable Neural Architecture Search for Embedded Platforms	12
feGRASS: Fast and Effective Graph Spectral Sparsification for Scalable Power Grid Analysis	12
HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning	12
Silicon Photonic Microring Resonators: A Comprehensive Design-Space Exploration and Optimization Under Fabrication-Process Variations	12
Swallow: A Versatile Accelerator for Sparse Neural Networks	12
Multiagent Reinforcement Learning for Hyperparameter Optimization of Convolutional Neural Networks	12
Enabling Latency-Aware Data Initialization for Integrated CPU/GPU Heterogeneous Platform	12
LeGO: A Learning-Guided Obfuscation Framework for Hardware IP Protection	12
Hybrid System Falsification Under (In)equality Constraints via Search Space Transformation	12
MARS: Multimacro Architecture SRAM CIM-Based Accelerator With Co-Designed Compressed Neural Networks	12
CUTIE: Beyond PetaOp/s/W Ternary DNN Inference Acceleration With Better-Than-Binary Energy Efficiency	12
Large-Scale Quantum Approximate Optimization via Divide-and-Conquer	12
CircuitNet: An Open-Source Dataset for Machine Learning in VLSI CAD Applications With Improved Domain-Specific Evaluation Metric and Learning Strategies	12
Adaptive Edge Offloading for Image Classification Under Rate Limit	12
Accelerating Static Timing Analysis Using CPU–GPU Heterogeneous Parallelism	12
Defending Hardware-Based Malware Detectors Against Adversarial Attacks	12
REIN the RobuTS: Robust DNN-Based Image Recognition in Autonomous Driving Systems	12
DLUX: A LUT-Based Near-Bank Accelerator for Data Center Deep Learning Training Workloads	12
Maximal Independent Fault Set for Gate-Exhaustive Faults	12
Verifying Controllers With Vision-Based Perception Using Safe Approximate Abstractions	12
Faster Region-Based Hotspot Detection	12
RTL-ConTest: Concolic Testing on RTL for Detecting Security Vulnerabilities	12
On Minimizing Analog Variation Errors to Resolve the Scalability Issue of ReRAM-Based Crossbar Accelerators	12
Safe Overclocking for CNN Accelerators Through Algorithm-Level Error Detection	12
A Design Flow for Click-Based Asynchronous Circuits Design With Conventional EDA Tools	11
Ant Colony Optimization-Based Thermal-Aware Adaptive Routing Mechanism for Optical NoCs	11
iPROBE: Internal Shielding Approach for Protecting Against Front-Side and Back-Side Probing Attacks	11
SpikeSim: An End-to-End Compute-in-Memory Hardware Evaluation Tool for Benchmarking Spiking Neural Networks	11
ORACALL: An Oracle-Based Attack on Cellular Automata Guided Logic Locking	11
Energy-Aware Nonpreemptive Scheduling of Mixed-Criticality Real-Time Task Systems	11
Digitally Assisted Mixed-Signal Circuit Security	11
A Lightweight Nonlinear Methodology to Accurately Model Multicore Processor Power	11
LATICS: A Low-Overhead Adaptive Task-Based Intermittent Computing System	11
Hybrid RRAM/SRAM in-Memory Computing for Robust DNN Acceleration	11
Reduced Worst-Case Communication Latency Using Single-Cycle Multihop Traversal Network-on-Chip	11
Suspension-Aware Earliest-Deadline-First Scheduling Analysis	11
GAN-SRAF: Subresolution Assist Feature Generation Using Generative Adversarial Networks	11
Synthesis of Hidden State Transitions for Sequential Logic Locking	11
Layerwise Buffer Voltage Scaling for Energy-Efficient Convolutional Neural Network	11
SEAL: User Experience-Aware Two-Level Swap for Mobile Devices	11
How Secure Are Checkpoint-Based Defenses in Digital Microfluidic Biochips?	11
Fast Surrogate-Assisted Constrained Multiobjective Optimization for Analog Circuit Sizing via Self-Adaptive Incremental Learning	11
Preplacement Net Length and Timing Estimation by Customized Graph Neural Network	11
Detection of and Countermeasure Against Thermal Covert Channel in Many-Core Systems	11
Toward Hardware-Based IP Vulnerability Detection and Post-Deployment Patching in Systems-on-Chip	11
Exploiting Process Variations to Secure Photonic NoC Architectures From Snooping Attacks	11
OCC: An Automated End-to-End Machine Learning Optimizing Compiler for Computing-In-Memory	11
Development of Programmable Logic Array for Multiple-Valued Logic Functions	11
Grid-Based Framework for Routability Analysis and Diagnosis With Conditional Design Rules	11
Learning-Based Quality Management for Approximate Communication in Network-on-Chips	11
CAST: Content-Aware STT-MRAM Cache Write Management for Different Levels of Approximation	11
Contention Cognizant Scheduling of Task Graphs on Shared Bus-Based Heterogeneous Platforms	11
Checking Robustness Against EM Side-Channel Attacks Prior to Manufacturing	11