IEEE Transactions on Computer-Aided Design of Integrated Circuits and

Article	Citations
ACED-IT: Assuring Confidential Electronic Design Against Insider Threats in a Zero-Trust Environment	164
Pass/Fail Data for Logic Diagnosis Under Bounded Transparent Scan	119
Experimental Verification and Analysis of the Acceleration Factor Model for 3-D nand Flash Memory	105
Crosstalk-Aware Automatic Topology Customization and Optimization for Wavelength-Routed Optical NoCs	84
Via-Based Redistribution Layer Routing for InFO Packages With Irregular Pad Structures	68
Data Representation Aware of Damage to Extend the Lifetime of MLC NAND Flash Memory	65
Detecting Spoofed Noisy Speeches via Activation-Based Residual Blocks for Embedded Systems	62
A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead	61
Multimode Security-Aware Real-Time Scheduling on Multiprocessors	61
Cocktail: Mixing Data With Different Characteristics to Reduce Read Reclaims for nand Flash Memory	55
k-Degree Parallel Comparison-Free Hardware Sorter for Complete Sorting	55
Contamination-Aware Synthesis for Programmable Microfluidic Devices	55
Near-Free Lifetime Extension for 3-D nand Flash via Opportunistic Self-Healing	52
Defending Hardware-Based Malware Detectors Against Adversarial Attacks	51
A Style-Based Analog Layout Migration Technique With Complete Routing Behavior Preservation	51
Hardware-Enabled Efficient Data Processing With Tensor-Train Decomposition	50
HyperSpikeASIC: Accelerating Event-Based Workloads With HyperDimensional Computing and Spiking Neural Networks	49
Computing Execution Times With Execution Decision Diagrams in the Presence of Out-of-Order Resources	48
A Novel Read Scheme Using GIDL Current to Suppress Read Disturbance in 3-D nand Flash Memories	47
SparseACC: A Generalized Linear Model Accelerator for Sparse Datasets	44
Making the Most of Scarce Input Data in Deep Learning-Based Source Code Classification for Heterogeneous Device Mapping	43
AutoHoG: Automating Homomorphic Gate Design for Large-Scale Logic Circuit Evaluation	39
Adaptive Granularity Progressive LDPC Decoding for NAND Flash Memory	39
A New Pipelined Output Data Reducer of BOST for Improved Parallelism	38
Harmonia: A Unified Architecture for Efficient Deep Symbolic Regression	37

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	37
Table of Contents	36
Formal Verification of Integer Multiplier Circuits Using Binary Decision Diagrams	35
Reducing Transistor Count in CMOS Logic Design Through Clustering and Library-Independent Multiple-Output Logic Synthesis	35
GPCB Routing: Generative Pretrained Transformers-Based Printed Circuit Board Routing Method	34
An Optimization-Aware Pre-Routing Timing Prediction Framework Based on Multi-Modal Learning	34
Prism-SSD: A Flexible Storage Interface for SSDs	33
On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers	33
COMPACT: Flow-Based Computing on Nanoscale Crossbars With Minimal Semiperimeter and Maximum Dimension	31
General Purpose Deep Learning Accelerator Based on Bit Interleaving	31
A Space–Time Neural Network for Analysis of Stress Evolution Under DC Current Stressing	31
Toward an Analysable, Scalable, Energy-Efficient I/O Virtualization for Mixed-Criticality Systems	31
Code Synthesis for Dataflow-Based Embedded Software Design	30
SATA: Sparsity-Aware Training Accelerator for Spiking Neural Networks	29
Combating Stealthy Thermal Covert Channel Attack With Its Thermal Signal Transmitted in Direct Sequence Spread Spectrum	29
Eff-ECC: Protecting GPGPUs Register File With a Unified Energy-Efficient ECC Mechanism	29
Flex-SFU: Activation Function Acceleration with Non-Uniform Piecewise Approximation	29
Deeploy: Enabling Energy-Efficient Deployment of Small Language Models on Heterogeneous Microcontrollers	28
Reducing the CNOT Count for Clifford+T Circuits on NISQ Architectures	28
Exploring Bitslicing Architectures for Enabling FHE-Assisted Machine Learning	27
DCP-CNN: Efficient Acceleration of CNNs With Dynamic Computing Parallelism on FPGA	27
Circuit Topology-Aware Vaccination-Based Hardware Trojan Detection	27
Block Convolution: Toward Memory-Efficient Inference of Large-Scale CNNs on FPGA	27
RLPlace: Using Reinforcement Learning and Smart Perturbations to Optimize FPGA Placement	26
HotCluster: A Thermal-Aware Defect Recovery Method for Through-Silicon-Vias Toward Reliable 3-D ICs Systems	26
A Probabilistic Machine Learning Approach for the Uncertainty Quantification of Electronic Circuits Based on Gaussian Process Regression	25
RefSCAT: Formal Verification of Logic-Optimized Multipliers via Automated Reference Multiplier Generation and SCA-SAT Synergy	25
Practical Attacks on Deep Neural Networks by Memory Trojaning	25
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	24
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	24
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	24
2021 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 40	24
Keeping Deep Lithography Simulators Updated: Global–Local Shape-Based Novelty Detection and Active Learning	23
NC-Net: Efficient Neuromorphic Computing Using Aggregated Subnets on a Crossbar-Based Architecture With Nonvolatile Memory	23
Xplace: An Extremely Fast and Extensible Placement Framework	23
LoCoMOBO: A Local Constrained Multiobjective Bayesian Optimization for Analog Circuit Sizing	23
Efficient Sample Preparation With Fully Programmable Valve Arrays	23
PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced Nodes	23
Caphammer: Exploiting Capacitor Vulnerability of Energy Harvesting Systems	23
Robust Wafer Classification With Imperfectly Labeled Data Based on Self-Boosting Co-Teaching	23
Silicon-Proven ASIC Design for the Polynomial Operations of Fully Homomorphic Encryption	22
Design of Ultracompact Content Addressable Memory Exploiting 1T-1MTJ Cell	22
Direct Search Procedure for Functional Compaction With Improved Fault Coverage	22
SMT Solver With Hardware Acceleration	22
When Random Is Bad: Selective CRPs for Protecting PUFs Against Modeling Attacks	22
CKTSO: High-Performance Parallel Sparse Linear Solver for General Circuit Simulations	22
An Efficient Deep Learning Accelerator Architecture for Compressed Video Analysis	22
3D-ICE 3.0: Efficient Nonlinear MPSoC Thermal Simulation With Pluggable Heat Sink Models	21
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	21
Wrapping Paths of Undetected Transition Faults With Two-Cycle Gate-Exhaustive Faults	21

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	21
TaintLock: Hardware IP Protection Against Oracle-Guided and Oracle-Reconstruction Attacks	20
Accuracy-Based Hybrid Parasitic Capacitance Extraction Using Rule-Based, Neural-Networks, and Field-Solver Methods	20
LAHDC: Logic-Aggregation-Based Query for Embedded Hyperdimensional Computing Accelerator	20
On Modeling and Detecting Trojans in Instruction Sets	20
Approximate Conformance Checking for Closed-Loop Systems With Neural Network Controllers	20
CPU Address-Leakage Transient Execution Attack Detection and Its Countermeasures	20
Analytical Modeling of Multiple Co-Existing Inaccuracies in RF Controlling Circuits for Superconducting Quantum Computing	20
Adaptive Edge Offloading for Image Classification Under Rate Limit	19
Functionally Possible Scan-Based Test Set as a Dual of a Compressed Multicycle Test Set	19
Toward Minimum WCRT Bound for DAG Tasks Under Prioritized List Scheduling Algorithms	19
Delay Prediction for ASIC HLS: Comparing Graph-Based and Nongraph-Based Learning Models	19
FPGA Technology Mapping With Adaptive Gate Decomposition	19
Detecting Spoofed Speeches via Segment-Based Word CQCC and Average ZCR for Embedded Systems	19
A Low Latency and Compact GCD Design Using an Intelligent Seed-Selection Scheme of LL-PRNG	18
Real-Time Video Recognition via Decoder-Assisted Neural Network Acceleration Framework	18
Tail Latency Optimization for LDPC-Based High-Density and Low-Cost Flash Memory Devices	18
BLAST: Belling the Black-Hat High-Level Synthesis Tool	18
A Memristor Crossbar-Based Lyapunov Equation Solver	18
Development and Efficiency Analysis of a Switching Scheme for INL Reduction in Unary DACs	18
Efficient Identification of Undetectable Two-Cycle Gate-Exhaustive Faults	18
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	17
SoFI: Security Property-Driven Vulnerability Assessments of ICs Against Fault-Injection Attacks	17
Bulls-Eye: Active Few-Shot Learning Guided Logic Synthesis	17
MDD: A Unified Model-Driven Design Framework for Embedded Control Software	17
Clock-Gated Variable Frequency Signaling to Alleviate Power Supply Noise in a Packaged IC	17
Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review	17
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	17
FDAM: Filter-Dedicated Approximate Multiplier Design for Real-Time CNN Acceleration	17
Table of Contents	17
Model-to-Circuit Cross-Approximation For Printed Machine Learning Classifiers	17
ProVAT: An Automated Design and Analysis Framework for Process-Variation-Resilient Design of Silicon Photonic Microring Resonators	17
FLAM-PUF: A Response–Feedback-Based Lightweight Anti-Machine-Learning-Attack PUF	17
CaBaFL: Asynchronous Federated Learning via Hierarchical Cache and Feature Balance	17
K-SpecPart: Supervised Embedding Algorithms and Cut Overlay for Improved Hypergraph Partitioning	17
Similarity-Aware CNN for Efficient Video Recognition at the Edge	17
Partial Sum Quantization for Reducing ADC Size in ReRAM-Based Neural Network Accelerators	17
On-Chip Trust Evaluation Utilizing TDC-Based Parameter-Adjustable Security Primitive	17
Location-and-Preference Joint Prediction for Task Assignment in Spatial Crowdsourcing	16
RuleLearner: OPC Rule Extraction From Inverse Lithography Technique Engine	16
Tight Compression: Compressing CNN Through Fine-Grained Pruning and Weight Permutation for Efficient Implementation	16
Mapping Nearest Neighbor Compliant Quantum Circuits Onto a 2-D Hexagonal Architecture	16
CURIOUS: Efficient Neural Architecture Search Based on a Performance Predictor and Evolutionary Search	16
Glass Interposer Integration of Logic and Memory Chiplets: PPA and Power/Signal Integrity Benefits	16
Contention Cognizant Scheduling of Task Graphs on Shared Bus-Based Heterogeneous Platforms	16
QuantTPM: Efficient Mixed-Precision Quantization Framework for Tractable Probabilistic Models	16
Compiling All-Digital-Embedded Content Addressable Memories on Chip for Edge Application	16
PISOV: Physics-Informed Separation of Variables Solvers for Full-Chip Thermal Analysis	16
CTM-SRAF: Continuous Transmission Mask-Based Constraint-Aware Subresolution Assist Feature Generation	16
Cross-Domain Optimization of Low-Power Mixed-Signal Sensor Systems Under Classification Accuracy Constraints	16
Carry-Out Interference Optimization in WCRT Analysis for Global Fixed-Priority Multiprocessor Scheduling	15
Efficient Static-Driven Integration for Step-Function Transient Simulation	15
ACCURATE: Accuracy Maximization for Real-Time Multicore Systems With Energy-Efficient Way-Sharing Caches	15
NeRF-PIM: PIM Hardware-Software Co-Design of Neural Rendering Networks	15
ARMISTICE: Microarchitectural Leakage Modeling for Masked Software Formal Verification	15
VirSoC: Automatic Synthesis of Virtual System-on-Chip Environments	15
Vespa: Logic-Level Constraint-Based Validation for Continuous-Flow Microfluidic Devices	15
Information Leakage Analysis Using a Co-Design-Based Fault Injection Technique on a RISC-V Microprocessor	15
Harnessing Unipolar Threshold Switches for Enhanced Rectification	15
Energy-Efficient DNN Inference on Approximate Accelerators Through Formal Property Exploration	15
ARTEMIS: A Mixed Analog-Stochastic In-DRAM Accelerator for Transformer Neural Networks	15
Memristive Circuit Implementation of Context-Dependent Emotional Learning Network and Its Application in Multitask	15
CoaCAD: Correlation-Assisted Computer-Aided Design for Nonvolatile FPGAs	15
A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking	15
Through the Looking Glass: Automated Design Understanding of SystemC-Based VPs at the ESL	15
Achievable-Rate-Aware Retention-Error Correction for Multi-Level-Cell NAND Flash Memory	15
Online Reset for Signal Temporal Logic Monitoring	15
CHEF: A Framework for Deploying Heterogeneous Models on Clusters With Heterogeneous FPGAs	15
Aging Effects on Template Attacks Launched on Dual-Rail Protected Chips	15
PASS: Pattern-Sequence-Authentication-Based Secure Scan Against Reverse Engineering Attacks	15
Clock-Latency-Aware Fault-Tolerant DLL for Multi-Die Clock Synchronization	14
High-Precision Short-Term Lifetime Prediction in TLC 3-D NAND Flash Memory as Hot-Data Storage	14
A Hybrid Test Scheme for Automotive IC in Multisite Testing	14
A Data-Driven Stochastic Memristor Model for Integrated Circuit Simulation	14
Table of Contents	14
Fair-ZNS: Enhancing Fairness in ZNS SSDs Through Self-Balancing I/O Scheduling	14
Mixed-Criticality Scheduling Upon Permitted Failure Probability and Dynamic Priority	14
VirtualSync+: Timing Optimization With Virtual Synchronization	14
A Highly Compressed Accelerator With Temporal Optical Flow Feature Fusion and Tensorized LSTM for Video Action Recognition on Terminal Device	14
Hierarchical Mapping of Large-Scale Spiking Convolutional Neural Networks Onto Resource-Constrained Neuromorphic Processor	14

SeFAct2: Selective Feature Activation for Energy-Efficient CNNs Using Optimized Thresholds	14
Generalized Affine Equivalence Checking of Boolean Functions via Reachability Analysis	14
A Parameter Extraction Method for LC Circuit of DB-BPF Based on Fully Connected Network	14
Multi-Corner Timing Macro Modeling With Neural Collaborative Filtering From Recommendation Systems Perspective	14
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	14
A Compact Gated-Synapse Model for Neuromorphic Circuits	13
A Low-Power Variation-Tolerant 7T SRAM With Enhanced Read Sensing Margin for Voltage Scaling	13
RTeX: An Efficient and Timing-Predictable Multithreaded Executor for ROS 2	13
Improved EM Side-Channel Analysis Attack Probe Detection Range Utilizing Coplanar Capacitive Asymmetry Sensing	13
GEAR: Graph-Evolving Aware Data Arranger to Enhance the Performance of Traversing Evolving Graphs on SCM	13
Large Data Transfer Optimization for Improved Robustness in Real-Time V2X-Communication	13
Burst Automaton: Framework for Speed-Independent Synthesis Using Burst-Mode Specifications	13
Flexible Generation of Fast and Accurate Software Performance Simulators From Compact Processor Descriptions	13
Nested Speculative Execution Attacks via Runahead	13
Accelerating Real-Valued FFT on CPU-FPGA Platforms	13
A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs	13
A Hybrid-Grained Remapping Defense Scheme Against Hard Failures for Row-Column-NVM	13
Digitally Assisted Mixed-Signal Circuit Security	13
NoCFuzzer: Automating NoC Verification in UVM	13
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	13
Efficient Design Optimization for Diffractive Deep Neural Networks	13
MLogNet: A Logarithmic Quantization-Based Accelerator for Depthwise Separable Convolution	13
Hierarchical Model Checking of SystemVerilog-Specified Asynchronous Circuits for Deadlock Detection	13
Multiplication Through a Single Look-Up-Table (LUT) in CNN Inference Computation	13
Data-Driven Feature Selection Framework for Approximate Circuit Design	13
Modeling and Analysis of the LatestTime Message Synchronization Policy in ROS	13
HALTRAV: Design of A High-performance and Area-efficient Latch with Triple-node-upset Recovery and Algorithm-based Verifications	13
On Development of Reliable Machine Learning Systems Based on Machine Error Tolerance of Input Images	13
MiniControl 2.0: Co-Synthesis of Flow and Control Layers for Microfluidic Biochips With Strictly Constrained Control Ports	13
An LDE-Aware g m /I D -Based Hybri	12
Quantized Neural Network Synthesis for Direct Logic Circuit Implementation	12
CDAR-DRAM: Enabling Runtime DRAM Performance and Energy Optimization via In-Situ Charge Detection and Adaptive Data Restoration	12
CKFO: Convolution Kernel First Operated Algorithm With Applications in Memristor-Based Convolutional Neural Network	12
Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICs	12
Correlated Bayesian Model Fusion: Efficient High-Dimensional Performance Modeling of Analog/RF Integrated Circuits Over Multiple Corners	12
Varying Periods of In-Field Testing With Storage and Counter Based Logic Built-In Self-Test	12
Delaying Crash Consistency for Building A High-Performance Persistent Memory File System	12
OpeNPDN: A Neural-Network-Based Framework for Power Delivery Network Synthesis	12
On Legalization of Die Bonding Bumps and Pads for 3-D ICs	12
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	12
High-Performance Accurate and Approximate Multipliers for FPGA-Based Hardware Accelerators	12
PASGCN: An ReRAM-Based PIM Design for GCN With Adaptively Sparsified Graphs	12
NV-APP: Invalid Programming Performance Improved No-Verify and Adaptive Pulse Programming Scheme for 3D QLC NAND Flash	12
INCAME: Interruptible CNN Accelerator for Multirobot Exploration	12
An Efficient Bit-Sparse DNN Accelerator Exploiting Adaptive Bit-Serial Computations	12
A Universal RRAM-Based DNN Accelerator With Programmable Crossbars Beyond MVM Operator	12
Methodology for Distributed-ROM-Based Implementation of Finite State Machines	12
Toward the Predictability of Dynamic Real-Time DNN Inference	11
PTPS: Precision-Aware Task Partitioning and Scheduling for SpMV on CPU-FPGA Heterogeneous Platforms	11
Mosaic-3C1S: A Low Overhead Crosstalk Suppression Scheme for Rectangular TSV Array	11
A Flexible Yet Efficient DNN Pruning Approach for Crossbar-Based Processing-in-Memory Architectures	11
Optimizing Data Reuse for Loop Mapping on CGRAs With Joint Affine and Nonaffine Transformations	11
Table of Contents	11
Knowledge-Intensive Diagnostics Using Case-Based Reasoning and Synthetic Case Generation	11
Assessing the Potential of Escalating RowHammer Attack Distance to Bypass-Counter-Based Defenses	11
PcGC: A Parity-Check Garbage Collection for Boosting 3-D NAND Flash Performance	11
ELight: Toward Efficient and Aging-Resilient Photonic In-Memory Neurocomputing	11
Energy-Efficient DNN Inferencing on ReRAM-Based PIM Accelerators Using Heterogeneous Operation Units	11
Counteracting Adversarial Attacks in Autonomous Driving	11
Toward Fully Automated Machine Learning for Routability Estimator Development	11
ILRM: Imitation Learning Based Resource Management for Integrated CPU-GPU Edge Systems With Renewable Energy Sources	11
Toward Write Optimization for Skyrmion Racetrack Memory by Skyrmion Repermutation	11
Flexible Inverse Design of Microwave Filter Customized on Demand With Wavelet Transform Deep Learning	11
RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique	11
Table of contents	11
An MILP Encoding for Efficient Verification of Quantized Deep Neural Networks	11
Reducing SRAM Reading Power With Column Data Segment and Weights Correlation Enhancement for CNN Processing	11
Unleashing the Potential of Sparse DNNs Through Synergistic Hardware-Sparsity Co-Design	11
A Recursion and Lock Free GPU-Based Logic Rewriting Framework Exploiting Both Intranode and Internode Parallelism	11
FS-TRA: Evaluating Sequential Circuit Reliability via a Fanout-Source Tracking and Reduction Approach	11
System-on-Chip Information Flow Validation Under Asynchronous Resets	11
Toward Critical Flip-Flop Identification for Soft-Error Tolerance With Graph Neural Networks	11
Security-Driven Placement and Routing Tools for Electromagnetic Side-Channel Protection	11
ATOM: An Automatic Topology Synthesis Framework for Operational Amplifiers	11
Closed-Form Capacitance Network Compact Model and Monte Carlo Analysis of the GIDL Assisted Potential Growth in 3 D NAND Flash String	11
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Publication Information	11
Quantifying Information Leakage for Security Verification of Compiler Optimizations	11
Search-Free Inference Acceleration for Sparse Convolutional Neural Networks	11
FlexFL: Heterogeneous Federated Learning via APoZ-Guided Flexible Pruning in Uncertain Scenarios	11
A Comprehensive Evaluation of Integrated Circuits Side-Channel Resilience Utilizing Three-Independent-Gate Silicon Nanowire Field Effect Transistors-Based Current Mode Logic	11
Test Generation for Functionally Possible Subpaths	11
Table of Contents	10
Minimum Unit Capacitance Calculation for Capacitor Arrays in Binary-Weighted and Split DACs	10
A Lightweight Full Entropy TRNG With On-Chip Entropy Assurance	10
Acceleration-Aware Fine-Grained Channel Pruning for Deep Neural Networks via Residual Gating	10
Fast Energy-Optimal Multikernel DNN-Like Application Allocation on Multi-FPGA Platforms	10
LithoHoD: A Litho Simulator-Powered Framework for IC Layout Hotspot Detection	10
Techniques to Improve Write and Retention Reliability of STT-MRAM Memory Subsystem	10
Multielectrostatic FPGA Placement Considering SLICEL–SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization	10
Equivalence Checking of Sequential Quantum Circuits	10
Circuit Partitioning and Transmission Cost Optimization in Distributed Quantum Circuits	10
VIGILANT: Vulnerability Detection Tool Against Fault-Injection Attacks for Locking Techniques	10
Silicon Modeling of Spiking Neurons With Diverse Dynamic Behaviors	10
QANS: Toward Quantized Neural Network Adversarial Noise Suppression	10
Reduced-Pin-Count BOST for Test-Cost Reduction	10