IEEE Transactions on Computer-Aided Design of Integrated Circuits and

Article	Citations
Table of Contents	209
Reducing Transistor Count in CMOS Logic Design Through Clustering and Library-Independent Multiple-Output Logic Synthesis	124
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	105
Formal Verification of Integer Multiplier Circuits Using Binary Decision Diagrams	87
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	86
A Style-Based Analog Layout Migration Technique With Complete Routing Behavior Preservation	81
HyperSpikeASIC: Accelerating Event-Based Workloads With HyperDimensional Computing and Spiking Neural Networks	76
A Novel Read Scheme Using GIDL Current to Suppress Read Disturbance in 3-D nand Flash Memories	74
SparseACC: A Generalized Linear Model Accelerator for Sparse Datasets	68
A New Pipelined Output Data Reducer of BOST for Improved Parallelism	67
Harmonia: A Unified Architecture for Efficient Deep Symbolic Regression	66
Pass/Fail Data for Logic Diagnosis Under Bounded Transparent Scan	65
Data Representation Aware of Damage to Extend the Lifetime of MLC NAND Flash Memory	60
Detecting Spoofed Noisy Speeches via Activation-Based Residual Blocks for Embedded Systems	57
Multimode Security-Aware Real-Time Scheduling on Multiprocessors	52
HotCluster: A Thermal-Aware Defect Recovery Method for Through-Silicon-Vias Toward Reliable 3-D ICs Systems	49
Near-Free Lifetime Extension for 3-D nand Flash via Opportunistic Self-Healing	49
Experimental Verification and Analysis of the Acceleration Factor Model for 3-D nand Flash Memory	49
Adaptive Granularity Progressive LDPC Decoding for NAND Flash Memory	46
AutoHoG: Automating Homomorphic Gate Design for Large-Scale Logic Circuit Evaluation	46
A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead	44
Circuit Topology-Aware Vaccination-Based Hardware Trojan Detection	43
An Optimization-Aware Prerouting Timing Prediction Framework Based on Multimodal Learning	43
Reducing the CNOT Count for Clifford+T Circuits on NISQ Architectures	42
Block Convolution: Toward Memory-Efficient Inference of Large-Scale CNNs on FPGA	42

RLPlace: Using Reinforcement Learning and Smart Perturbations to Optimize FPGA Placement	41
A Probabilistic Machine Learning Approach for the Uncertainty Quantification of Electronic Circuits Based on Gaussian Process Regression	41
Combating Stealthy Thermal Covert Channel Attack With Its Thermal Signal Transmitted in Direct Sequence Spread Spectrum	40
On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers	39
Cocktail: Mixing Data With Different Characteristics to Reduce Read Reclaims for nand Flash Memory	39
ESFA: An Efficient Scalable FFT Design Framework on Versal AI Engine	38
COMPACT: Flow-Based Computing on Nanoscale Crossbars With Minimal Semiperimeter and Maximum Dimension	38
Multicycle Tests for Functionally Possible Two-Cycle Gate-Exhaustive Faults	38
Frequency Domain Modeling of Interconnects Based on Assemble Neural Network for 3D Integration	38
Prism-SSD: A Flexible Storage Interface for SSDs	37
k-Degree Parallel Comparison-Free Hardware Sorter for Complete Sorting	36
Eff-ECC: Protecting GPGPUs Register File With a Unified Energy-Efficient ECC Mechanism	36
Code Synthesis for Dataflow-Based Embedded Software Design	36
A Space–Time Neural Network for Analysis of Stress Evolution Under DC Current Stressing	36
Crosstalk-Aware Automatic Topology Customization and Optimization for Wavelength-Routed Optical NoCs	35
Contamination-Aware Synthesis for Programmable Microfluidic Devices	35
Exploring Bitslicing Architectures for Enabling FHE-Assisted Machine Learning	34
General Purpose Deep Learning Accelerator Based on Bit Interleaving	34
ACED-IT: Assuring Confidential Electronic Design Against Insider Threats in a Zero-Trust Environment	33
Via-Based Redistribution Layer Routing for InFO Packages With Irregular Pad Structures	32
Toward an Analysable, Scalable, Energy-Efficient I/O Virtualization for Mixed-Criticality Systems	32
Hardware-Enabled Efficient Data Processing With Tensor-Train Decomposition	31
GPCB Routing: Generative Pretrained Transformers-Based Printed Circuit Board Routing Method	31
DCP-CNN: Efficient Acceleration of CNNs With Dynamic Computing Parallelism on FPGA	30
Computing Execution Times With Execution Decision Diagrams in the Presence of Out-of-Order Resources	30
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	30
Making the Most of Scarce Input Data in Deep Learning-Based Source Code Classification for Heterogeneous Device Mapping	29
Flex-SFU: Activation Function Acceleration With Nonuniform Piecewise Approximation	29
RefSCAT: Formal Verification of Logic-Optimized Multipliers via Automated Reference Multiplier Generation and SCA-SAT Synergy	29
Deeploy: Enabling Energy-Efficient Deployment of Small Language Models on Heterogeneous Microcontrollers	29
SATA: Sparsity-Aware Training Accelerator for Spiking Neural Networks	29
2021 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 40	28
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	28
FPGA Technology Mapping With Adaptive Gate Decomposition	27
Silicon-Proven ASIC Design for the Polynomial Operations of Fully Homomorphic Encryption	27
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	27
A Low Latency and Compact GCD Design Using an Intelligent Seed-Selection Scheme of LL-PRNG	27
On Modeling and Detecting Trojans in Instruction Sets	27
HeteroQNN: Enabling Distributed QNN under Heterogeneous Quantum Devices	27
FedMT: Multi-Task Federated Learning with Competitive GPU Resource Sharing	27
Partial Sum Quantization for Reducing ADC Size in ReRAM-Based Neural Network Accelerators	27
Keeping Deep Lithography Simulators Updated: Global–Local Shape-Based Novelty Detection and Active Learning	27
Robust Wafer Classification With Imperfectly Labeled Data Based on Self-Boosting Co-Teaching	27
ProVAT: An Automated Design and Analysis Framework for Process-Variation-Resilient Design of Silicon Photonic Microring Resonators	27
CaBaFL: Asynchronous Federated Learning via Hierarchical Cache and Feature Balance	26
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	26
Real-Time Video Recognition via Decoder-Assisted Neural Network Acceleration Framework	26
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	26
CKTSO: High-Performance Parallel Sparse Linear Solver for General Circuit Simulations	25
Direct Search Procedure for Functional Compaction With Improved Fault Coverage	25

Analytical Modeling of Multiple Co-Existing Inaccuracies in RF Controlling Circuits for Superconducting Quantum Computing	25
NC-Net: Efficient Neuromorphic Computing Using Aggregated Subnets on a Crossbar-Based Architecture With Nonvolatile Memory	25
Wrapping Paths of Undetected Transition Faults With Two-Cycle Gate-Exhaustive Faults	25
Functionally Possible Scan-Based Test Set as a Dual of a Compressed Multicycle Test Set	25
DAGSIS: A DAG-Aware MAGIC based Synthesis Framework for In-Memory Computing	25
SMT Solver With Hardware Acceleration	25
Detecting Spoofed Speeches via Segment-Based Word CQCC and Average ZCR for Embedded Systems	25
An Efficient Deep Learning Accelerator Architecture for Compressed Video Analysis	24
Efficient Identification of Undetectable Two-Cycle Gate-Exhaustive Faults	24
LAHDC: Logic-Aggregation-Based Query for Embedded Hyperdimensional Computing Accelerator	24
Development and Efficiency Analysis of a Switching Scheme for INL Reduction in Unary DACs	24
CPU Address-Leakage Transient Execution Attack Detection and Its Countermeasures	24
Efficient Sample Preparation With Fully Programmable Valve Arrays	23
Toward Minimum WCRT Bound for DAG Tasks Under Prioritized List Scheduling Algorithms	23
TaintLock: Hardware IP Protection Against Oracle-Guided and Oracle-Reconstruction Attacks	23
When Random Is Bad: Selective CRPs for Protecting PUFs Against Modeling Attacks	23
Design of Ultracompact Content Addressable Memory Exploiting 1T-1MTJ Cell	23
Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review	23
Caphammer: Exploiting Capacitor Vulnerability of Energy Harvesting Systems	23
BLAST: Belling the Black-Hat High-Level Synthesis Tool	22
Accuracy-Based Hybrid Parasitic Capacitance Extraction Using Rule-Based, Neural-Networks, and Field-Solver Methods	22
LoCoMOBO: A Local Constrained Multiobjective Bayesian Optimization for Analog Circuit Sizing	22
Xplace: An Extremely Fast and Extensible Placement Framework	22
Delay Prediction for ASIC HLS: Comparing Graph-Based and Nongraph-Based Learning Models	22
Tail Latency Optimization for LDPC-Based High-Density and Low-Cost Flash Memory Devices	22
3D-ICE 3.0: Efficient Nonlinear MPSoC Thermal Simulation With Pluggable Heat Sink Models	22
Approximate Conformance Checking for Closed-Loop Systems With Neural Network Controllers	21
Clock-Gated Variable Frequency Signaling to Alleviate Power Supply Noise in a Packaged IC	21
PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced Nodes	21
A Memristor Crossbar-Based Lyapunov Equation Solver	21
Adaptive Edge Offloading for Image Classification Under Rate Limit	21
FLAM-PUF: A Response–Feedback-Based Lightweight Anti-Machine-Learning-Attack PUF	21
DASA: Distribution-Aware Sparse Attention for Accelerating Diffusion Transformer	21
Cross-Domain Optimization of Low-Power Mixed-Signal Sensor Systems Under Classification Accuracy Constraints	20
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	20
Glass Interposer Integration of Logic and Memory Chiplets: PPA and Power/Signal Integrity Benefits	20
PISOV: Physics-Informed Separation of Variables Solvers for Full-Chip Thermal Analysis	20
RuleLearner: OPC Rule Extraction From Inverse Lithography Technique Engine	20
Similarity-Aware CNN for Efficient Video Recognition at the Edge	20
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	20
Table of Contents	20
A Data-Driven Stochastic Memristor Model for Integrated Circuit Simulation	19
MarchGen: A March Sequence Generation Method for Faults with Arbitrary Number of Operations in RAMs	19
ACCURATE: Accuracy Maximization for Real-Time Multicore Systems With Energy-Efficient Way-Sharing Caches	19
Aging Effects on Template Attacks Launched on Dual-Rail Protected Chips	19
PASS: Pattern-Sequence-Authentication-Based Secure Scan Against Reverse Engineering Attacks	19
Efficient Static-Driven Integration for Step-Function Transient Simulation	19
Online Reset for Signal Temporal Logic Monitoring	19
Mixed-Criticality Scheduling Upon Permitted Failure Probability and Dynamic Priority	19
Division-Free Four-Way Toom-Cook Polynomial Multiplication Architecture for Large Integer Arithmetic on FPGAs and ASICs	19
K-SpecPart: Supervised Embedding Algorithms and Cut Overlay for Improved Hypergraph Partitioning	19
Information Leakage Analysis Using a Co-Design-Based Fault Injection Technique on a RISC-V Microprocessor	19
Model-to-Circuit Cross-Approximation For Printed Machine Learning Classifiers	19
Achievable-Rate-Aware Retention-Error Correction for Multi-Level-Cell NAND Flash Memory	19
Fama : An FPGA-Oriented Multi-Scalar Multiplication Accelerator Optimized via Algorithm-Hardware Co-Design	19
A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking	19
Computational Performance Bounds Prediction in Quantum Computing With Unstable Noise	19
Carry-Out Interference Optimization in WCRT Analysis for Global Fixed-Priority Multiprocessor Scheduling	19
Lightweight Failure Prediction Algorithms Based on Internal Characteristics of 3D NAND Flash Memory	19
NeRF-PIM: PIM Hardware-Software Co-Design of Neural Rendering Networks	19
Clock-Latency-Aware Fault-Tolerant DLL for Multi-Die Clock Synchronization	18
Generalized Affine Equivalence Checking of Boolean Functions via Reachability Analysis	18
AnaCraft: Duel-Play Probabilistic-Model-based Reinforcement Learning for Sample-Efficient PVT-Robust Analog Circuit Sizing Optimization	18
VirtualSync+: Timing Optimization With Virtual Synchronization	18
Modern Automatic PCB Placement with Complex Constraints	18
High-Precision Short-Term Lifetime Prediction in TLC 3-D NAND Flash Memory as Hot-Data Storage	18
CHEF: A Framework for Deploying Heterogeneous Models on Clusters With Heterogeneous FPGAs	18
Multi-Corner Timing Macro Modeling With Neural Collaborative Filtering From Recommendation Systems Perspective	18
Energy-Efficient DNN Inference on Approximate Accelerators Through Formal Property Exploration	18
CoaCAD: Correlation-Assisted Computer-Aided Design for Nonvolatile FPGAs	17
Mapping Nearest Neighbor Compliant Quantum Circuits Onto a 2-D Hexagonal Architecture	17
Vespa: Logic-Level Constraint-Based Validation for Continuous-Flow Microfluidic Devices	17
Contention Cognizant Scheduling of Task Graphs on Shared Bus-Based Heterogeneous Platforms	17
QuantTPM: Efficient Mixed-Precision Quantization Framework for Tractable Probabilistic Models	17
Hierarchical Mapping of Large-Scale Spiking Convolutional Neural Networks Onto Resource-Constrained Neuromorphic Processor	17
Harnessing Unipolar Threshold Switches for Enhanced Rectification	17
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	17
Modular Functional Test Sequences for Test Compaction	17
Bulls-Eye: Active Few-Shot Learning Guided Logic Synthesis	17
CURIOUS: Efficient Neural Architecture Search Based on a Performance Predictor and Evolutionary Search	17

VirSoC: Automatic Synthesis of Virtual System-on-Chip Environments	17
Through the Looking Glass: Automated Design Understanding of SystemC-Based VPs at the ESL	17
TroLL: Exploiting Structural Similarities between Logic Locking and Hardware Trojans	17
Hardware Security Meets Incomplete Netlists: Insights into Trojan Detection via Structural Reasoning	16
MDD: A Unified Model-Driven Design Framework for Embedded Control Software	16
Fair-ZNS: Enhancing Fairness in ZNS SSDs Through Self-Balancing I/O Scheduling	16
Approximate Logic Synthesis for Dot-Inverter Graphs Using Node Merging-enhanced Genetic Algorithm-based Approach	16
Tight Compression: Compressing CNN Through Fine-Grained Pruning and Weight Permutation for Efficient Implementation	16
FDAM: Filter-Dedicated Approximate Multiplier Design for Real-Time CNN Acceleration	16
Memristive Circuit Implementation of Context-Dependent Emotional Learning Network and Its Application in Multitask	16
ARMISTICE: Microarchitectural Leakage Modeling for Masked Software Formal Verification	16
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	16
A Hybrid Test Scheme for Automotive IC in Multisite Testing	16
SoFI: Security Property-Driven Vulnerability Assessments of ICs Against Fault-Injection Attacks	16
CirOPT : Towards Effective Combinational Equivalence Checking via Compiler Optimization	16
CTM-SRAF: Continuous Transmission Mask-Based Constraint-Aware Subresolution Assist Feature Generation	16
ARTEMIS: A Mixed Analog-Stochastic In-DRAM Accelerator for Transformer Neural Networks	16
Compiling All-Digital-Embedded Content Addressable Memories on Chip for Edge Application	16
A Parameter Extraction Method for LC Circuit of DB-BPF Based on Fully Connected Network	16
Location-and-Preference Joint Prediction for Task Assignment in Spatial Crowdsourcing	16
A Highly Compressed Accelerator With Temporal Optical Flow Feature Fusion and Tensorized LSTM for Video Action Recognition on Terminal Device	16
Flexible Generation of Fast and Accurate Software Performance Simulators From Compact Processor Descriptions	15
GEAR: Graph-Evolving Aware Data Arranger to Enhance the Performance of Traversing Evolving Graphs on SCM	15
A Hybrid-Grained Remapping Defense Scheme Against Hard Failures for Row-Column-NVM	15
CDAR-DRAM: Enabling Runtime DRAM Performance and Energy Optimization via In-Situ Charge Detection and Adaptive Data Restoration	15
Modeling and Analysis of the LatestTime Message Synchronization Policy in ROS	15
Data-Driven Feature Selection Framework for Approximate Circuit Design	15
Table of Contents	15
Efficient Design Optimization for Diffractive Deep Neural Networks	15
Multi-Objective Coverage Optimization for 3D Heterogeneous Wireless Sensor Networks	15
Burst Automaton: Framework for Speed-Independent Synthesis Using Burst-Mode Specifications	15
Hardware Accelerator for Short-Read DNA Sequence Alignment Using Burrows-Wheeler Transformation	15
Improved EM Side-Channel Analysis Attack Probe Detection Range Utilizing Coplanar Capacitive Asymmetry Sensing	15
On Development of Reliable Machine Learning Systems Based on Machine Error Tolerance of Input Images	15
Large Data Transfer Optimization for Improved Robustness in Real-Time V2X-Communication	15
ParaVOM: Parallel-Execution-Aware Validation and Optimization for Multilayered Continuous-Flow Microfluidic Biochips	15
Methodology for Distributed-ROM-Based Implementation of Finite State Machines	15
RTeX: An Efficient and Timing-Predictable Multithreaded Executor for ROS 2	15
Delaying Crash Consistency for Building A High-Performance Persistent Memory File System	14
A Novel MDM-Based Optical Networks-on-Chip With Reliability Analysis	14
DH-PIM: Maximizing Computing Unit Utilization in Digital PIM by Dual Half Mode Extension	14
Quantized Neural Network Synthesis for Direct Logic Circuit Implementation	14
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	14
Varying Periods of In-Field Testing With Storage- and Counter-Based Logic Built-In Self-Test	14
NV-APP: Invalid Programming Performance Improved No-Verify and Adaptive Pulse Programming Scheme for 3-D QLC nand Flash	14
Knowledge-Intensive Diagnostics Using Case-Based Reasoning and Synthetic Case Generation	14
A Universal RRAM-Based DNN Accelerator With Programmable Crossbars Beyond MVM Operator	14
HALTRAV: Design of a High-Performance and Area-Efficient Latch With Triple-Node-Upset Recovery and Algorithm-Based Verifications	14
Digitally Assisted Mixed-Signal Circuit Security	14
An MILP Encoding for Efficient Verification of Quantized Deep Neural Networks	14
Accelerating Real-Valued FFT on CPU-FPGA Platforms	14
On Legalization of Die Bonding Bumps and Pads for 3-D ICs	14
MiniControl 2.0: Co-Synthesis of Flow and Control Layers for Microfluidic Biochips With Strictly Constrained Control Ports	14
MLogNet: A Logarithmic Quantization-Based Accelerator for Depthwise Separable Convolution	14
Correlated Bayesian Model Fusion: Efficient High-Dimensional Performance Modeling of Analog/RF Integrated Circuits Over Multiple Corners	14
Hierarchical Model Checking of SystemVerilog-Specified Asynchronous Circuits for Deadlock Detection	14
Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICs	14
Nested Speculative Execution Attacks via Runahead	14
NoCFuzzer: Automating NoC Verification in UVM	14
A Low-Power Variation-Tolerant 7T SRAM With Enhanced Read Sensing Margin for Voltage Scaling	14
Multiplication Through a Single Look-Up-Table (LUT) in CNN Inference Computation	14
Closed-Form Capacitance Network Compact Model and Monte Carlo Analysis of the GIDL-Assisted Potential Growth in 3-D NAND Flash String	13
A Flexible Yet Efficient DNN Pruning Approach for Crossbar-Based Processing-in-Memory Architectures	13
Test Generation for Functionally Possible Subpaths	13
Unleashing the Potential of Sparse DNNs Through Synergistic Hardware-Sparsity Co-Design	13
Reducing SRAM Reading Power With Column Data Segment and Weights Correlation Enhancement for CNN Processing	13
Assessing the Potential of Escalating RowHammer Attack Distance to Bypass-Counter-Based Defenses	13
AsyncGrid: An Intra- and Inter-Layer Asynchronous Hybrid Parallelism System for Responsive Edge LLM Inference	13
INCAME: Interruptible CNN Accelerator for Multirobot Exploration	13
An Efficient Bit-Sparse DNN Accelerator Exploiting Adaptive Bit-Serial Computations	13
A Comprehensive Evaluation of Integrated Circuits Side-Channel Resilience Utilizing Three-Independent-Gate Silicon Nanowire Field Effect Transistors-Based Current Mode Logic	13
Table of Contents	13
LightNAS: On Lightweight and Scalable Neural Architecture Search for Embedded Platforms	13
ELight: Toward Efficient and Aging-Resilient Photonic In-Memory Neurocomputing	13
High-Performance Accurate and Approximate Multipliers for FPGA-Based Hardware Accelerators	13
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Publication Information	13
OpeNPDN: A Neural-Network-Based Framework for Power Delivery Network Synthesis	13
A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs	13
Toward Fully Automated Machine Learning for Routability Estimator Development	13
FS-TRA: Evaluating Sequential Circuit Reliability via a Fanout-Source Tracking and Reduction Approach	13
A Recursion and Lock Free GPU-Based Logic Rewriting Framework Exploiting Both Intranode and Internode Parallelism	13
Quantifying Information Leakage for Security Verification of Compiler Optimizations	13
Counteracting Adversarial Attacks in Autonomous Driving	13
ATOM: An Automatic Topology Synthesis Framework for Operational Amplifiers	13
Table of contents	13
PASGCN: An ReRAM-Based PIM Design for GCN With Adaptively Sparsified Graphs	13
Search-Free Inference Acceleration for Sparse Convolutional Neural Networks	13
CNN-Oriented Placement Algorithm for High-Performance Accelerators on Rad-Hard FPGAs	12
Optimizing Data Reuse for Loop Mapping on CGRAs With Joint Affine and Nonaffine Transformations	12
FlexFL: Heterogeneous Federated Learning via APoZ-Guided Flexible Pruning in Uncertain Scenarios	12
Efficient Cartesian Genetic Programming-Based Automatic Synthesis Framework for Reversible Quantum-Flux-Parametron Logic Circuits	12
ViA: A Novel Vision-Transformer Accelerator Based on FPGA	12
A Comprehensive Dataflow-Mapping Optimization for Fully Pipelined Execution in Spatial Programmable Architecture	12
A Q-Learning-Based Display Energy Optimization Scheme for Android Systems	12
Improving Transformer Inference Through Optimized Nonlinear Operations With Quantization-Approximation-Based Strategy	12