IEEE Transactions on Computer-Aided Design of Integrated Circuits and

Article	Citations
Pass/Fail Data for Logic Diagnosis Under Bounded Transparent Scan	192
Data Representation Aware of Damage to Extend the Lifetime of MLC NAND Flash Memory	120
Detecting Spoofed Noisy Speeches via Activation-Based Residual Blocks for Embedded Systems	97
Multimode Security-Aware Real-Time Scheduling on Multiprocessors	81
Near-Free Lifetime Extension for 3-D nand Flash via Opportunistic Self-Healing	79
A Style-Based Analog Layout Migration Technique With Complete Routing Behavior Preservation	74
HyperSpikeASIC: Accelerating Event-Based Workloads With HyperDimensional Computing and Spiking Neural Networks	70
SparseACC: A Generalized Linear Model Accelerator for Sparse Datasets	67
A Novel Read Scheme Using GIDL Current to Suppress Read Disturbance in 3-D nand Flash Memories	67
A New Pipelined Output Data Reducer of BOST for Improved Parallelism	61
Making the Most of Scarce Input Data in Deep Learning-Based Source Code Classification for Heterogeneous Device Mapping	61
Harmonia: A Unified Architecture for Efficient Deep Symbolic Regression	59
Table of Contents	55
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	55
Formal Verification of Integer Multiplier Circuits Using Binary Decision Diagrams	52
Prism-SSD: A Flexible Storage Interface for SSDs	51
AutoHoG: Automating Homomorphic Gate Design for Large-Scale Logic Circuit Evaluation	47
GPCB Routing: Generative Pretrained Transformers-Based Printed Circuit Board Routing Method	46
A Probabilistic Machine Learning Approach for the Uncertainty Quantification of Electronic Circuits Based on Gaussian Process Regression	45
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	44
An Optimization-Aware Pre-Routing Timing Prediction Framework Based on Multi-Modal Learning	43
Block Convolution: Toward Memory-Efficient Inference of Large-Scale CNNs on FPGA	43
DCP-CNN: Efficient Acceleration of CNNs With Dynamic Computing Parallelism on FPGA	42
k-Degree Parallel Comparison-Free Hardware Sorter for Complete Sorting	42
Code Synthesis for Dataflow-Based Embedded Software Design	40

Exploring Bitslicing Architectures for Enabling FHE-Assisted Machine Learning	37
General Purpose Deep Learning Accelerator Based on Bit Interleaving	37
Eff-ECC: Protecting GPGPUs Register File With a Unified Energy-Efficient ECC Mechanism	37
Computing Execution Times With Execution Decision Diagrams in the Presence of Out-of-Order Resources	37
RefSCAT: Formal Verification of Logic-Optimized Multipliers via Automated Reference Multiplier Generation and SCA-SAT Synergy	37
Cocktail: Mixing Data With Different Characteristics to Reduce Read Reclaims for nand Flash Memory	37
A Space–Time Neural Network for Analysis of Stress Evolution Under DC Current Stressing	37
Defending Hardware-Based Malware Detectors Against Adversarial Attacks	35
Via-Based Redistribution Layer Routing for InFO Packages With Irregular Pad Structures	35
ACED-IT: Assuring Confidential Electronic Design Against Insider Threats in a Zero-Trust Environment	34
Experimental Verification and Analysis of the Acceleration Factor Model for 3-D nand Flash Memory	34
SATA: Sparsity-Aware Training Accelerator for Spiking Neural Networks	34
A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead	33
Adaptive Granularity Progressive LDPC Decoding for NAND Flash Memory	33
Combating Stealthy Thermal Covert Channel Attack With Its Thermal Signal Transmitted in Direct Sequence Spread Spectrum	32
Reducing Transistor Count in CMOS Logic Design Through Clustering and Library-Independent Multiple-Output Logic Synthesis	32
Hardware-Enabled Efficient Data Processing With Tensor-Train Decomposition	32
On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers	32
Toward an Analysable, Scalable, Energy-Efficient I/O Virtualization for Mixed-Criticality Systems	31
HotCluster: A Thermal-Aware Defect Recovery Method for Through-Silicon-Vias Toward Reliable 3-D ICs Systems	31
Circuit Topology-Aware Vaccination-Based Hardware Trojan Detection	31
Crosstalk-Aware Automatic Topology Customization and Optimization for Wavelength-Routed Optical NoCs	30
RLPlace: Using Reinforcement Learning and Smart Perturbations to Optimize FPGA Placement	29
Deeploy: Enabling Energy-Efficient Deployment of Small Language Models on Heterogeneous Microcontrollers	29
Contamination-Aware Synthesis for Programmable Microfluidic Devices	29
Flex-SFU: Activation Function Acceleration with Non-Uniform Piecewise Approximation	28
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	27
COMPACT: Flow-Based Computing on Nanoscale Crossbars With Minimal Semiperimeter and Maximum Dimension	27
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	27
Reducing the CNOT Count for Clifford+T Circuits on NISQ Architectures	27
2021 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 40	26
Efficient Sample Preparation With Fully Programmable Valve Arrays	26
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	26
Xplace: An Extremely Fast and Extensible Placement Framework	26
NC-Net: Efficient Neuromorphic Computing Using Aggregated Subnets on a Crossbar-Based Architecture With Nonvolatile Memory	26
SMT Solver With Hardware Acceleration	26
Design of Ultracompact Content Addressable Memory Exploiting 1T-1MTJ Cell	25
Direct Search Procedure for Functional Compaction With Improved Fault Coverage	25
Real-Time Video Recognition via Decoder-Assisted Neural Network Acceleration Framework	25
CKTSO: High-Performance Parallel Sparse Linear Solver for General Circuit Simulations	25
Toward Minimum WCRT Bound for DAG Tasks Under Prioritized List Scheduling Algorithms	24
Accuracy-Based Hybrid Parasitic Capacitance Extraction Using Rule-Based, Neural-Networks, and Field-Solver Methods	24
DAGSIS: A DAG-Aware MAGIC based Synthesis Framework for In-Memory Computing	24
HeteroQNN: Enabling Distributed QNN under Heterogeneous Quantum Devices	23
FLAM-PUF: A Response–Feedback-Based Lightweight Anti-Machine-Learning-Attack PUF	23
BLAST: Belling the Black-Hat High-Level Synthesis Tool	23
CaBaFL: Asynchronous Federated Learning via Hierarchical Cache and Feature Balance	23
LoCoMOBO: A Local Constrained Multiobjective Bayesian Optimization for Analog Circuit Sizing	23
Adaptive Edge Offloading for Image Classification Under Rate Limit	23
Tail Latency Optimization for LDPC-Based High-Density and Low-Cost Flash Memory Devices	22

An Efficient Deep Learning Accelerator Architecture for Compressed Video Analysis	22
Wrapping Paths of Undetected Transition Faults With Two-Cycle Gate-Exhaustive Faults	22
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	22
Analytical Modeling of Multiple Co-Existing Inaccuracies in RF Controlling Circuits for Superconducting Quantum Computing	22
FedMT: Multi-Task Federated Learning with Competitive GPU Resource Sharing	22
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	22
TaintLock: Hardware IP Protection Against Oracle-Guided and Oracle-Reconstruction Attacks	22
LAHDC: Logic-Aggregation-Based Query for Embedded Hyperdimensional Computing Accelerator	21
Detecting Spoofed Speeches via Segment-Based Word CQCC and Average ZCR for Embedded Systems	21
Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review	21
Functionally Possible Scan-Based Test Set as a Dual of a Compressed Multicycle Test Set	21
Clock-Gated Variable Frequency Signaling to Alleviate Power Supply Noise in a Packaged IC	21
Partial Sum Quantization for Reducing ADC Size in ReRAM-Based Neural Network Accelerators	21
Development and Efficiency Analysis of a Switching Scheme for INL Reduction in Unary DACs	21
CPU Address-Leakage Transient Execution Attack Detection and Its Countermeasures	21
Efficient Identification of Undetectable Two-Cycle Gate-Exhaustive Faults	21
When Random Is Bad: Selective CRPs for Protecting PUFs Against Modeling Attacks	21
Robust Wafer Classification With Imperfectly Labeled Data Based on Self-Boosting Co-Teaching	20
ProVAT: An Automated Design and Analysis Framework for Process-Variation-Resilient Design of Silicon Photonic Microring Resonators	20
A Memristor Crossbar-Based Lyapunov Equation Solver	20
Keeping Deep Lithography Simulators Updated: Global–Local Shape-Based Novelty Detection and Active Learning	20
Glass Interposer Integration of Logic and Memory Chiplets: PPA and Power/Signal Integrity Benefits	19
On Modeling and Detecting Trojans in Instruction Sets	19
A Low Latency and Compact GCD Design Using an Intelligent Seed-Selection Scheme of LL-PRNG	19
Caphammer: Exploiting Capacitor Vulnerability of Energy Harvesting Systems	19
Table of Contents	19
Similarity-Aware CNN for Efficient Video Recognition at the Edge	19
Silicon-Proven ASIC Design for the Polynomial Operations of Fully Homomorphic Encryption	19
On-Chip Trust Evaluation Utilizing TDC-Based Parameter-Adjustable Security Primitive	19
3D-ICE 3.0: Efficient Nonlinear MPSoC Thermal Simulation With Pluggable Heat Sink Models	19
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	19
MDD: A Unified Model-Driven Design Framework for Embedded Control Software	19
FDAM: Filter-Dedicated Approximate Multiplier Design for Real-Time CNN Acceleration	19
FPGA Technology Mapping With Adaptive Gate Decomposition	19
Delay Prediction for ASIC HLS: Comparing Graph-Based and Nongraph-Based Learning Models	19
Approximate Conformance Checking for Closed-Loop Systems With Neural Network Controllers	19
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	19
PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced Nodes	19
Cross-Domain Optimization of Low-Power Mixed-Signal Sensor Systems Under Classification Accuracy Constraints	18
Mapping Nearest Neighbor Compliant Quantum Circuits Onto a 2-D Hexagonal Architecture	18
VirSoC: Automatic Synthesis of Virtual System-on-Chip Environments	18
A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking	18
PISOV: Physics-Informed Separation of Variables Solvers for Full-Chip Thermal Analysis	18
CTM-SRAF: Continuous Transmission Mask-Based Constraint-Aware Subresolution Assist Feature Generation	18
Tight Compression: Compressing CNN Through Fine-Grained Pruning and Weight Permutation for Efficient Implementation	18
CoaCAD: Correlation-Assisted Computer-Aided Design for Nonvolatile FPGAs	18
RuleLearner: OPC Rule Extraction From Inverse Lithography Technique Engine	18
ARMISTICE: Microarchitectural Leakage Modeling for Masked Software Formal Verification	18
Harnessing Unipolar Threshold Switches for Enhanced Rectification	18
Vespa: Logic-Level Constraint-Based Validation for Continuous-Flow Microfluidic Devices	18
K-SpecPart: Supervised Embedding Algorithms and Cut Overlay for Improved Hypergraph Partitioning	17
Mixed-Criticality Scheduling Upon Permitted Failure Probability and Dynamic Priority	17
Achievable-Rate-Aware Retention-Error Correction for Multi-Level-Cell NAND Flash Memory	17
CHEF: A Framework for Deploying Heterogeneous Models on Clusters With Heterogeneous FPGAs	17
VirtualSync+: Timing Optimization With Virtual Synchronization	17
Through the Looking Glass: Automated Design Understanding of SystemC-Based VPs at the ESL	17
Clock-Latency-Aware Fault-Tolerant DLL for Multi-Die Clock Synchronization	17
ACCURATE: Accuracy Maximization for Real-Time Multicore Systems With Energy-Efficient Way-Sharing Caches	17
Generalized Affine Equivalence Checking of Boolean Functions via Reachability Analysis	17
Multi-Corner Timing Macro Modeling With Neural Collaborative Filtering From Recommendation Systems Perspective	17
Contention Cognizant Scheduling of Task Graphs on Shared Bus-Based Heterogeneous Platforms	17
Information Leakage Analysis Using a Co-Design-Based Fault Injection Technique on a RISC-V Microprocessor	17
NeRF-PIM: PIM Hardware-Software Co-Design of Neural Rendering Networks	17
Efficient Static-Driven Integration for Step-Function Transient Simulation	17
PASS: Pattern-Sequence-Authentication-Based Secure Scan Against Reverse Engineering Attacks	16
Model-to-Circuit Cross-Approximation For Printed Machine Learning Classifiers	16
Bulls-Eye: Active Few-Shot Learning Guided Logic Synthesis	16
Aging Effects on Template Attacks Launched on Dual-Rail Protected Chips	16
Lightweight Failure Prediction Algorithms Based on Internal Characteristics of 3D NAND Flash Memory	16
Modular Functional Test Sequences for Test Compaction	16
AnaCraft: Duel-Play Probabilistic-Model-based Reinforcement Learning for Sample-Efficient PVT-Robust Analog Circuit Sizing Optimization	16
Compiling All-Digital-Embedded Content Addressable Memories on Chip for Edge Application	16
Computational Performance Bounds Prediction in Quantum Computing With Unstable Noise	16
Carry-Out Interference Optimization in WCRT Analysis for Global Fixed-Priority Multiprocessor Scheduling	16
A Hybrid Test Scheme for Automotive IC in Multisite Testing	16
Energy-Efficient DNN Inference on Approximate Accelerators Through Formal Property Exploration	16
ARTEMIS: A Mixed Analog-Stochastic In-DRAM Accelerator for Transformer Neural Networks	16
A Data-Driven Stochastic Memristor Model for Integrated Circuit Simulation	16
A Highly Compressed Accelerator With Temporal Optical Flow Feature Fusion and Tensorized LSTM for Video Action Recognition on Terminal Device	16
Location-and-Preference Joint Prediction for Task Assignment in Spatial Crowdsourcing	15

Online Reset for Signal Temporal Logic Monitoring	15
CURIOUS: Efficient Neural Architecture Search Based on a Performance Predictor and Evolutionary Search	15
Memristive Circuit Implementation of Context-Dependent Emotional Learning Network and Its Application in Multitask	15
Fair-ZNS: Enhancing Fairness in ZNS SSDs Through Self-Balancing I/O Scheduling	15
High-Precision Short-Term Lifetime Prediction in TLC 3-D NAND Flash Memory as Hot-Data Storage	15
Table of Contents	15
TroLL: Exploiting Structural Similarities between Logic Locking and Hardware Trojans	15
QuantTPM: Efficient Mixed-Precision Quantization Framework for Tractable Probabilistic Models	15
Approximate Logic Synthesis for Dot-Inverter Graphs Using Node Merging-enhanced Genetic Algorithm-based Approach	15
Hierarchical Mapping of Large-Scale Spiking Convolutional Neural Networks Onto Resource-Constrained Neuromorphic Processor	15
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	15
SoFI: Security Property-Driven Vulnerability Assessments of ICs Against Fault-Injection Attacks	15
A Parameter Extraction Method for LC Circuit of DB-BPF Based on Fully Connected Network	15
A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs	14
Improved EM Side-Channel Analysis Attack Probe Detection Range Utilizing Coplanar Capacitive Asymmetry Sensing	14
Multi-Objective Coverage Optimization for 3D Heterogeneous Wireless Sensor Networks	14
NoCFuzzer: Automating NoC Verification in UVM	14
An Efficient Bit-Sparse DNN Accelerator Exploiting Adaptive Bit-Serial Computations	14
ParaVOM: Parallel-Execution-Aware Validation and Optimization for Multilayered Continuous-Flow Microfluidic Biochips	14
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	14
Digitally Assisted Mixed-Signal Circuit Security	14
MLogNet: A Logarithmic Quantization-Based Accelerator for Depthwise Separable Convolution	14
A Hybrid-Grained Remapping Defense Scheme Against Hard Failures for Row-Column-NVM	14
Flexible Generation of Fast and Accurate Software Performance Simulators From Compact Processor Descriptions	14
Methodology for Distributed-ROM-Based Implementation of Finite State Machines	14
On Development of Reliable Machine Learning Systems Based on Machine Error Tolerance of Input Images	14
A Universal RRAM-Based DNN Accelerator With Programmable Crossbars Beyond MVM Operator	14
Large Data Transfer Optimization for Improved Robustness in Real-Time V2X-Communication	14
PASGCN: An ReRAM-Based PIM Design for GCN With Adaptively Sparsified Graphs	14
RTeX: An Efficient and Timing-Predictable Multithreaded Executor for ROS 2	14
Data-Driven Feature Selection Framework for Approximate Circuit Design	14
Modeling and Analysis of the LatestTime Message Synchronization Policy in ROS	14
GEAR: Graph-Evolving Aware Data Arranger to Enhance the Performance of Traversing Evolving Graphs on SCM	14
Burst Automaton: Framework for Speed-Independent Synthesis Using Burst-Mode Specifications	14
Efficient Design Optimization for Diffractive Deep Neural Networks	14
OpeNPDN: A Neural-Network-Based Framework for Power Delivery Network Synthesis	14
CDAR-DRAM: Enabling Runtime DRAM Performance and Energy Optimization via In-Situ Charge Detection and Adaptive Data Restoration	14
Quantized Neural Network Synthesis for Direct Logic Circuit Implementation	14
Correlated Bayesian Model Fusion: Efficient High-Dimensional Performance Modeling of Analog/RF Integrated Circuits Over Multiple Corners	13
Hardware Accelerator for Short-Read DNA Sequence Alignment Using Burrows-Wheeler Transformation	13
DH-PIM: Maximizing Computing Unit Utilization in Digital PIM by Dual Half Mode Extension	13
HALTRAV: Design of a High-Performance and Area-Efficient Latch With Triple-Node-Upset Recovery and Algorithm-Based Verifications	13
Accelerating Real-Valued FFT on CPU-FPGA Platforms	13
Varying Periods of In-Field Testing With Storage- and Counter-Based Logic Built-In Self-Test	13
Nested Speculative Execution Attacks via Runahead	13
INCAME: Interruptible CNN Accelerator for Multirobot Exploration	13
Delaying Crash Consistency for Building A High-Performance Persistent Memory File System	13
A Low-Power Variation-Tolerant 7T SRAM With Enhanced Read Sensing Margin for Voltage Scaling	13
A Compact Gated-Synapse Model for Neuromorphic Circuits	13
Closed-Form Capacitance Network Compact Model and Monte Carlo Analysis of the GIDL Assisted Potential Growth in 3 D NAND Flash String	13
Hierarchical Model Checking of SystemVerilog-Specified Asynchronous Circuits for Deadlock Detection	13
An MILP Encoding for Efficient Verification of Quantized Deep Neural Networks	13
PTPS: Precision-Aware Task Partitioning and Scheduling for SpMV on CPU-FPGA Heterogeneous Platforms	12
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Publication Information	12
NV-APP: Invalid Programming Performance Improved No-Verify and Adaptive Pulse Programming Scheme for 3-D QLC nand Flash	12
Knowledge-Intensive Diagnostics Using Case-Based Reasoning and Synthetic Case Generation	12
Quantifying Information Leakage for Security Verification of Compiler Optimizations	12
Low-Cost Shuffling Countermeasures Against Side-Channel Attacks for NTT-Based Post-Quantum Cryptography	12
Real-Time 3-D Thermal Simulation of Advanced Packages via Generative Adversarial Networks	12
ELight: Toward Efficient and Aging-Resilient Photonic In-Memory Neurocomputing	12
Test Generation for Functionally Possible Subpaths	12
Search-Free Inference Acceleration for Sparse Convolutional Neural Networks	12
High-Performance Accurate and Approximate Multipliers for FPGA-Based Hardware Accelerators	12
Assessing the Potential of Escalating RowHammer Attack Distance to Bypass-Counter-Based Defenses	12
Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICs	12
MiniControl 2.0: Co-Synthesis of Flow and Control Layers for Microfluidic Biochips With Strictly Constrained Control Ports	12
ATOM: An Automatic Topology Synthesis Framework for Operational Amplifiers	12
Table of contents	12
Electrothermal Simulation and Optimal Design of Thermoelectric Cooler Using Analytical Approach	12
Reducing SRAM Reading Power With Column Data Segment and Weights Correlation Enhancement for CNN Processing	12
A Flexible Yet Efficient DNN Pruning Approach for Crossbar-Based Processing-in-Memory Architectures	12
Toward the Predictability of Dynamic Real-Time DNN Inference	12
Counteracting Adversarial Attacks in Autonomous Driving	12
Optimizing Data Reuse for Loop Mapping on CGRAs With Joint Affine and Nonaffine Transformations	12
Table of Contents	12
Multiplication Through a Single Look-Up-Table (LUT) in CNN Inference Computation	12
A Novel MDM-Based Optical Networks-on-Chip With Reliability Analysis	12
On Legalization of Die Bonding Bumps and Pads for 3-D ICs	12
A Recursion and Lock Free GPU-Based Logic Rewriting Framework Exploiting Both Intranode and Internode Parallelism	12
Toward Critical Flip-Flop Identification for Soft-Error Tolerance With Graph Neural Networks	12
Unleashing the Potential of Sparse DNNs Through Synergistic Hardware-Sparsity Co-Design	12
A Comprehensive Evaluation of Integrated Circuits Side-Channel Resilience Utilizing Three-Independent-Gate Silicon Nanowire Field Effect Transistors-Based Current Mode Logic	12
Toward Fully Automated Machine Learning for Routability Estimator Development	12
Mosaic-3C1S: A Low Overhead Crosstalk Suppression Scheme for Rectangular TSV Array	11
Automated Topology Synthesis of Analog Integrated Circuits With Frequency Compensation	11
System-on-Chip Information Flow Validation Under Asynchronous Resets	11
Toward Write Optimization for Skyrmion Racetrack Memory by Skyrmion Repermutation	11
A Photonic Interconnect Enabling Cross-Layer Scheduling for Chiplet-Based DNN Accelerators	11
CMD: A Cache-Assisted GPU Memory Deduplication Architecture	11
ViA: A Novel Vision-Transformer Accelerator Based on FPGA	11
SNAS: Fast Hardware-Aware Neural Architecture Search Methodology	11
Improving Transformer Inference Through Optimized Nonlinear Operations With Quantization-Approximation-Based Strategy	11
ILRM: Imitation Learning-Based Resource Management for Integrated CPU–GPU Edge Systems With Renewable Energy Sources	11
Minimum Unit Capacitance Calculation for Capacitor Arrays in Binary-Weighted and Split DACs	11
FS-TRA: Evaluating Sequential Circuit Reliability via a Fanout-Source Tracking and Reduction Approach	11