IEEE Transactions on Computer-Aided Design of Integrated Circuits and

Article	Citations
Table of Contents	130
Reducing Transistor Count in CMOS Logic Design Through Clustering and Library-Independent Multiple-Output Logic Synthesis	110
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	96
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	94
A Novel Read Scheme Using GIDL Current to Suppress Read Disturbance in 3-D nand Flash Memories	93
SparseACC: A Generalized Linear Model Accelerator for Sparse Datasets	87
Pass/Fail Data for Logic Diagnosis Under Bounded Transparent Scan	82
Data Representation Aware of Damage to Extend the Lifetime of MLC NAND Flash Memory	81
Detecting Spoofed Noisy Speeches via Activation-Based Residual Blocks for Embedded Systems	72
Multimode Security-Aware Real-Time Scheduling on Multiprocessors	70
Near-Free Lifetime Extension for 3-D nand Flash via Opportunistic Self-Healing	68
Hardware-Enabled Efficient Data Processing With Tensor-Train Decomposition	60
Computing Execution Times With Execution Decision Diagrams in the Presence of Out-of-Order Resources	60
Toward an Analysable, Scalable, Energy-Efficient I/O Virtualization for Mixed-Criticality Systems	59
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	57
A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead	55
ACED-IT: Assuring Confidential Electronic Design Against Insider Threats in a Zero-Trust Environment	53
Combating Stealthy Thermal Covert Channel Attack With Its Thermal Signal Transmitted in Direct Sequence Spread Spectrum	52
Multicycle Tests for Functionally Possible Two-Cycle Gate-Exhaustive Faults	50
ESFA: An Efficient Scalable FFT Design Framework on Versal AI Engine	48
VersaAccel: A Versatile Configurable Accelerator for Diverse Sparse-Dense Matrix Operators	47
Frequency Domain Modeling of Interconnects Based on Assemble Neural Network for 3D Integration	47
Prism-SSD: A Flexible Storage Interface for SSDs	47
COMPACT: Flow-Based Computing on Nanoscale Crossbars With Minimal Semiperimeter and Maximum Dimension	47
Experimental Verification and Analysis of the Acceleration Factor Model for 3-D nand Flash Memory	44

HyperSpikeASIC: Accelerating Event-Based Workloads With HyperDimensional Computing and Spiking Neural Networks	44
Code Synthesis for Dataflow-Based Embedded Software Design	43
Crosstalk-Aware Automatic Topology Customization and Optimization for Wavelength-Routed Optical NoCs	42
k-Degree Parallel Comparison-Free Hardware Sorter for Complete Sorting	42
Contamination-Aware Synthesis for Programmable Microfluidic Devices	42
General Purpose Deep Learning Accelerator Based on Bit Interleaving	41
Via-Based Redistribution Layer Routing for InFO Packages With Irregular Pad Structures	40
Exploring Bitslicing Architectures for Enabling FHE-Assisted Machine Learning	40
Adaptive Granularity Progressive LDPC Decoding for NAND Flash Memory	39
Block Convolution: Toward Memory-Efficient Inference of Large-Scale CNNs on FPGA	39
Reducing the CNOT Count for Clifford+T Circuits on NISQ Architectures	39
Harmonia : A Unified Architecture for Efficient Deep Symbolic Regression	38
Eff-ECC: Protecting GPGPUs Register File With a Unified Energy-Efficient ECC Mechanism	38
A New Pipelined Output Data Reducer of BOST for Improved Parallelism	38
Flex-SFU: Activation Function Acceleration With Nonuniform Piecewise Approximation	37
A Space–Time Neural Network for Analysis of Stress Evolution Under DC Current Stressing	36
AutoHoG: Automating Homomorphic Gate Design for Large-Scale Logic Circuit Evaluation	35
Cocktail: Mixing Data With Different Characteristics to Reduce Read Reclaims for nand Flash Memory	34
Deeploy: Enabling Energy-Efficient Deployment of Small Language Models on Heterogeneous Microcontrollers	34
Formal Verification of Integer Multiplier Circuits Using Binary Decision Diagrams	34
RLPlace: Using Reinforcement Learning and Smart Perturbations to Optimize FPGA Placement	33
Making the Most of Scarce Input Data in Deep Learning-Based Source Code Classification for Heterogeneous Device Mapping	33
RefSCAT: Formal Verification of Logic-Optimized Multipliers via Automated Reference Multiplier Generation and SCA-SAT Synergy	33
SATA: Sparsity-Aware Training Accelerator for Spiking Neural Networks	33
An Optimization-Aware Prerouting Timing Prediction Framework Based on Multimodal Learning	32
A Probabilistic Machine Learning Approach for the Uncertainty Quantification of Electronic Circuits Based on Gaussian Process Regression	32
GPCB Routing: Generative Pretrained Transformers-Based Printed Circuit Board Routing Method	32
Circuit Topology-Aware Vaccination-Based Hardware Trojan Detection	32
HotCluster: A Thermal-Aware Defect Recovery Method for Through-Silicon-Vias Toward Reliable 3-D ICs Systems	31
DCP-CNN: Efficient Acceleration of CNNs With Dynamic Computing Parallelism on FPGA	31
Partial Sum Quantization for Reducing ADC Size in ReRAM-Based Neural Network Accelerators	30
On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers	30
On Modeling and Detecting Trojans in Instruction Sets	30
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	30
FPGA Technology Mapping With Adaptive Gate Decomposition	30
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	30
Keeping Deep Lithography Simulators Updated: Global–Local Shape-Based Novelty Detection and Active Learning	30
Crosstalk Analysis and Advancements in RDL Interposer Design for High-Speed Channels	29
Silicon-Proven ASIC Design for the Polynomial Operations of Fully Homomorphic Encryption	29
Tail Latency Optimization for LDPC-Based High-Density and Low-Cost Flash Memory Devices	29
Development and Efficiency Analysis of a Switching Scheme for INL Reduction in Unary DACs	29
Robust Wafer Classification With Imperfectly Labeled Data Based on Self-Boosting Co-Teaching	28
CKTSO: High-Performance Parallel Sparse Linear Solver for General Circuit Simulations	28
Adaptive Edge Offloading for Image Classification Under Rate Limit	28
LoCoMOBO: A Local Constrained Multiobjective Bayesian Optimization for Analog Circuit Sizing	28
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	27
A Low Latency and Compact GCD Design Using an Intelligent Seed-Selection Scheme of LL-PRNG	27
FedMT: Multi-Task Federated Learning with Competitive GPU Resource Sharing	27
3D-ICE 3.0: Efficient Nonlinear MPSoC Thermal Simulation With Pluggable Heat Sink Models	27
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	27

HeteroQNN: Enabling Distributed QNN under Heterogeneous Quantum Devices	27
A Memristor Crossbar-Based Lyapunov Equation Solver	27
SMT Solver With Hardware Acceleration	26
DAGSIS: A DAG-Aware MAGIC based Synthesis Framework for In-Memory Computing	26
Efficient Identification of Undetectable Two-Cycle Gate-Exhaustive Faults	26
Real-Time Video Recognition via Decoder-Assisted Neural Network Acceleration Framework	26
DASA: Distribution-Aware Sparse Attention for Accelerating Diffusion Transformer	26
Wrapping Paths of Undetected Transition Faults With Two-Cycle Gate-Exhaustive Faults	26
Analytical Modeling of Multiple Co-Existing Inaccuracies in RF Controlling Circuits for Superconducting Quantum Computing	26
CaBaFL: Asynchronous Federated Learning via Hierarchical Cache and Feature Balance	26
PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced Nodes	26
Functionally Possible Scan-Based Test Set as a Dual of a Compressed Multicycle Test Set	26
CPU Address-Leakage Transient Execution Attack Detection and Its Countermeasures	25
Delay Prediction for ASIC HLS: Comparing Graph-Based and Nongraph-Based Learning Models	25
When Random Is Bad: Selective CRPs for Protecting PUFs Against Modeling Attacks	25
BLAST: Belling the Black-Hat High-Level Synthesis Tool	25
Efficient Sample Preparation With Fully Programmable Valve Arrays	25
Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review	24
Direct Search Procedure for Functional Compaction With Improved Fault Coverage	24
A Markov-Chain Based PUF Using Chain-Block-Obfuscation Mechanism Resisting Machine Learning Attacks with High Uniformity Robustness	24
NC-Net: Efficient Neuromorphic Computing Using Aggregated Subnets on a Crossbar-Based Architecture With Nonvolatile Memory	24
LAHDC: Logic-Aggregation-Based Query for Embedded Hyperdimensional Computing Accelerator	24
ProVAT: An Automated Design and Analysis Framework for Process-Variation-Resilient Design of Silicon Photonic Microring Resonators	23
Design of Ultracompact Content Addressable Memory Exploiting 1T-1MTJ Cell	23
TRAGIC: Test Oracle Generation for ISA Compliance Testing via Large Language Model	23
Hierarchical-ISA Supporting Row-wise Operands for Efficient DNN Computation	23
Approximate Conformance Checking for Closed-Loop Systems With Neural Network Controllers	23
Comparing Methods for the Cross-Level Verification of SystemC Peripherals with Symbolic Execution	22
Detecting Spoofed Speeches via Segment-Based Word CQCC and Average ZCR for Embedded Systems	22
Accuracy-Based Hybrid Parasitic Capacitance Extraction Using Rule-Based, Neural-Networks, and Field-Solver Methods	22
Clock-Gated Variable Frequency Signaling to Alleviate Power Supply Noise in a Packaged IC	22
TaintLock: Hardware IP Protection Against Oracle-Guided and Oracle-Reconstruction Attacks	22
Toward Minimum WCRT Bound for DAG Tasks Under Prioritized List Scheduling Algorithms	22
FLAM-PUF: A Response–Feedback-Based Lightweight Anti-Machine-Learning-Attack PUF	22
An Efficient Deep Learning Accelerator Architecture for Compressed Video Analysis	22
Caphammer: Exploiting Capacitor Vulnerability of Energy Harvesting Systems	22
Xplace: An Extremely Fast and Extensible Placement Framework	22
Cross-Domain Optimization of Low-Power Mixed-Signal Sensor Systems Under Classification Accuracy Constraints	21
Table of Contents	21
MarchGen: A March Sequence Generation Method for Faults with Arbitrary Number of Operations in RAMs	21
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	21
Mixed-Criticality Scheduling Upon Permitted Failure Probability and Dynamic Priority	21
Division-Free Four-Way Toom-Cook Polynomial Multiplication Architecture for Large Integer Arithmetic on FPGAs and ASICs	21
Similarity-Aware CNN for Efficient Video Recognition at the Edge	21
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	21
Fama : An FPGA-Oriented Multi-Scalar Multiplication Accelerator Optimized via Algorithm-Hardware Co-Design	21
Information Leakage Analysis Using a Co-Design-Based Fault Injection Technique on a RISC-V Microprocessor	20
NeRF-PIM: PIM Hardware-Software Co-Design of Neural Rendering Networks	20
VirtualSync+: Timing Optimization With Virtual Synchronization	20
ACCURATE: Accuracy Maximization for Real-Time Multicore Systems With Energy-Efficient Way-Sharing Caches	20
Computational Performance Bounds Prediction in Quantum Computing With Unstable Noise	20
Generalized Affine Equivalence Checking of Boolean Functions via Reachability Analysis	20
CHEF: A Framework for Deploying Heterogeneous Models on Clusters With Heterogeneous FPGAs	20
Efficient Static-Driven Integration for Step-Function Transient Simulation	20
A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking	20
Aging Effects on Template Attacks Launched on Dual-Rail Protected Chips	20
Achievable-Rate-Aware Retention-Error Correction for Multi-Level-Cell NAND Flash Memory	20
Clock-Latency-Aware Fault-Tolerant DLL for Multi-Die Clock Synchronization	20
Lightweight Failure Prediction Algorithms Based on Internal Characteristics of 3D NAND Flash Memory	20
K-SpecPart: Supervised Embedding Algorithms and Cut Overlay for Improved Hypergraph Partitioning	20
Harnessing Unipolar Threshold Switches for Enhanced Rectification	19
Hierarchical Mapping of Large-Scale Spiking Convolutional Neural Networks Onto Resource-Constrained Neuromorphic Processor	19
VirSoC: Automatic Synthesis of Virtual System-on-Chip Environments	19
Through the Looking Glass: Automated Design Understanding of SystemC-Based VPs at the ESL	19
QuantTPM: Efficient Mixed-Precision Quantization Framework for Tractable Probabilistic Models	19
Multi-Corner Timing Macro Modeling With Neural Collaborative Filtering From Recommendation Systems Perspective	19
A Highly Compressed Accelerator With Temporal Optical Flow Feature Fusion and Tensorized LSTM for Video Action Recognition on Terminal Device	19
A Parameter Extraction Method for LC Circuit of DB-BPF Based on Fully Connected Network	19
Modular Functional Test Sequences for Test Compaction	19
CoaCAD: Correlation-Assisted Computer-Aided Design for Nonvolatile FPGAs	19
Modern Automatic PCB Placement with Complex Constraints	19
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	19
Vespa: Logic-Level Constraint-Based Validation for Continuous-Flow Microfluidic Devices	19
TroLL: Exploiting Structural Similarities between Logic Locking and Hardware Trojans	19
Location-and-Preference Joint Prediction for Task Assignment in Spatial Crowdsourcing	18
Fair-ZNS: Enhancing Fairness in ZNS SSDs Through Self-Balancing I/O Scheduling	18
ARTEMIS: A Mixed Analog-Stochastic In-DRAM Accelerator for Transformer Neural Networks	18
Bulls-Eye: Active Few-Shot Learning Guided Logic Synthesis	18
CirOPT : Towards Effective Combinational Equivalence Checking via Compiler Optimization	18
Carry-Out Interference Optimization in WCRT Analysis for Global Fixed-Priority Multiprocessor Scheduling	18

Approximate Logic Synthesis for Dot-Inverter Graphs Using Node Merging-enhanced Genetic Algorithm-based Approach	18
A Data-Driven Stochastic Memristor Model for Integrated Circuit Simulation	18
Hardware Security Meets Incomplete Netlists: Insights into Trojan Detection via Structural Reasoning	18
High-Precision Short-Term Lifetime Prediction in TLC 3-D NAND Flash Memory as Hot-Data Storage	18
Contention Cognizant Scheduling of Task Graphs on Shared Bus-Based Heterogeneous Platforms	17
CTM-SRAF: Continuous Transmission Mask-Based Constraint-Aware Subresolution Assist Feature Generation	17
RuleLearner: OPC Rule Extraction From Inverse Lithography Technique Engine	17
PISOV: Physics-Informed Separation of Variables Solvers for Full-Chip Thermal Analysis	17
AnaCraft: Duel-Play Probabilistic-Model-based Reinforcement Learning for Sample-Efficient PVT-Robust Analog Circuit Sizing Optimization	17
Mapping Nearest Neighbor Compliant Quantum Circuits Onto a 2-D Hexagonal Architecture	17
A Hybrid Test Scheme for Automotive IC in Multisite Testing	17
Compiling All-Digital-Embedded Content Addressable Memories on Chip for Edge Application	17
MDD: A Unified Model-Driven Design Framework for Embedded Control Software	17
PASS: Pattern-Sequence-Authentication-Based Secure Scan Against Reverse Engineering Attacks	17
Glass Interposer Integration of Logic and Memory Chiplets: PPA and Power/Signal Integrity Benefits	17
SoFI: Security Property-Driven Vulnerability Assessments of ICs Against Fault-Injection Attacks	17
ARMISTICE: Microarchitectural Leakage Modeling for Masked Software Formal Verification	17
CURIOUS: Efficient Neural Architecture Search Based on a Performance Predictor and Evolutionary Search	17
Model-to-Circuit Cross-Approximation For Printed Machine Learning Classifiers	17
Energy-Efficient DNN Inference on Approximate Accelerators Through Formal Property Exploration	17
FDAM: Filter-Dedicated Approximate Multiplier Design for Real-Time CNN Acceleration	17
Memristive Circuit Implementation of Context-Dependent Emotional Learning Network and Its Application in Multitask	17
Tight Compression: Compressing CNN Through Fine-Grained Pruning and Weight Permutation for Efficient Implementation	17
Modeling and Analysis of the LatestTime Message Synchronization Policy in ROS	16
Nested Speculative Execution Attacks via Runahead	16
Online Reset for Signal Temporal Logic Monitoring	16
GEAR: Graph-Evolving Aware Data Arranger to Enhance the Performance of Traversing Evolving Graphs on SCM	16
Data-Driven Feature Selection Framework for Approximate Circuit Design	16
ParaVOM: Parallel-Execution-Aware Validation and Optimization for Multilayered Continuous-Flow Microfluidic Biochips	16
Hardware Accelerator for Short-Read DNA Sequence Alignment Using Burrows-Wheeler Transformation	16
An MILP Encoding for Efficient Verification of Quantized Deep Neural Networks	16
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	16
Large Data Transfer Optimization for Improved Robustness in Real-Time V2X-Communication	16
On Development of Reliable Machine Learning Systems Based on Machine Error Tolerance of Input Images	16
Burst Automaton: Framework for Speed-Independent Synthesis Using Burst-Mode Specifications	16
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	16
Improved EM Side-Channel Analysis Attack Probe Detection Range Utilizing Coplanar Capacitive Asymmetry Sensing	16
Table of Contents	16
Flexible Generation of Fast and Accurate Software Performance Simulators From Compact Processor Descriptions	16
A Hybrid-Grained Remapping Defense Scheme Against Hard Failures for Row-Column-NVM	16
Accelerating Real-Valued FFT on CPU-FPGA Platforms	15
Hierarchical Model Checking of SystemVerilog-Specified Asynchronous Circuits for Deadlock Detection	15
PASGCN: An ReRAM-Based PIM Design for GCN With Adaptively Sparsified Graphs	15
RTeX: An Efficient and Timing-Predictable Multithreaded Executor for ROS 2	15
NoCFuzzer: Automating NoC Verification in UVM	15
MLogNet: A Logarithmic Quantization-Based Accelerator for Depthwise Separable Convolution	15
A Universal RRAM-Based DNN Accelerator With Programmable Crossbars Beyond MVM Operator	15
Quantized Neural Network Synthesis for Direct Logic Circuit Implementation	15
A Low-Power Variation-Tolerant 7T SRAM With Enhanced Read Sensing Margin for Voltage Scaling	15
Closed-Form Capacitance Network Compact Model and Monte Carlo Analysis of the GIDL-Assisted Potential Growth in 3-D NAND Flash String	15
DH-PIM: Maximizing Computing Unit Utilization in Digital PIM by Dual Half Mode Extension	15
Espresso: Exploiting the Sparsity Property in Brain-Inspired Vision Sensors with Spatiotemporal Ordering	15
MiniControl 2.0: Co-Synthesis of Flow and Control Layers for Microfluidic Biochips With Strictly Constrained Control Ports	15
CDAR-DRAM: Enabling Runtime DRAM Performance and Energy Optimization via In-Situ Charge Detection and Adaptive Data Restoration	15
Digitally Assisted Mixed-Signal Circuit Security	15
A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs	15
AsyncGrid: An Intra- and Inter-Layer Asynchronous Hybrid Parallelism System for Responsive Edge LLM Inference	15
A Novel MDM-Based Optical Networks-on-Chip With Reliability Analysis	15
Correlated Bayesian Model Fusion: Efficient High-Dimensional Performance Modeling of Analog/RF Integrated Circuits Over Multiple Corners	15
OpeNPDN: A Neural-Network-Based Framework for Power Delivery Network Synthesis	15
Quantum Multi-View Feature Selection With Configurable Kernel Circuits and Adaptive Fusion	14
Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICs	14
Efficient Design Optimization for Diffractive Deep Neural Networks	14
An Efficient Bit-Sparse DNN Accelerator Exploiting Adaptive Bit-Serial Computations	14
Delaying Crash Consistency for Building A High-Performance Persistent Memory File System	14
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Publication Information	14
A Comprehensive Dataflow-Mapping Optimization for Fully Pipelined Execution in Spatial Programmable Architecture	14
Table of Contents	14
InstantGR: Scalable GPU Parallelization for 3-D Global Routing	14
Assessing the Potential of Escalating RowHammer Attack Distance to Bypass-Counter-Based Defenses	14
Counteracting Adversarial Attacks in Autonomous Driving	14
HALTRAV: Design of a High-Performance and Area-Efficient Latch With Triple-Node-Upset Recovery and Algorithm-Based Verifications	14
Varying Periods of In-Field Testing With Storage- and Counter-Based Logic Built-In Self-Test	14
NV-APP: Invalid Programming Performance Improved No-Verify and Adaptive Pulse Programming Scheme for 3-D QLC nand Flash	14
On Legalization of Die Bonding Bumps and Pads for 3-D ICs	14
Table of contents	14
Unleashing the Potential of Sparse DNNs Through Synergistic Hardware-Sparsity Co-Design	14
Autonomous Model Quantization Framework for Hybrid Vision Transformers based on Reinforcement Learning	14
Toward Critical Flip-Flop Identification for Soft-Error Tolerance With Graph Neural Networks	14
WPAlloc: An Efficient Wear-Leveling-Aware Parallel Allocator for Persistent Memory File Systems	14
Table of Contents	14
Automated Bitstream-Level Cost-Reliability Design-Space Exploration for SRAM-Based FPGAs	14
High-Performance Accurate and Approximate Multipliers for FPGA-Based Hardware Accelerators	14
Multiplication Through a Single Look-Up-Table (LUT) in CNN Inference Computation	14
Knowledge-Intensive Diagnostics Using Case-Based Reasoning and Synthetic Case Generation	14
Intertwine: Nonlinear Quantum Feature Selection With Multi-Kernel Circuits	14
INCAME: Interruptible CNN Accelerator for Multirobot Exploration	14
Multiobjective Coverage Optimization for 3-D Heterogeneous Wireless Sensor Networks	14
A Comprehensive Evaluation of Integrated Circuits Side-Channel Resilience Utilizing Three-Independent-Gate Silicon Nanowire Field Effect Transistors-Based Current Mode Logic	14
Search-Free Inference Acceleration for Sparse Convolutional Neural Networks	14
System-on-Chip Information Flow Validation Under Asynchronous Resets	14
Discovering Optimal Constant Matrix Multiplication Circuits with Boolean Satisfiability	14
Quantifying Information Leakage for Security Verification of Compiler Optimizations	14
A Flexible Yet Efficient DNN Pruning Approach for Crossbar-Based Processing-in-Memory Architectures	13
Toward Write Optimization for Skyrmion Racetrack Memory by Skyrmion Repermutation	13