IEEE Transactions on Computer-Aided Design of Integrated Circuits and

Article	Citations
Table of Contents	141
Reducing Transistor Count in CMOS Logic Design Through Clustering and Library-Independent Multiple-Output Logic Synthesis	134
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	127
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	125
SparseACC: A Generalized Linear Model Accelerator for Sparse Datasets	92
Pass/Fail Data for Logic Diagnosis Under Bounded Transparent Scan	89
Data Representation Aware of Damage to Extend the Lifetime of MLC NAND Flash Memory	84
Detecting Spoofed Noisy Speeches via Activation-Based Residual Blocks for Embedded Systems	83
Multimode Security-Aware Real-Time Scheduling on Multiprocessors	79
Combating Stealthy Thermal Covert Channel Attack With Its Thermal Signal Transmitted in Direct Sequence Spread Spectrum	74
COMPACT: Flow-Based Computing on Nanoscale Crossbars With Minimal Semiperimeter and Maximum Dimension	69
FETTA: Flexible and Efficient Hardware Accelerator for Tensorized Neural Network Training	67
General Purpose Deep Learning Accelerator Based on Bit Interleaving	65
VSTherm: A Virtual Path-based Stochastic Solver for Full-Chip Leakage-Aware Nonlinear Thermal Simulation	63
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	62
ACED-IT: Assuring Confidential Electronic Design Against Insider Threats in a Zero-Trust Environment	60
Harmonia : A Unified Architecture for Efficient Deep Symbolic Regression	60
A New Pipelined Output Data Reducer of BOST for Improved Parallelism	60
Experimental Verification and Analysis of the Acceleration Factor Model for 3-D nand Flash Memory	58
Exploring Bitslicing Architectures for Enabling FHE-Assisted Machine Learning	58
Near-Free Lifetime Extension for 3-D nand Flash via Opportunistic Self-Healing	58
Eff-ECC: Protecting GPGPUs Register File With a Unified Energy-Efficient ECC Mechanism	55
Contamination-Aware Synthesis for Programmable Microfluidic Devices	54
Frequency-Domain Modeling of Interconnects Based on Assemble Neural Network for 3-D Integration	54
An Optimization-Aware Prerouting Timing Prediction Framework Based on Multimodal Learning	54

CorcPUM++: Enabling Row-Access and Column-Access Cooperation for Fair and Efficient Thread-Level Scientific Computing using Resistive Cross-Point Random-Access Memory	53
A Novel Read Scheme Using GIDL Current to Suppress Read Disturbance in 3-D nand Flash Memories	53
Reducing the CNOT Count for Clifford+T Circuits on NISQ Architectures	50
ESFA: An Efficient Scalable FFT Design Framework on Versal AI Engine	49
RefSCAT: Formal Verification of Logic-Optimized Multipliers via Automated Reference Multiplier Generation and SCA-SAT Synergy	49
A Space–Time Neural Network for Analysis of Stress Evolution Under DC Current Stressing	48
DCP-CNN: Efficient Acceleration of CNNs With Dynamic Computing Parallelism on FPGA	48
Surrogate-Assisted Framework for Log-Periodic Feedlines based Filter Optimization	47
A Probabilistic Machine Learning Approach for the Uncertainty Quantification of Electronic Circuits Based on Gaussian Process Regression	45
GPCB Routing: Generative Pretrained Transformers-Based Printed Circuit Board Routing Method	44
Via-Based Redistribution Layer Routing for InFO Packages With Irregular Pad Structures	44
Formal Verification of Integer Multiplier Circuits Using Binary Decision Diagrams	44
A Geometry-Scalable DC I–V Calibration Methodology for a Commercial Bulk CMOS Process Design Kit for Cryogenic ICs Operating Near 1 K	43
DrlGoFPGA 2.0: FPGA Global Placement Based on Multi-Agent Graph Transformers and Nonlinear Placement Co-Optimization	41
Fission: A Unified FHE Accelerator Supporting Variable Bit-Widths	41
Computing Execution Times With Execution Decision Diagrams in the Presence of Out-of-Order Resources	39
RLPlace: Using Reinforcement Learning and Smart Perturbations to Optimize FPGA Placement	39
AutoHoG: Automating Homomorphic Gate Design for Large-Scale Logic Circuit Evaluation	38
SATA: Sparsity-Aware Training Accelerator for Spiking Neural Networks	38
Flex-SFU: Activation Function Acceleration With Nonuniform Piecewise Approximation	38
Adaptive Granularity Progressive LDPC Decoding for NAND Flash Memory	37
Cocktail: Mixing Data With Different Characteristics to Reduce Read Reclaims for nand Flash Memory	37
A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead	37
HyperSpikeASIC: Accelerating Event-Based Workloads With HyperDimensional Computing and Spiking Neural Networks	36
k-Degree Parallel Comparison-Free Hardware Sorter for Complete Sorting	36
VersaAccel: A Versatile Configurable Accelerator for Diverse Sparse-Dense Matrix Operators	36
Circuit Topology-Aware Vaccination-Based Hardware Trojan Detection	36
Multicycle Tests for Functionally Possible Two-Cycle Gate-Exhaustive Faults	35
On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers	35
DRPplace: Reinforcement Learning-Based Hierarchical Geometric Placement with Polygon-Aware Whitespace Management	35
Functionally Possible Scan-Based Test Set as a Dual of a Compressed Multicycle Test Set	34
Crosstalk-Aware Automatic Topology Customization and Optimization for Wavelength-Routed Optical NoCs	34
Adaptive Edge Offloading for Image Classification Under Rate Limit	34
On Modeling and Detecting Trojans in Instruction Sets	34
FedMT: Multitask Federated Learning With Competitive GPU Resource Sharing	34
Deeploy: Enabling Energy-Efficient Deployment of Small Language Models on Heterogeneous Microcontrollers	34
Toward Minimum WCRT Bound for DAG Tasks Under Prioritized List Scheduling Algorithms	33
When Random Is Bad: Selective CRPs for Protecting PUFs Against Modeling Attacks	33
Accuracy-Based Hybrid Parasitic Capacitance Extraction Using Rule-Based, Neural-Networks, and Field-Solver Methods	33
Crosstalk Analysis and Advancements in RDL Interposer Design for High-Speed Channels	32
Development and Efficiency Analysis of a Switching Scheme for INL Reduction in Unary DACs	32
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	31
NC-Net: Efficient Neuromorphic Computing Using Aggregated Subnets on a Crossbar-Based Architecture With Nonvolatile Memory	31
A Low Latency and Compact GCD Design Using an Intelligent Seed-Selection Scheme of LL-PRNG	31
Robust Wafer Classification With Imperfectly Labeled Data Based on Self-Boosting Co-Teaching	31
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	31
A Memristor Crossbar-Based Lyapunov Equation Solver	31
Design of Ultracompact Content Addressable Memory Exploiting 1T-1MTJ Cell	31
CPU Address-Leakage Transient Execution Attack Detection and Its Countermeasures	30
Efficient Sample Preparation With Fully Programmable Valve Arrays	30

Wrapping Paths of Undetected Transition Faults With Two-Cycle Gate-Exhaustive Faults	30
Analytical Modeling of Multiple Co-Existing Inaccuracies in RF Controlling Circuits for Superconducting Quantum Computing	30
An Efficient Deep Learning Accelerator Architecture for Compressed Video Analysis	29
SwarmRouter: Obstacle-Avoiding Routing for Droplet Swarms on Active-Matrix Digital Microfluidic Biochips	29
Keeping Deep Lithography Simulators Updated: Global–Local Shape-Based Novelty Detection and Active Learning	29
ProVAT: An Automated Design and Analysis Framework for Process-Variation-Resilient Design of Silicon Photonic Microring Resonators	29
HeteroQNN: Enabling Distributed QNN Under Heterogeneous Quantum Devices	29
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	29
DASA: Distribution-Aware Sparse Attention for Accelerating Diffusion Transformer	29
Softm e x : Lightweight Softmax Compute Engines Based on Exponentiation Unit	28
CaBaFL: Asynchronous Federated Learning via Hierarchical Cache and Feature Balance	28
Approximate Conformance Checking for Closed-Loop Systems With Neural Network Controllers	28
DAGSIS: A DAG-Aware MAGIC-Based Synthesis Framework for In-Memory Computing	28
Redistribution Layer Routing for Fan-Out Wafer-Level Packaging Considering Multiple Advanced Design Rules	28
Simulation-Guided Approximate Logic Synthesis Under the Maximum Error Constraint	28
Board-Level Reliability Evaluation and Optimization of Power MOSFET Module Under Thermal Cycling Conditions	28
Real-Time Video Recognition via Decoder-Assisted Neural Network Acceleration Framework	28
Detecting Spoofed Speeches via Segment-Based Word CQCC and Average ZCR for Embedded Systems	27
Two-Layer Memristive Neural Network Circuit Based on Biological Hierarchical Information Processing Mechanism	27
Caphammer: Exploiting Capacitor Vulnerability of Energy Harvesting Systems	27
TaintLock: Hardware IP Protection Against Oracle-Guided and Oracle-Reconstruction Attacks	27
SMT Solver With Hardware Acceleration	26
Comparing Methods for the Cross-Level Verification of SystemC Peripherals with Symbolic Execution	26
Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review	26
FLAM-PUF: A Response–Feedback-Based Lightweight Anti-Machine-Learning-Attack PUF	26
CKTSO: High-Performance Parallel Sparse Linear Solver for General Circuit Simulations	26
Partial Sum Quantization for Reducing ADC Size in ReRAM-Based Neural Network Accelerators	26
Delay Prediction for ASIC HLS: Comparing Graph-Based and Nongraph-Based Learning Models	26
TRAGIC: Test Oracle Generation for ISA Compliance Testing via Large Language Model	26
BLAST: Belling the Black-Hat High-Level Synthesis Tool	26
LoCoMOBO: A Local Constrained Multiobjective Bayesian Optimization for Analog Circuit Sizing	26
LAHDC: Logic-Aggregation-Based Query for Embedded Hyperdimensional Computing Accelerator	26
Silicon-Proven ASIC Design for the Polynomial Operations of Fully Homomorphic Encryption	26
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	25
Hierarchical-ISA Supporting Row-Wise Operands for Efficient DNN Computation	25
Direct Search Procedure for Functional Compaction With Improved Fault Coverage	25
Cross-Domain Optimization of Low-Power Mixed-Signal Sensor Systems Under Classification Accuracy Constraints	25
Xplace: An Extremely Fast and Extensible Placement Framework	25
A Markov-Chain-Based PUF Using Chain-Block-Obfuscation Mechanism Resisting Machine Learning Attacks With High Uniformity Robustness	25
Similarity-Aware CNN for Efficient Video Recognition at the Edge	25
FPGA Technology Mapping With Adaptive Gate Decomposition	25
Table of Contents	24
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	24
Achievable-Rate-Aware Retention-Error Correction for Multi-Level-Cell NAND Flash Memory	24
A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking	24
Efficient Static-Driven Integration for Step-Function Transient Simulation	24
ACCURATE: Accuracy Maximization for Real-Time Multicore Systems With Energy-Efficient Way-Sharing Caches	23
VirtualSync+: Timing Optimization With Virtual Synchronization	23
A Highly Compressed Accelerator With Temporal Optical Flow Feature Fusion and Tensorized LSTM for Video Action Recognition on Terminal Device	23
Generalized Affine Equivalence Checking of Boolean Functions via Reachability Analysis	23
Multi-Corner Timing Macro Modeling With Neural Collaborative Filtering From Recommendation Systems Perspective	23
Clock-Latency-Aware Fault-Tolerant DLL for Multi-Die Clock Synchronization	23
NeuroSchedule2.0: A Novel GNN-based Scheduling Method with RL-based Preprocessing Optimization for High-level Synthesis	22
Mapping Nearest Neighbor Compliant Quantum Circuits Onto a 2-D Hexagonal Architecture	22
VirSoC: Automatic Synthesis of Virtual System-on-Chip Environments	22
A Hybrid Test Scheme for Automotive IC in Multisite Testing	22
SEM-CLIP 2.0: Precise Zero-/Few-Shot Learning for Nanoscale Defect Detection in SEM Image	22
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	22
QuantTPM: Efficient Mixed-Precision Quantization Framework for Tractable Probabilistic Models	22
PASS: Pattern-Sequence-Authentication-Based Secure Scan Against Reverse Engineering Attacks	22
CURIOUS: Efficient Neural Architecture Search Based on a Performance Predictor and Evolutionary Search	22
Harnessing Unipolar Threshold Switches for Enhanced Rectification	22
AnaCraft: Duel-Play Probabilistic-Model-Based Reinforcement Learning for Sample-Efficient PVT-Robust Analog Circuit Sizing Optimization	22
Vespa: Logic-Level Constraint-Based Validation for Continuous-Flow Microfluidic Devices	22
CirOPT : Toward Effective Combinational Equivalence Checking via Compiler Optimization	21
NeRF-PIM: PIM Hardware-Software Co-Design of Neural Rendering Networks	21
Lightweight Failure Prediction Algorithms Based on Internal Characteristics of 3-D nand Flash Memory	21
MarchGen: A March Sequence Generation Method for Faults With an Arbitrary Number of Operations in RAMs	21
CHEF: A Framework for Deploying Heterogeneous Models on Clusters With Heterogeneous FPGAs	21
Computational Performance Bounds Prediction in Quantum Computing With Unstable Noise	21
Division-Free Four-Way Toom–Cook Polynomial Multiplication Architecture for Large Integer Arithmetic on FPGAs and ASICs	21
A Zero-overhead Flow for Security Closure	21
Modular Functional Test Sequences for Test Compaction	21
A Data-Driven Stochastic Memristor Model for Integrated Circuit Simulation	21
PISOV: Physics-Informed Separation of Variables Solvers for Full-Chip Thermal Analysis	20
A Framework of Automated LC -VCO Design with Physical Layout Based on Reinforcement Learning	20
Table of Contents	20
Energy-Efficient DNN Inference on Approximate Accelerators Through Formal Property Exploration	20
Fair-ZNS: Enhancing Fairness in ZNS SSDs Through Self-Balancing I/O Scheduling	20
CTM-SRAF: Continuous Transmission Mask-Based Constraint-Aware Subresolution Assist Feature Generation	20

TroLL: Exploiting Structural Similarities Between Logic Locking and Hardware Trojans	20
ARMISTICE: Microarchitectural Leakage Modeling for Masked Software Formal Verification	20
Modern Automatic PCB Placement With Complex Constraints	20
LAS: Reducing Redundant Memory Access in ANNS via Adaptive Learned Indexing	20
CoaCAD: Correlation-Assisted Computer-Aided Design for Nonvolatile FPGAs	20
Online Reset for Signal Temporal Logic Monitoring	20
A Parallelism-Driven, Area-Aware Technology Mapping Framework for Memristive Logic-in-Memory	20
Approximate Logic Synthesis for Dot-Inverter Graphs Using Node Merging-Enhanced Genetic Algorithm-Based Approach	19
AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMs	19
ARTEMIS: A Mixed Analog-Stochastic In-DRAM Accelerator for Transformer Neural Networks	19
Glass Interposer Integration of Logic and Memory Chiplets: PPA and Power/Signal Integrity Benefits	19
A Parameter Extraction Method for LC Circuit of DB-BPF Based on Fully Connected Network	19
High-Precision Short-Term Lifetime Prediction in TLC 3-D NAND Flash Memory as Hot-Data Storage	19
Model-to-Circuit Cross-Approximation For Printed Machine Learning Classifiers	19
FDAM: Filter-Dedicated Approximate Multiplier Design for Real-Time CNN Acceleration	19
MDD: A Unified Model-Driven Design Framework for Embedded Control Software	19
RuleLearner: OPC Rule Extraction From Inverse Lithography Technique Engine	19
K-SpecPart: Supervised Embedding Algorithms and Cut Overlay for Improved Hypergraph Partitioning	19
Fama: An FPGA-Oriented Multiscalar Multiplication Accelerator Optimized via Algorithm–Hardware Co-Design	19
Location-and-Preference Joint Prediction for Task Assignment in Spatial Crowdsourcing	19
Bulls-Eye: Active Few-Shot Learning Guided Logic Synthesis	19
Compiling All-Digital-Embedded Content Addressable Memories on Chip for Edge Application	19
Improved EM Side-Channel Analysis Attack Probe Detection Range Utilizing Coplanar Capacitive Asymmetry Sensing	18
Tight Compression: Compressing CNN Through Fine-Grained Pruning and Weight Permutation for Efficient Implementation	18
Memristive Circuit Implementation of Context-Dependent Emotional Learning Network and Its Application in Multitask	18
Table of Contents	18
Towards Efficient ECO Automation: Timing and DRCs Concurrent Optimization Using Reinforcement Learning	18
DH-PIM: Maximizing Computing Unit Utilization in Digital PIM by Dual Half Mode Extension	18
Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICs	18
An Efficient Bit-Sparse DNN Accelerator Exploiting Adaptive Bit-Serial Computations	18
CDAR-DRAM: Enabling Runtime DRAM Performance and Energy Optimization via In-Situ Charge Detection and Adaptive Data Restoration	18
Flexible Generation of Fast and Accurate Software Performance Simulators From Compact Processor Descriptions	18
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	18
Hardware Security Meets Incomplete Netlists: Insights Into Trojan Detection via Structural Reasoning	18
Nested Speculative Execution Attacks via Runahead	18
Hierarchical Model Checking of SystemVerilog-Specified Asynchronous Circuits for Deadlock Detection	18
Accelerating Real-Valued FFT on CPU-FPGA Platforms	18
Closed-Form Capacitance Network Compact Model and Monte Carlo Analysis of the GIDL-Assisted Potential Growth in 3-D NAND Flash String	18
ParaVOM: Parallel-Execution-Aware Validation and Optimization for Multilayered Continuous-Flow Microfluidic Biochips	18
On Development of Reliable Machine Learning Systems Based on Machine Error Tolerance of Input Images	18
GEAR: Graph-Evolving Aware Data Arranger to Enhance the Performance of Traversing Evolving Graphs on SCM	18
Hierarchical Mapping of Large-Scale Spiking Convolutional Neural Networks Onto Resource-Constrained Neuromorphic Processor	18
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	18
Hardware Accelerator for Short-Read DNA Sequence Alignment Using Burrows-Wheeler Transformation	18
On Legalization of Die Bonding Bumps and Pads for 3-D ICs	18
An MILP Encoding for Efficient Verification of Quantized Deep Neural Networks	18
MLogNet: A Logarithmic Quantization-Based Accelerator for Depthwise Separable Convolution	18
Quantum Multi-View Feature Selection With Configurable Kernel Circuits and Adaptive Fusion	17
A Low-Power Variation-Tolerant 7T SRAM With Enhanced Read Sensing Margin for Voltage Scaling	17
Correlated Bayesian Model Fusion: Efficient High-Dimensional Performance Modeling of Analog/RF Integrated Circuits Over Multiple Corners	17
AsyncGrid: An Intralayer and Interlayer Asynchronous Hybrid Parallelism System for Responsive Edge LLM Inference	17
MiniControl 2.0: Co-Synthesis of Flow and Control Layers for Microfluidic Biochips With Strictly Constrained Control Ports	17
A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs	17
TransMap: Transformer-Enhanced Divide-and-Conquer Reinforcement Learning Framework for Efficient CGRA Compilation	17
Multiobjective Coverage Optimization for 3-D Heterogeneous Wireless Sensor Networks	17
Burst Automaton: Framework for Speed-Independent Synthesis Using Burst-Mode Specifications	17
A Universal RRAM-Based DNN Accelerator With Programmable Crossbars Beyond MVM Operator	17
PASGCN: An ReRAM-Based PIM Design for GCN With Adaptively Sparsified Graphs	17
RTCache: An Efficient Remapping Table Cache for NVM Wear-Leveling	17
A Novel MDM-Based Optical Networks-on-Chip With Reliability Analysis	17
Quantized Neural Network Synthesis for Direct Logic Circuit Implementation	16
Delaying Crash Consistency for Building A High-Performance Persistent Memory File System	16
GARNETT: Graph-based Fast yet Accurate Post-Placement Toggle Rate Prediction Model from RTL without Technology-dependent Logic Synthesis and Placement	16
CoGNN: An Algorithm-Hardware Co-Design Approach to Accelerate GNN Inference With Minibatch Sampling	16
Unleashing the Potential of Sparse DNNs Through Synergistic Hardware-Sparsity Co-Design	16
RTeX: An Efficient and Timing-Predictable Multithreaded Executor for ROS 2	16
NoCFuzzer: Automating NoC Verification in UVM	16
HALTRAV: Design of a High-Performance and Area-Efficient Latch With Triple-Node-Upset Recovery and Algorithm-Based Verifications	16
Espresso: Exploiting the Sparsity Property in Brain-Inspired Vision Sensors With Spatiotemporal Ordering	16
Data-Driven Feature Selection Framework for Approximate Circuit Design	16
Knowledge-Intensive Diagnostics Using Case-Based Reasoning and Synthetic Case Generation	16
Digitally Assisted Mixed-Signal Circuit Security	16
Test Generation for Functionally Possible Subpaths	16
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Publication Information	16
Varying Periods of In-Field Testing With Storage- and Counter-Based Logic Built-In Self-Test	16
Modeling and Analysis of the LatestTime Message Synchronization Policy in ROS	16
Intertwine: Nonlinear Quantum Feature Selection With Multikernel Circuits	16
NV-APP: Invalid Programming Performance Improved No-Verify and Adaptive Pulse Programming Scheme for 3-D QLC nand Flash	16
Efficient Design Optimization for Diffractive Deep Neural Networks	16
F-POI: A Lightweight, Noise-Resilient Parallel Side-Channel Attack on Kyber	16
OpeNPDN: A Neural-Network-Based Framework for Power Delivery Network Synthesis	16
Automated Bitstream-Level Cost-Reliability Design-Space Exploration for SRAM-Based FPGAs	16
Table of Contents	16
Large Data Transfer Optimization for Improved Robustness in Real-Time V2X-Communication	16
GPU Performance Optimization via Shared Instruction-Aware Cache Cooperation	16
AIoTML: A Unified Modeling Language for AIoT-Based Cyber–Physical Systems	15
Real-Time 3-D Thermal Simulation of Advanced Packages via Generative Adversarial Networks	15
Efficient Cartesian Genetic Programming-Based Automatic Synthesis Framework for Reversible Quantum-Flux-Parametron Logic Circuits	15
FS-TRA: Evaluating Sequential Circuit Reliability via a Fanout-Source Tracking and Reduction Approach	15
A Q -Learning-Based Display Energy Optimization Scheme for Android Systems	15
A Flexible Yet Efficient DNN Pruning Approach for Crossbar-Based Processing-in-Memory Architectures	15
WPAlloc: An Efficient Wear-Leveling-Aware Parallel Allocator for Persistent Memory File Systems	15
ILRM: Imitation Learning-Based Resource Management for Integrated CPU–GPU Edge Systems With Renewable Energy Sources	15
SNAS: Fast Hardware-Aware Neural Architecture Search Methodology	15
SubMap: A Partial Mapping Strategy for CGRA Based on sub-CGRA Exploration	15