IEEE Transactions on Computer-Aided Design of Integrated Circuits and

Papers
(The H4-Index of IEEE Transactions on Computer-Aided Design of Integrated Circuits and is 39. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-06-01 to 2026-06-01.)
ArticleCitations
Table of Contents138
Reducing Transistor Count in CMOS Logic Design Through Clustering and Library-Independent Multiple-Output Logic Synthesis125
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information123
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information106
SparseACC: A Generalized Linear Model Accelerator for Sparse Datasets104
Pass/Fail Data for Logic Diagnosis Under Bounded Transparent Scan90
Data Representation Aware of Damage to Extend the Lifetime of MLC NAND Flash Memory82
Detecting Spoofed Noisy Speeches via Activation-Based Residual Blocks for Embedded Systems79
Multimode Security-Aware Real-Time Scheduling on Multiprocessors77
Combating Stealthy Thermal Covert Channel Attack With Its Thermal Signal Transmitted in Direct Sequence Spread Spectrum74
COMPACT: Flow-Based Computing on Nanoscale Crossbars With Minimal Semiperimeter and Maximum Dimension66
VersaAccel: A Versatile Configurable Accelerator for Diverse Sparse-Dense Matrix Operators66
FETTA: Flexible and Efficient Hardware Accelerator for Tensorized Neural Network Training61
Making the Most of Scarce Input Data in Deep Learning-Based Source Code Classification for Heterogeneous Device Mapping59
General Purpose Deep Learning Accelerator Based on Bit Interleaving58
VSTherm: A Virtual Path-based Stochastic Solver for Full-Chip Leakage-Aware Nonlinear Thermal Simulation57
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information56
A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead55
A New Pipelined Output Data Reducer of BOST for Improved Parallelism54
Harmonia : A Unified Architecture for Efficient Deep Symbolic Regression54
GPCB Routing: Generative Pretrained Transformers-Based Printed Circuit Board Routing Method53
ACED-IT: Assuring Confidential Electronic Design Against Insider Threats in a Zero-Trust Environment52
Crosstalk-Aware Automatic Topology Customization and Optimization for Wavelength-Routed Optical NoCs51
k-Degree Parallel Comparison-Free Hardware Sorter for Complete Sorting50
Exploring Bitslicing Architectures for Enabling FHE-Assisted Machine Learning50
Near-Free Lifetime Extension for 3-D nand Flash via Opportunistic Self-Healing50
Circuit Topology-Aware Vaccination-Based Hardware Trojan Detection48
Experimental Verification and Analysis of the Acceleration Factor Model for 3-D nand Flash Memory48
Flex-SFU: Activation Function Acceleration With Nonuniform Piecewise Approximation47
DCP-CNN: Efficient Acceleration of CNNs With Dynamic Computing Parallelism on FPGA46
An Optimization-Aware Prerouting Timing Prediction Framework Based on Multimodal Learning46
A Novel Read Scheme Using GIDL Current to Suppress Read Disturbance in 3-D nand Flash Memories45
CorcPUM++: Enabling Row-Access and Column-Access Cooperation for Fair and Efficient Thread-Level Scientific Computing using Resistive Cross-Point Random-Access Memory45
AutoHoG: Automating Homomorphic Gate Design for Large-Scale Logic Circuit Evaluation44
HyperSpikeASIC: Accelerating Event-Based Workloads With HyperDimensional Computing and Spiking Neural Networks42
Computing Execution Times With Execution Decision Diagrams in the Presence of Out-of-Order Resources41
Reducing the CNOT Count for Clifford+T Circuits on NISQ Architectures41
Adaptive Granularity Progressive LDPC Decoding for NAND Flash Memory40
RefSCAT: Formal Verification of Logic-Optimized Multipliers via Automated Reference Multiplier Generation and SCA-SAT Synergy40
Frequency-Domain Modeling of Interconnects Based on Assemble Neural Network for 3-D Integration39
Eff-ECC: Protecting GPGPUs Register File With a Unified Energy-Efficient ECC Mechanism39
ESFA: An Efficient Scalable FFT Design Framework on Versal AI Engine39
RLPlace: Using Reinforcement Learning and Smart Perturbations to Optimize FPGA Placement39
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