OOIR: Observatory of International Research

Papers

(The H4-Index of IEEE Transactions on Computer-Aided Design of Integrated Circuits and is 37. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-12-01 to 2025-12-01.)

Article	Citations
Table of Contents	127
Reducing Transistor Count in CMOS Logic Design Through Clustering and Library-Independent Multiple-Output Logic Synthesis	109
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	92
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	90
A Style-Based Analog Layout Migration Technique With Complete Routing Behavior Preservation	85
A Novel Read Scheme Using GIDL Current to Suppress Read Disturbance in 3-D nand Flash Memories	84
Pass/Fail Data for Logic Diagnosis Under Bounded Transparent Scan	77
SparseACC: A Generalized Linear Model Accelerator for Sparse Datasets	77
Data Representation Aware of Damage to Extend the Lifetime of MLC NAND Flash Memory	69
Detecting Spoofed Noisy Speeches via Activation-Based Residual Blocks for Embedded Systems	66
Multimode Security-Aware Real-Time Scheduling on Multiprocessors	65
Near-Free Lifetime Extension for 3-D nand Flash via Opportunistic Self-Healing	58
Experimental Verification and Analysis of the Acceleration Factor Model for 3-D nand Flash Memory	55
A Probabilistic Machine Learning Approach for the Uncertainty Quantification of Electronic Circuits Based on Gaussian Process Regression	53
A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead	53
Reducing the CNOT Count for Clifford+T Circuits on NISQ Architectures	52
Combating Stealthy Thermal Covert Channel Attack With Its Thermal Signal Transmitted in Direct Sequence Spread Spectrum	48
Cocktail: Mixing Data With Different Characteristics to Reduce Read Reclaims for nand Flash Memory	47
ESFA: An Efficient Scalable FFT Design Framework on Versal AI Engine	46
Multicycle Tests for Functionally Possible Two-Cycle Gate-Exhaustive Faults	46
Frequency Domain Modeling of Interconnects Based on Assemble Neural Network for 3D Integration	46
COMPACT: Flow-Based Computing on Nanoscale Crossbars With Minimal Semiperimeter and Maximum Dimension	45
Prism-SSD: A Flexible Storage Interface for SSDs	44
k-Degree Parallel Comparison-Free Hardware Sorter for Complete Sorting	44
Code Synthesis for Dataflow-Based Embedded Software Design	44

Crosstalk-Aware Automatic Topology Customization and Optimization for Wavelength-Routed Optical NoCs	43
Contamination-Aware Synthesis for Programmable Microfluidic Devices	42
Exploring Bitslicing Architectures for Enabling FHE-Assisted Machine Learning	41
ACED-IT: Assuring Confidential Electronic Design Against Insider Threats in a Zero-Trust Environment	41
General Purpose Deep Learning Accelerator Based on Bit Interleaving	41
Via-Based Redistribution Layer Routing for InFO Packages With Irregular Pad Structures	39
Toward an Analysable, Scalable, Energy-Efficient I/O Virtualization for Mixed-Criticality Systems	39
Hardware-Enabled Efficient Data Processing With Tensor-Train Decomposition	38
Computing Execution Times With Execution Decision Diagrams in the Presence of Out-of-Order Resources	38
Deeploy: Enabling Energy-Efficient Deployment of Small Language Models on Heterogeneous Microcontrollers	38
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	38
AutoHoG: Automating Homomorphic Gate Design for Large-Scale Logic Circuit Evaluation	38
Block Convolution: Toward Memory-Efficient Inference of Large-Scale CNNs on FPGA	37
Adaptive Granularity Progressive LDPC Decoding for NAND Flash Memory	37