IEEE Transactions on Computer-Aided Design of Integrated Circuits and

Papers
(The H4-Index of IEEE Transactions on Computer-Aided Design of Integrated Circuits and is 39. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-05-01 to 2026-05-01.)
ArticleCitations
Table of Contents136
Reducing Transistor Count in CMOS Logic Design Through Clustering and Library-Independent Multiple-Output Logic Synthesis124
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information119
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information105
SparseACC: A Generalized Linear Model Accelerator for Sparse Datasets98
Pass/Fail Data for Logic Diagnosis Under Bounded Transparent Scan96
Data Representation Aware of Damage to Extend the Lifetime of MLC NAND Flash Memory89
Detecting Spoofed Noisy Speeches via Activation-Based Residual Blocks for Embedded Systems81
Multimode Security-Aware Real-Time Scheduling on Multiprocessors78
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information76
A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead69
Cocktail: Mixing Data With Different Characteristics to Reduce Read Reclaims for nand Flash Memory66
Contamination-Aware Synthesis for Programmable Microfluidic Devices65
On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers61
Deeploy: Enabling Energy-Efficient Deployment of Small Language Models on Heterogeneous Microcontrollers58
RefSCAT: Formal Verification of Logic-Optimized Multipliers via Automated Reference Multiplier Generation and SCA-SAT Synergy57
COMPACT: Flow-Based Computing on Nanoscale Crossbars With Minimal Semiperimeter and Maximum Dimension54
Combating Stealthy Thermal Covert Channel Attack With Its Thermal Signal Transmitted in Direct Sequence Spread Spectrum54
VSTherm: A Virtual Path-based Stochastic Solver for Full-Chip Leakage-Aware Nonlinear Thermal Simulation53
VersaAccel: A Versatile Configurable Accelerator for Diverse Sparse-Dense Matrix Operators53
Formal Verification of Integer Multiplier Circuits Using Binary Decision Diagrams52
ACED-IT: Assuring Confidential Electronic Design Against Insider Threats in a Zero-Trust Environment51
ESFA: An Efficient Scalable FFT Design Framework on Versal AI Engine50
A Probabilistic Machine Learning Approach for the Uncertainty Quantification of Electronic Circuits Based on Gaussian Process Regression50
SATA: Sparsity-Aware Training Accelerator for Spiking Neural Networks48
Frequency-Domain Modeling of Interconnects Based on Assemble Neural Network for 3-D Integration48
Multicycle Tests for Functionally Possible Two-Cycle Gate-Exhaustive Faults48
Eff-ECC: Protecting GPGPUs Register File With a Unified Energy-Efficient ECC Mechanism47
Adaptive Granularity Progressive LDPC Decoding for NAND Flash Memory46
A Space–Time Neural Network for Analysis of Stress Evolution Under DC Current Stressing46
RLPlace: Using Reinforcement Learning and Smart Perturbations to Optimize FPGA Placement46
GPCB Routing: Generative Pretrained Transformers-Based Printed Circuit Board Routing Method46
AutoHoG: Automating Homomorphic Gate Design for Large-Scale Logic Circuit Evaluation44
CorcPUM++: Enabling Row-Access and Column-Access Cooperation for Fair and Efficient Thread-Level Scientific Computing using Resistive Cross-Point Random-Access Memory43
Block Convolution: Toward Memory-Efficient Inference of Large-Scale CNNs on FPGA42
A New Pipelined Output Data Reducer of BOST for Improved Parallelism41
An Optimization-Aware Prerouting Timing Prediction Framework Based on Multimodal Learning41
Harmonia : A Unified Architecture for Efficient Deep Symbolic Regression41
Making the Most of Scarce Input Data in Deep Learning-Based Source Code Classification for Heterogeneous Device Mapping40
Crosstalk-Aware Automatic Topology Customization and Optimization for Wavelength-Routed Optical NoCs39
FETTA: Flexible and Efficient Hardware Accelerator for Tensorized Neural Network Training39
Exploring Bitslicing Architectures for Enabling FHE-Assisted Machine Learning39
General Purpose Deep Learning Accelerator Based on Bit Interleaving39
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