OOIR: Observatory of International Research

Papers

(The H4-Index of IEEE Transactions on Computer-Aided Design of Integrated Circuits and is 34. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-09-01 to 2025-09-01.)

Article	Citations
Pass/Fail Data for Logic Diagnosis Under Bounded Transparent Scan	192
Data Representation Aware of Damage to Extend the Lifetime of MLC NAND Flash Memory	120
Detecting Spoofed Noisy Speeches via Activation-Based Residual Blocks for Embedded Systems	97
Multimode Security-Aware Real-Time Scheduling on Multiprocessors	81
Near-Free Lifetime Extension for 3-D nand Flash via Opportunistic Self-Healing	79
A Style-Based Analog Layout Migration Technique With Complete Routing Behavior Preservation	74
HyperSpikeASIC: Accelerating Event-Based Workloads With HyperDimensional Computing and Spiking Neural Networks	70
SparseACC: A Generalized Linear Model Accelerator for Sparse Datasets	67
A Novel Read Scheme Using GIDL Current to Suppress Read Disturbance in 3-D nand Flash Memories	67
A New Pipelined Output Data Reducer of BOST for Improved Parallelism	61
Making the Most of Scarce Input Data in Deep Learning-Based Source Code Classification for Heterogeneous Device Mapping	61
Harmonia: A Unified Architecture for Efficient Deep Symbolic Regression	59
Table of Contents	55
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	55
Formal Verification of Integer Multiplier Circuits Using Binary Decision Diagrams	52
Prism-SSD: A Flexible Storage Interface for SSDs	51
AutoHoG: Automating Homomorphic Gate Design for Large-Scale Logic Circuit Evaluation	47
GPCB Routing: Generative Pretrained Transformers-Based Printed Circuit Board Routing Method	46
A Probabilistic Machine Learning Approach for the Uncertainty Quantification of Electronic Circuits Based on Gaussian Process Regression	45
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	44
Block Convolution: Toward Memory-Efficient Inference of Large-Scale CNNs on FPGA	43
An Optimization-Aware Pre-Routing Timing Prediction Framework Based on Multi-Modal Learning	43
k-Degree Parallel Comparison-Free Hardware Sorter for Complete Sorting	42
DCP-CNN: Efficient Acceleration of CNNs With Dynamic Computing Parallelism on FPGA	42
Code Synthesis for Dataflow-Based Embedded Software Design	40

Cocktail: Mixing Data With Different Characteristics to Reduce Read Reclaims for nand Flash Memory	37
A Space–Time Neural Network for Analysis of Stress Evolution Under DC Current Stressing	37
Exploring Bitslicing Architectures for Enabling FHE-Assisted Machine Learning	37
General Purpose Deep Learning Accelerator Based on Bit Interleaving	37
Eff-ECC: Protecting GPGPUs Register File With a Unified Energy-Efficient ECC Mechanism	37
Computing Execution Times With Execution Decision Diagrams in the Presence of Out-of-Order Resources	37
RefSCAT: Formal Verification of Logic-Optimized Multipliers via Automated Reference Multiplier Generation and SCA-SAT Synergy	37
Via-Based Redistribution Layer Routing for InFO Packages With Irregular Pad Structures	35
Defending Hardware-Based Malware Detectors Against Adversarial Attacks	35
ACED-IT: Assuring Confidential Electronic Design Against Insider Threats in a Zero-Trust Environment	34
Experimental Verification and Analysis of the Acceleration Factor Model for 3-D nand Flash Memory	34
SATA: Sparsity-Aware Training Accelerator for Spiking Neural Networks	34