OOIR: Observatory of International Research

Papers

(The H4-Index of IEEE Transactions on Computer-Aided Design of Integrated Circuits and is 41. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2022-08-01 to 2026-08-01.)

Article	Citations
Table of Contents	143
Reducing Transistor Count in CMOS Logic Design Through Clustering and Library-Independent Multiple-Output Logic Synthesis	137
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	131
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	128
SparseACC: A Generalized Linear Model Accelerator for Sparse Datasets	127
Pass/Fail Data for Logic Diagnosis Under Bounded Transparent Scan	92
Data Representation Aware of Damage to Extend the Lifetime of MLC NAND Flash Memory	89
Detecting Spoofed Noisy Speeches via Activation-Based Residual Blocks for Embedded Systems	88
Multimode Security-Aware Real-Time Scheduling on Multiprocessors	84
Combating Stealthy Thermal Covert Channel Attack With Its Thermal Signal Transmitted in Direct Sequence Spread Spectrum	79
COMPACT: Flow-Based Computing on Nanoscale Crossbars With Minimal Semiperimeter and Maximum Dimension	76
FETTA: Flexible and Efficient Hardware Accelerator for Tensorized Neural Network Training	72
General Purpose Deep Learning Accelerator Based on Bit Interleaving	69
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	68
VSTherm: A Virtual Path-based Stochastic Solver for Full-Chip Leakage-Aware Nonlinear Thermal Simulation	68
Harmonia : A Unified Architecture for Efficient Deep Symbolic Regression	65
Exploring Bitslicing Architectures for Enabling FHE-Assisted Machine Learning	64
A New Pipelined Output Data Reducer of BOST for Improved Parallelism	64
Frequency-Domain Modeling of Interconnects Based on Assemble Neural Network for 3-D Integration	61
Experimental Verification and Analysis of the Acceleration Factor Model for 3-D nand Flash Memory	61
An Optimization-Aware Prerouting Timing Prediction Framework Based on Multimodal Learning	59
Contamination-Aware Synthesis for Programmable Microfluidic Devices	59
CorcPUM++: Enabling Row-Access and Column-Access Cooperation for Fair and Efficient Thread-Level Scientific Computing using Resistive Cross-Point Random-Access Memory	57
A Novel Read Scheme Using GIDL Current to Suppress Read Disturbance in 3-D nand Flash Memories	56
GPCB Routing: Generative Pretrained Transformers-Based Printed Circuit Board Routing Method	55

Surrogate-Assisted Framework for Log-Periodic Feedlines based Filter Optimization	54
Via-Based Redistribution Layer Routing for InFO Packages With Irregular Pad Structures	54
DrlGoFPGA 2.0: FPGA Global Placement Based on Multi-Agent Graph Transformers and Nonlinear Placement Co-Optimization	54
A Geometry-Scalable DC I–V Calibration Methodology for a Commercial Bulk CMOS Process Design Kit for Cryogenic ICs Operating Near 1 K	54
DCP-CNN: Efficient Acceleration of CNNs With Dynamic Computing Parallelism on FPGA	53
A Space–Time Neural Network for Analysis of Stress Evolution Under DC Current Stressing	50
ESFA: An Efficient Scalable FFT Design Framework on Versal AI Engine	49
Fission: A Unified FHE Accelerator Supporting Variable Bit-Widths	48
Computing Execution Times With Execution Decision Diagrams in the Presence of Out-of-Order Resources	47
DRPplace: Reinforcement Learning-Based Hierarchical Geometric Placement with Polygon-Aware Whitespace Management	47
AutoHoG: Automating Homomorphic Gate Design for Large-Scale Logic Circuit Evaluation	45
Multicycle Tests for Functionally Possible Two-Cycle Gate-Exhaustive Faults	45
k-Degree Parallel Comparison-Free Hardware Sorter for Complete Sorting	45
Crosstalk-Aware Automatic Topology Customization and Optimization for Wavelength-Routed Optical NoCs	43
Flex-SFU: Activation Function Acceleration With Nonuniform Piecewise Approximation	42
A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead	41
Cocktail: Mixing Data With Different Characteristics to Reduce Read Reclaims for nand Flash Memory	41