OOIR: Observatory of International Research

Papers

(The H4-Index of IEEE Transactions on Computer-Aided Design of Integrated Circuits and is 33. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-11-01 to 2024-11-01.)

Article	Citations
DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training	124
Hardware/Software Co-Exploration of Neural Architectures	89
A Memristive Synapse Control Method to Generate Diversified Multistructure Chaotic Attractors	88
An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools	78
RxNN: A Framework for Evaluating Deep Neural Networks on Resistive Crossbars	66
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement	64
CKFO: Convolution Kernel First Operated Algorithm With Applications in Memristor-Based Convolutional Neural Network	61
A Triple-Memristor Hopfield Neural Network With Space Multistructure Attractors and Space Initial-Offset Behaviors	56
High-Performance Accurate and Approximate Multipliers for FPGA-Based Hardware Accelerators	52
Client Scheduling and Resource Management for Efficient Training in Heterogeneous IoT-Edge Federated Learning	50
Truly Stripping Functionality for Logic Locking: A Fault-Based Perspective	48
Advanced Equivalence Checking for Quantum Circuits	48
Real-Time Detection and Localization of Distributed DoS Attacks in NoC-Based SoCs	46
Throughput-Conscious Energy Allocation and Reliability-Aware Task Assignment for Renewable Powered In-Situ Server Systems	46
Thwarting All Logic Locking Attacks: Dishonest Oracle With Truly Random Logic Locking	46
Standing on the Shoulders of Giants: Hardware and Neural Architecture Co-Search With Hot Start	45
A Modeling Attack Resistant Deception Technique for Securing Lightweight-PUF-Based Authentication	43
An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization	41
A Novel Memristive Chaotic Neuron Circuit and Its Application in Chaotic Neural Networks for Associative Memory	41
MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper	40
A Memristive Spiking Neural Network Circuit With Selective Supervised Attention Algorithm	39
Efficient Federated Learning for Cloud-Based AIoT Applications	37
Quantum Circuit Transformation Based on Simulated Annealing and Heuristic Search	37
An Efficient Batch-Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multiobjective Acquisition Ensemble	36
NPU Thermal Management	35

Flux Controlled Floating Memristor Employing VDTA: Incremental or Decremental Operation	35
INDRA: Intrusion Detection Using Recurrent Autoencoders in Automotive Embedded Systems	35
Chaotic Weights: A Novel Approach to Protect Intellectual Property of Deep Neural Networks	35
Dynamic DAG Scheduling on Multiprocessor Systems: Reliability, Energy, and Makespan	35
QuCTS—Single-Flux Quantum Clock Tree Synthesis	35
FSpiNN: An Optimization Framework for Memory-Efficient and Energy-Efficient Spiking Neural Networks	34
Memristive Circuit Implementation of Context-Dependent Emotional Learning Network and Its Application in Multitask	34
ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs	33
OpenTimer v2: A New Parallel Incremental Timing Analysis Engine	33
SoFI: Security Property-Driven Vulnerability Assessments of ICs Against Fault-Injection Attacks	33
AccuReD: High Accuracy Training of CNNs on ReRAM/GPU Heterogeneous 3-D Architecture	33