OOIR: Observatory of International Research

Papers

(The H4-Index of IEEE Transactions on Computer-Aided Design of Integrated Circuits and is 33. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-05-01 to 2025-05-01.)

Article	Citations
ACED-IT: Assuring Confidential Electronic Design Against Insider Threats in a Zero-Trust Environment	164
Pass/Fail Data for Logic Diagnosis Under Bounded Transparent Scan	119
Experimental Verification and Analysis of the Acceleration Factor Model for 3-D nand Flash Memory	105
Crosstalk-Aware Automatic Topology Customization and Optimization for Wavelength-Routed Optical NoCs	84
Via-Based Redistribution Layer Routing for InFO Packages With Irregular Pad Structures	68
Data Representation Aware of Damage to Extend the Lifetime of MLC NAND Flash Memory	65
Detecting Spoofed Noisy Speeches via Activation-Based Residual Blocks for Embedded Systems	62
Multimode Security-Aware Real-Time Scheduling on Multiprocessors	61
A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead	61
k-Degree Parallel Comparison-Free Hardware Sorter for Complete Sorting	55
Contamination-Aware Synthesis for Programmable Microfluidic Devices	55
Cocktail: Mixing Data With Different Characteristics to Reduce Read Reclaims for nand Flash Memory	55
Near-Free Lifetime Extension for 3-D nand Flash via Opportunistic Self-Healing	52
A Style-Based Analog Layout Migration Technique With Complete Routing Behavior Preservation	51
Defending Hardware-Based Malware Detectors Against Adversarial Attacks	51
Hardware-Enabled Efficient Data Processing With Tensor-Train Decomposition	50
HyperSpikeASIC: Accelerating Event-Based Workloads With HyperDimensional Computing and Spiking Neural Networks	49
Computing Execution Times With Execution Decision Diagrams in the Presence of Out-of-Order Resources	48
A Novel Read Scheme Using GIDL Current to Suppress Read Disturbance in 3-D nand Flash Memories	47
SparseACC: A Generalized Linear Model Accelerator for Sparse Datasets	44
Making the Most of Scarce Input Data in Deep Learning-Based Source Code Classification for Heterogeneous Device Mapping	43
AutoHoG: Automating Homomorphic Gate Design for Large-Scale Logic Circuit Evaluation	39
Adaptive Granularity Progressive LDPC Decoding for NAND Flash Memory	39
A New Pipelined Output Data Reducer of BOST for Improved Parallelism	38
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	37

Harmonia: A Unified Architecture for Efficient Deep Symbolic Regression	37
Table of Contents	36
Reducing Transistor Count in CMOS Logic Design Through Clustering and Library-Independent Multiple-Output Logic Synthesis	35
Formal Verification of Integer Multiplier Circuits Using Binary Decision Diagrams	35
An Optimization-Aware Pre-Routing Timing Prediction Framework Based on Multi-Modal Learning	34
GPCB Routing: Generative Pretrained Transformers-Based Printed Circuit Board Routing Method	34
Prism-SSD: A Flexible Storage Interface for SSDs	33
On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers	33