OOIR: Observatory of International Research

Papers

(The H4-Index of IEEE Transactions on Computer-Aided Design of Integrated Circuits and is 35. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-10-01 to 2025-10-01.)

Article	Citations
Pass/Fail Data for Logic Diagnosis Under Bounded Transparent Scan	202
Data Representation Aware of Damage to Extend the Lifetime of MLC NAND Flash Memory	122
Detecting Spoofed Noisy Speeches via Activation-Based Residual Blocks for Embedded Systems	102
Near-Free Lifetime Extension for 3-D nand Flash via Opportunistic Self-Healing	84
Multimode Security-Aware Real-Time Scheduling on Multiprocessors	84
A Style-Based Analog Layout Migration Technique With Complete Routing Behavior Preservation	77
HyperSpikeASIC: Accelerating Event-Based Workloads With HyperDimensional Computing and Spiking Neural Networks	73
A Novel Read Scheme Using GIDL Current to Suppress Read Disturbance in 3-D nand Flash Memories	71
SparseACC: A Generalized Linear Model Accelerator for Sparse Datasets	66
Making the Most of Scarce Input Data in Deep Learning-Based Source Code Classification for Heterogeneous Device Mapping	64
A New Pipelined Output Data Reducer of BOST for Improved Parallelism	60
Harmonia: A Unified Architecture for Efficient Deep Symbolic Regression	59
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information	57
Table of Contents	54
Toward an Analysable, Scalable, Energy-Efficient I/O Virtualization for Mixed-Criticality Systems	52
Contamination-Aware Synthesis for Programmable Microfluidic Devices	47
Crosstalk-Aware Automatic Topology Customization and Optimization for Wavelength-Routed Optical NoCs	47
RLPlace: Using Reinforcement Learning and Smart Perturbations to Optimize FPGA Placement	45
HotCluster: A Thermal-Aware Defect Recovery Method for Through-Silicon-Vias Toward Reliable 3-D ICs Systems	45
Formal Verification of Integer Multiplier Circuits Using Binary Decision Diagrams	45
DCP-CNN: Efficient Acceleration of CNNs With Dynamic Computing Parallelism on FPGA	44
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information	42
GPCB Routing: Generative Pretrained Transformers-Based Printed Circuit Board Routing Method	42
A Probabilistic Machine Learning Approach for the Uncertainty Quantification of Electronic Circuits Based on Gaussian Process Regression	40
Prism-SSD: A Flexible Storage Interface for SSDs	39

General Purpose Deep Learning Accelerator Based on Bit Interleaving	39
Experimental Verification and Analysis of the Acceleration Factor Model for 3-D nand Flash Memory	38
Eff-ECC: Protecting GPGPUs Register File With a Unified Energy-Efficient ECC Mechanism	38
k-Degree Parallel Comparison-Free Hardware Sorter for Complete Sorting	38
Code Synthesis for Dataflow-Based Embedded Software Design	38
Flex-SFU: Activation Function Acceleration with Non-Uniform Piecewise Approximation	38
A Space–Time Neural Network for Analysis of Stress Evolution Under DC Current Stressing	38
COMPACT: Flow-Based Computing on Nanoscale Crossbars With Minimal Semiperimeter and Maximum Dimension	37
Reducing the CNOT Count for Clifford+T Circuits on NISQ Architectures	36
Block Convolution: Toward Memory-Efficient Inference of Large-Scale CNNs on FPGA	35
Circuit Topology-Aware Vaccination-Based Hardware Trojan Detection	35
Frequency Domain Modeling of Interconnects Based on Assemble Neural Network for 3D Integration	35