IEEE Micro

Article	Citations
NVIDIA A100 Tensor Core GPU: Performance and Innovation	121
Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs	118
MAESTRO: A Data-Centric Approach to Understand Reuse, Performance, and Hardware Cost of DNN Mappings	76
FerroElectronics for Edge Intelligence	46
PEFL: Deep Privacy-Encoding-Based Federated Learning Framework for Smart Agriculture	45
The Design Process for Google's Training Chips: TPUv2 and TPUv3	45
Accelerating Genome Analysis: A Primer on an Ongoing Journey	42
BlackParrot: An Agile Open-Source RISC-V Multicore for Accelerator SoCs	37
FPGA-Based Near-Memory Acceleration of Modern Data-Intensive Applications	36
Accelerating Chip Design With Machine Learning	31
PyMTL3: A Python Framework for Open-Source Hardware Modeling, Generation, Simulation, and Verification	30
MHADBOR: AI-Enabled Administrative-Distance-Based Opportunistic Load Balancing Scheme for an Agriculture Internet of Things Network	29
Chasing Carbon: The Elusive Environmental Footprint of Computing	29
A Cloud-Optimized Transport Protocol for Elastic and Scalable HPC	28
Kunpeng 920: The First 7-nm Chiplet-Based 64-Core ARM SoC for Cloud Services	28
Near-Memory Processing in Action: Accelerating Personalized Recommendation With AxDIMM	25
Manticore: A 4096-Core RISC-V Chiplet Architecture for Ultraefficient Floating-Point Computing	25
OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs	24
SymbiFlow and VPR: An Open-Source Design Flow for Commercial and Novel FPGAs	23
Evolution of the Graphics Processing Unit (GPU)	21
ReLeQ : A Reinforcement Learning Approach for Automatic Deep Quantization of Neural Networks	21
The Path to Successful Wafer-Scale Integration: The Cerebras Story	19
Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing Cores	19
Circuits and Architectures for In-Memory Computing-Based Machine Learning Accelerators	18
Quantum Computers for High-Performance Computing	18

Superconductor Computing for Neural Networks	17
TSA-NoC: Learning-Based Threat Detection and Mitigation for Secure Network-on-Chip Architecture	17
Extending the Frontier of Quantum Computers With Qutrits	17
Intel Alder Lake CPU Architectures	16
ML-HW Co-Design of Noise-Robust TinyML Models and Always-On Analog Compute-in-Memory Edge Accelerator	15
PCI Express 6.0 Specification: A Low-Latency, High-Bandwidth, High-Reliability, and Cost-Effective Interconnect With 64.0 GT/s PAM-4 Signaling	14
Quantum Computing—From NISQ to PISQ	14
IBM's POWER10 Processor	14
Artificial Intelligence Best Practices in Smart Agriculture	14
FPGA-Accelerated Quantum Computing Emulation and Quantum Key Distillation	13
Agile Hardware Development and Instrumentation With PyRTL	13
Generating Systolic Array Accelerators With Reusable Blocks	13
CHIPKIT: An Agile, Reusable Open-Source Framework for Rapid Test Chip Development	13
Data Centers on Wheels: Emissions From Computing Onboard Autonomous Vehicles	13
Challenges and Opportunities for Autonomous Micro-UAVs in Precision Agriculture	13
On-Demand Mobile CPU Cooling With Thin-Film Thermoelectric Array	12
Accelerator Integration for Open-Source SoC Design	11
An Open Inter-Chiplet Communication Link: Bunch of Wires (BoW)	11
Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion	11
Temporal Computing With Superconductors	11
Co-Design and System for the Supercomputer “Fugaku”	10
AIDA: Associative In-Memory Deep Learning Accelerator	10
NVIDIA Hopper H100 GPU: Scaling Performance	9
Architecting Noisy Intermediate-Scale Quantum Computers: A Real-System Study	9
Evaluating Sensor Data Quality in Internet of Things Smart Agriculture Applications	9
OpenPiton at 5: A Nexus for Open and Agile Hardware Design	9
Compute Substrate for Software 2.0	9
Quantum Codesign	9
Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Systems	9
ECIM: Exponent Computing in Memory for an Energy-Efficient Heterogeneous Floating-Point DNN Training Processor	8
A Taxonomy of ML for Systems Problems	8
Configurable Network Protocol Accelerator (COPA)	8
A Programmable Approach to Neural Network Compression	8
The AMD Next-Generation “Zen 3” Core	8
Aquabolt-XL HBM2-PIM, LPDDR5-PIM With In-Memory Processing, and AXDIMM With Acceleration Buffer	8
Design Tradeoffs in CXL-Based Memory Pools for Public Cloud Platforms	7
On Double Full-Stack Communication-Enabled Architectures for Multicore Quantum Computers	7
Speculative Taint Tracking (STT): A Comprehensive Protection for Speculatively Accessed Data	7
A Next-Generation Cryogenic Processor Architecture	7
Unveiling the Hardware and Software Implications of Microservices in Cloud and Edge Systems	7
UAV–Assisted Joint Wireless Power Transfer and Data Collection Mechanism for Sustainable Precision Agriculture in 5G	7
A Case for Accelerating Software RTL Simulation	7
Accelerating Deep Learning Using Interconnect-Aware UCX Communication for MPI Collectives	7
Rome to Milan, AMD Continues Its Tour of Italy	6
Accelerating ML Recommendation With Over 1,000 RISC-V/Tensor Processors on Esperanto's ET-SoC-1 Chip	6
System on a Package Innovations With Universal Chiplet Interconnect Express (UCIe) Interconnect	6
LiveHD: A Productive Live Hardware Development Flow	6
Power Side-Channel Attacks in Negative Capacitance Transistor	6
MicroScope: Enabling Microarchitectural Replay Attacks	6
A Single-Shot Generalized Device Placement for Large Dataflow Graphs	6

Neuromorphic Near-Sensor Computing: From Event-Based Sensing to Edge Learning	6
Bridging Python to Silicon: The SODA Toolchain	6
High-Performance Mixed-Low-Precision CNN Inference Accelerator on FPGA	6
Temperature-Resilient RRAM-Based In-Memory Computing for DNN Inference	6
Performance Left on the Table: An Evaluation of Compiler Autovectorization for RISC-V	6
History of IBM Z Mainframe Processors	5
ILLIXR: An Open Testbed to Enable Extended Reality Systems Research	5
A Low-Latency and Low-Power Approach for Coherency and Memory Protocols on PCI Express 6.0 PHY at 64.0 GT/s With PAM-4 Signaling	5
Balancing Specialized Versus Flexible Computation in Brain–Computer Interfaces	5
Advances in Microprocessor Cache Architectures Over the Last 25 Years	5
PurpleDrop: A Digital Microfluidics-Based Platform for Hybrid Molecular-Electronics Applications	5
Memory Pooling With CXL	5
Cerebras Architecture Deep Dive: First Look Inside the Hardware/Software Co-Design for Deep Learning	5
Meet the FaM1ly	5
AsmDB: Understanding and Mitigating Front-End Stalls in Warehouse-Scale Computers	5
Democratizing Data-Driven Agriculture Using Affordable Hardware	5
Low-Precision Hardware Architectures Meet Recommendation Model Inference at Scale	5
The Open Domain-Specific Architecture	5
The Vision Behind MLPerf: Understanding AI Inference Performance	5
uGEMM: Unary Computing for GEMM Applications	5
Hertzbleed: Turning Power Side-Channel Attacks Into Remote Timing Attacks on x86	5
Hidden Potential Within Video Game Consoles	5
Emerging Technologies for Quantum Computing	4
ExHero: Execution History-Aware Error-Rate Estimation in Pipelined Designs	4
Accessible, FPGA Resource-Optimized Simulation of Multiclock Systems in FireSim	4
Three-Dimensional Stacked Neural Network Accelerator Architectures for AR/VR Applications	4
Accelerating Allreduce With In-Network Reduction on Intel PIUMA	4
Agile and Open-Source Hardware	4
Compiling for the IBM Matrix Engine for Enterprise Workloads	4
Accelerating Neural Network Inference With Processing-in-DRAM: From the Edge to the Cloud	4
Soil Fertility Monitoring With Internet of Underground Things: A Survey	4
RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures	4
History of Microcontrollers: First 50 Years	4
The Arm Morello Evaluation Platform—Validating CHERI-Based Security in a High-Performance System	4
Marvell ThunderX3: Next-Generation Arm-Based Server Processor	4
Energy-Efficient Video Processing for Virtual Reality	4
LSFQ: A Low-Bit Full Integer Quantization for High-Performance FPGA-Based CNN Acceleration	3
Efficient Language-Guided Reinforcement Learning for Resource-Constrained Autonomous Systems	3
Optimizing Distributed DNN Training Using CPUs and BlueField-2 DPUs	3
Unifying Spatial Accelerator Compilation With Idiomatic and Modular Transformations	3
FPGA Computing	3
Tydi: An Open Specification for Complex Data Structures Over Hardware Streams	3
Shortages of Integrated Circuits	3
The Apollo Guidance Computer	3
Universal Graph-Based Scheduling for Quantum Systems	3
Countering Load-to-Use Stalls in the NVIDIA Turing GPU	3
Enhancing Model Parallelism in Neural Architecture Search for Multidevice System	3
Failure Tolerant Training With Persistent Memory Disaggregation Over CXL	3
Compute Express Link (CXL): Enabling Heterogeneous Data-Centric Computing With Heterogeneous Memory Hierarchy	3
Architectural CO2 Footprint Tool: Designing Sustainable Computer Systems With an Architectural Carbon Modeling Tool	3
Artificial-Intelligence-Enhanced Ultrasound Flow Imaging at the Edge	3
Accelerating Genomic Data Analytics With Composable Hardware Acceleration Framework	3
CXL-Enabled Enhanced Memory Functions	3
TinyIREE: An ML Execution Environment for Embedded Systems From Compilation to Deployment	3
SpecHLS: Speculative Accelerator Design Using High-Level Synthesis	2
The Origin of Intel's Micro-Ops	2
Kaya for Computer Architects: Toward Sustainable Computer Systems	2
Accelerating Phylogenetics Using FPGAs in the Cloud	2
Understanding Acceleration Opportunities at Hyperscale	2
HALO: A Hardware–Software Co-Designed Processor for Brain–Computer Interfaces	2
PCs Take a Page From Xbox With Pluton	2
Pensando Distributed Services Architecture	2
ACCL: Architecting Highly Scalable Distributed Training Systems With Highly Efficient Collective Communication Library	2
Accelerating Finite Field Arithmetic for Homomorphic Encryption on GPUs	2
A Binary Translation Framework for Automated Hardware Generation	2
Compiling for Vector Extensions With Stream-Based Specialization	2
Fused Architecture for Dense and Sparse Matrix Processing in TensorFlow Lite	2
The AMD 400-G Adaptive SmartNIC System on Chip: A Technology Preview	2
Microprocessor Advances and the Mainframe Legacy	2
Hardware Specialization: From Cell to Heterogeneous Microprocessors Everywhere	2
LastLayer: Toward Hardware and Software Continuous Integration	2
Photonic Network-on-Wafer for Multichiplet GPUs	2
Machine Learning for Systems	2
Distributed Deep Learning With GPU-FPGA Heterogeneous Computing	2
A Mobile DNN Training Processor With Automatic Bit Precision Search and Fine-Grained Sparsity Exploitation	2
Virtual Logical Qubits: A Compact Architecture for Fault-Tolerant Quantum Computing	2
Quantum Computing and the Design of the Ultimate Accelerator	2
Towards General-Purpose Acceleration: Finding Structure in Irregularity	2
Creating Foundations for Secure Microarchitectures With Data-Oblivious ISA Extensions	2
HPVM: Hardware-Agnostic Programming for Heterogeneous Parallel Systems	2

Overclocking in Immersion-Cooled Datacenters	2
A Parallel and Updatable Architecture for FPGA-Based Packet Classification With Large-Scale Rule Sets	2
Analysis of Historical Patenting Behavior and Patent Characteristics of Computer Architecture Companies—Part V: References	2
Systematically Understanding Graph Accelerator Dimensions and the Value of Hardware Flexibility	2
Early History of Texas Instrument's Digital Signal Processor	1
SMT: Software-Defined Memory Tiering for Heterogeneous Computing Systems With CXL Memory Expander	1
The Economics of Confrontational Conversation	1
A 10.7-µJ/Frame 88% Accuracy CIFAR-10 Single-Chip Neuromorphic Field-Programmable Gate Array Processor Featuring Various Nonlinear Functions of Dendrites in the Human Cerebrum	1
The Fox and Shepherd Problem	1
Pod-racing: bulk-bitwise to floating-point compute in racetrack memory for machine learning at the edge	1
Online Code Layout Optimizations via OCOLOS	1
TCN-CUTIE: A 1,036-TOp/s/W, 2.72-µJ/Inference, 12.2-mW All-Digital Ternary Accelerator in 22-nm FDX Technology	1
Special Issue on Artificial Intelligence at the Edge	1
Varifocal Storage: Dynamic Multiresolution Data Storage	1
Z80—The 1970s Microprocessor Still Alive	1
Special Issue on Hot Interconnects	1
Economic Dependencies in Integrated Circuits	1
Sustainable AI Processing at the Edge	1
I-DVFS: Instantaneous Frequency Switch During Dynamic Voltage and Frequency Scaling	1
speedAI240: A 2-Petaflop, 30-Teraflops/W At-Memory Inference Acceleration Device With 1456 RISC-V Cores	1
XCRYPT: Accelerating Lattice-Based Cryptography With Memristor Crossbar Arrays	1
The Xbox Series X System Architecture	1
Special Issue on Artificial Intelligence, Edge, and Internet of Things for Smart Agriculture	1
Data Movement Accelerator Engines on a Prototype Power10 Processor	1
BabelFish: Fusing Address Translations for Containers	1
Increasing Throughput of In-Memory DNN Accelerators by Flexible Layerwise DNN Approximation	1
Exploring Memory-Oriented Design Optimization of Edge AI Hardware for Extended Reality Applications	1
A Compressed Spiking Neural Network Onto a Memcapacitive In-Memory Computing Array	1
Biology and Systems Interactions	1
A Hardware/Software Co-Design Vision for Deep Learning at the Edge	1
The 50 Year History of the Microprocessor as Five Technology Eras	1
IEEE Computer Society: Volunteer Service Awards	1
Toward Developing High-Performance RISC-V Processors Using Agile Methodology	1
Characterizing and Mitigating Soft Errors in GPU DRAM	1
Leaking Secrets Through Compressed Caches	1
Warehouse-Scale Video Acceleration	1
Interactions, Impacts, and Coincidences of the First Golden Age of Computer Architecture	1
The Microarchitecture of DOJO, Tesla’s Exa-Scale Computer	1
Masthead	1
On-Device Tiny Machine Learning for Anomaly Detection Based on the Extreme Values Theory	1
Navigating the Seismic Shift of Post-Moore Computer Systems Design	1
DVL-Lossy: Isolating Congesting Flows to Optimize Packet Dropping in Lossy Data-Center Networks	1
Dynamic Capacity Service for Improving CXL Pooled Memory Efficiency	1
Reliable and Time-Efficient Virtualized Function Placement	1
A Brief History of Warehouse-Scale Computing	1
Special Issue on In-Memory Computing	1
Retargetable Optimizing Compilers for Quantum Accelerators via a Multilevel Intermediate Representation	1
Characterizing and Modeling Nonvolatile Memory Systems	1
Vector Runahead for Indirect Memory Accesses	1
Combining Multiple tinyML Models for Multimodal Context-Aware Stress Recognition on Constrained Microcontrollers	1