OOIR: Observatory of International Research

Papers

(The median citation count of IEEE Micro is 0. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-11-01 to 2024-11-01.)

Article	Citations
NVIDIA A100 Tensor Core GPU: Performance and Innovation	160
FerroElectronics for Edge Intelligence	60
The Design Process for Google's Training Chips: TPUv2 and TPUv3	57
PEFL: Deep Privacy-Encoding-Based Federated Learning Framework for Smart Agriculture	52
Near-Memory Processing in Action: Accelerating Personalized Recommendation With AxDIMM	48
FPGA-Based Near-Memory Acceleration of Modern Data-Intensive Applications	40
Kunpeng 920: The First 7-nm Chiplet-Based 64-Core ARM SoC for Cloud Services	38
Chasing Carbon: The Elusive Environmental Footprint of Computing	36
Evolution of the Graphics Processing Unit (GPU)	35
Accelerating Chip Design With Machine Learning	35
A Cloud-Optimized Transport Protocol for Elastic and Scalable HPC	33
Manticore: A 4096-Core RISC-V Chiplet Architecture for Ultraefficient Floating-Point Computing	31
MHADBOR: AI-Enabled Administrative-Distance-Based Opportunistic Load Balancing Scheme for an Agriculture Internet of Things Network	29
Quantum Computers for High-Performance Computing	29
Circuits and Architectures for In-Memory Computing-Based Machine Learning Accelerators	26
Intel Alder Lake CPU Architectures	25
Superconductor Computing for Neural Networks	23
The Path to Successful Wafer-Scale Integration: The Cerebras Story	23
Data Centers on Wheels: Emissions From Computing Onboard Autonomous Vehicles	22
Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing Cores	22
NVIDIA Hopper H100 GPU: Scaling Performance	21
Quantum Computing—From NISQ to PISQ	21
Artificial Intelligence Best Practices in Smart Agriculture	20
PCI Express 6.0 Specification: A Low-Latency, High-Bandwidth, High-Reliability, and Cost-Effective Interconnect With 64.0 GT/s PAM-4 Signaling	18
Challenges and Opportunities for Autonomous Micro-UAVs in Precision Agriculture	18

ML-HW Co-Design of Noise-Robust TinyML Models and Always-On Analog Compute-in-Memory Edge Accelerator	17
On-Demand Mobile CPU Cooling With Thin-Film Thermoelectric Array	16
IBM's POWER10 Processor	16
Memory Pooling With CXL	15
Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion	15
FPGA-Accelerated Quantum Computing Emulation and Quantum Key Distillation	14
Accelerating Neural Network Inference With Processing-in-DRAM: From the Edge to the Cloud	14
Design Tradeoffs in CXL-Based Memory Pools for Public Cloud Platforms	14
The AMD Next-Generation “Zen 3” Core	14
Aquabolt-XL HBM2-PIM, LPDDR5-PIM With In-Memory Processing, and AXDIMM With Acceleration Buffer	14
Accelerator Integration for Open-Source SoC Design	13
Co-Design and System for the Supercomputer “Fugaku”	13
Quantum Codesign	12
An Open Inter-Chiplet Communication Link: Bunch of Wires (BoW)	12
Compute Substrate for Software 2.0	12
Temporal Computing With Superconductors	11
Bridging Python to Silicon: The SODA Toolchain	11
Evaluating Sensor Data Quality in Internet of Things Smart Agriculture Applications	11
A Next-Generation Cryogenic Processor Architecture	11
UAV–Assisted Joint Wireless Power Transfer and Data Collection Mechanism for Sustainable Precision Agriculture in 5G	11
AIDA: Associative In-Memory Deep Learning Accelerator	11
Configurable Network Protocol Accelerator (COPA)	10
Democratizing Data-Driven Agriculture Using Affordable Hardware	10
Hertzbleed: Turning Power Side-Channel Attacks Into Remote Timing Attacks on x86	10
On Double Full-Stack Communication-Enabled Architectures for Multicore Quantum Computers	10
Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Systems	10
Temperature-Resilient RRAM-Based In-Memory Computing for DNN Inference	10
Compute Express Link (CXL): Enabling Heterogeneous Data-Centric Computing With Heterogeneous Memory Hierarchy	10
Three-Dimensional Stacked Neural Network Accelerator Architectures for AR/VR Applications	10
Accelerating ML Recommendation With Over 1,000 RISC-V/Tensor Processors on Esperanto's ET-SoC-1 Chip	9
ILLIXR: An Open Testbed to Enable Extended Reality Systems Research	9
Accelerating Deep Learning Using Interconnect-Aware UCX Communication for MPI Collectives	9
Neuromorphic Near-Sensor Computing: From Event-Based Sensing to Edge Learning	9
A Low-Latency and Low-Power Approach for Coherency and Memory Protocols on PCI Express 6.0 PHY at 64.0 GT/s With PAM-4 Signaling	9
Rome to Milan, AMD Continues Its Tour of Italy	9
System on a Package Innovations With Universal Chiplet Interconnect Express (UCIe) Interconnect	9
ECIM: Exponent Computing in Memory for an Energy-Efficient Heterogeneous Floating-Point DNN Training Processor	9
Marvell ThunderX3: Next-Generation Arm-Based Server Processor	8
Cerebras Architecture Deep Dive: First Look Inside the Hardware/Software Co-Design for Deep Learning	8
Performance Left on the Table: An Evaluation of Compiler Autovectorization for RISC-V	8
TinyIREE: An ML Execution Environment for Embedded Systems From Compilation to Deployment	7
ACCL: Architecting Highly Scalable Distributed Training Systems With Highly Efficient Collective Communication Library	7
CXL-Enabled Enhanced Memory Functions	6
High-Performance Mixed-Low-Precision CNN Inference Accelerator on FPGA	6
The AMD 400-G Adaptive SmartNIC System on Chip: A Technology Preview	6
History of IBM Z Mainframe Processors	6
Advances in Microprocessor Cache Architectures Over the Last 25 Years	6
Kaya for Computer Architects: Toward Sustainable Computer Systems	6
The Arm Morello Evaluation Platform—Validating CHERI-Based Security in a High-Performance System	6
Meet the FaM1ly	6

Power Side-Channel Attacks in Negative Capacitance Transistor	6
AI and Memory Wall	6
History of Microcontrollers: First 50 Years	6
Overclocking in Immersion-Cooled Datacenters	6
Low-Precision Hardware Architectures Meet Recommendation Model Inference at Scale	5
Accelerating Allreduce With In-Network Reduction on Intel PIUMA	5
Balancing Specialized Versus Flexible Computation in Brain–Computer Interfaces	5
POD-RACING: Bulk-Bitwise to Floating-Point Compute in Racetrack Memory for Machine Learning at the Edge	5
The Vision Behind MLPerf: Understanding AI Inference Performance	5
Photonic Network-on-Wafer for Multichiplet GPUs	5
RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures	5
The Microarchitecture of DOJO, Tesla’s Exa-Scale Computer	5
Emerging Technologies for Quantum Computing	5
The Open Domain-Specific Architecture	5
uGEMM: Unary Computing for GEMM Applications	5
Hidden Potential Within Video Game Consoles	5
SMT: Software-Defined Memory Tiering for Heterogeneous Computing Systems With CXL Memory Expander	4
ExHero: Execution History-Aware Error-Rate Estimation in Pipelined Designs	4
Universal Graph-Based Scheduling for Quantum Systems	4
Accelerating Genomic Data Analytics With Composable Hardware Acceleration Framework	4
SpecHLS: Speculative Accelerator Design Using High-Level Synthesis	4
Accessible, FPGA Resource-Optimized Simulation of Multiclock Systems in FireSim	4
Pensando Distributed Services Architecture	4
Soil Fertility Monitoring With Internet of Underground Things: A Survey	4
LSFQ: A Low-Bit Full Integer Quantization for High-Performance FPGA-Based CNN Acceleration	4
Compiling for the IBM Matrix Engine for Enterprise Workloads	4
Optimizing Distributed DNN Training Using CPUs and BlueField-2 DPUs	4
Unifying Spatial Accelerator Compilation With Idiomatic and Modular Transformations	4
Fused Architecture for Dense and Sparse Matrix Processing in TensorFlow Lite	3
HALO: A Hardware–Software Co-Designed Processor for Brain–Computer Interfaces	3
ISOBlue Avena: A Framework for Agricultural Edge Computing and Data Sovereignty	3
The Apollo Guidance Computer	3
Monitoring InfiniBand Networks to React Efficiently to Congestion	3
Novel Composable and Scaleout Architectures Using Compute Express Link	3
Practical and Scalable ML-Driven Cloud Performance Debugging With Sage	3
The Intel Programmable and Integrated Unified Memory Architecture Graph Analytics Processor	3
Efficient Language-Guided Reinforcement Learning for Resource-Constrained Autonomous Systems	3
Architectural CO₂ Footprint Tool: Designing Sustainable Computer Systems With an Architectural Carbon Modeling Tool	3
Artificial-Intelligence-Enhanced Ultrasound Flow Imaging at the Edge	3
On-Device Customization of Tiny Deep Learning Models for Keyword Spotting With Few Examples	3
Failure Tolerant Training With Persistent Memory Disaggregation Over CXL	3
Characterizing and Modeling Nonvolatile Memory Systems	3
Sustainable AI Processing at the Edge	3
Dynamic Capacity Service for Improving CXL Pooled Memory Efficiency	3
A Parallel and Updatable Architecture for FPGA-Based Packet Classification With Large-Scale Rule Sets	3
Countering Load-to-Use Stalls in the NVIDIA Turing GPU	3
Accelerating Finite Field Arithmetic for Homomorphic Encryption on GPUs	3
FPGA Computing	3
Accelerating Phylogenetics Using FPGAs in the Cloud	3
Compiling for Vector Extensions With Stream-Based Specialization	2
Enterprise-Class Multilevel Cache Design: Low Latency, Huge Capacity, and High Reliability	2
A Compressed Spiking Neural Network Onto a Memcapacitive In-Memory Computing Array	2
HPVM: Hardware-Agnostic Programming for Heterogeneous Parallel Systems	2
Microprocessor Advances and the Mainframe Legacy	2
Datacenter-Scale Analysis and Optimization of GPU Machine Learning Workloads	2
PCs Take a Page From Xbox With Pluton	2
Retargetable Optimizing Compilers for Quantum Accelerators via a Multilevel Intermediate Representation	2
A Mobile DNN Training Processor With Automatic Bit Precision Search and Fine-Grained Sparsity Exploitation	2
A Binary Translation Framework for Automated Hardware Generation	2
The Origin of Intel's Micro-Ops	2
TCN-CUTIE: A 1,036-TOp/s/W, 2.72-µJ/Inference, 12.2-mW All-Digital Ternary Accelerator in 22-nm FDX Technology	2
Characterizing and Mitigating Soft Errors in GPU DRAM	2
I-DVFS: Instantaneous Frequency Switch During Dynamic Voltage and Frequency Scaling	2
Hardware Specialization: From Cell to Heterogeneous Microprocessors Everywhere	2
Remote Work	2
Combining Multiple Tiny Machine Learning Models for Multimodal Context-Aware Stress Recognition on Constrained Microcontrollers	2
XCRYPT: Accelerating Lattice-Based Cryptography With Memristor Crossbar Arrays	2
Systematically Understanding Graph Accelerator Dimensions and the Value of Hardware Flexibility	2
Virtual Logical Qubits: A Compact Architecture for Fault-Tolerant Quantum Computing	2
Quantum Computing and the Design of the Ultimate Accelerator	2
Shortages of Integrated Circuits	2
Understanding Acceleration Opportunities at Hyperscale	2
PACMAN: Attacking ARM Pointer Authentication With Speculative Execution	2
Exploring Memory-Oriented Design Optimization of Edge AI Hardware for Extended Reality Applications	2
Analysis of Historical Patenting Behavior and Patent Characteristics of Computer Architecture Companies—Part V: References	2
Distributed Deep Learning With GPU-FPGA Heterogeneous Computing	2
Warehouse-Scale Video Acceleration	1
Interactions, Impacts, and Coincidences of the First Golden Age of Computer Architecture	1
BabelFish: Fusing Address Translations for Containers	1
A 10.7-µJ/Frame 88% Accuracy CIFAR-10 Single-Chip Neuromorphic Field-Programmable Gate Array Processor Featuring Various Nonlinear Functions of Dendrites in the Human Cerebrum	1

Understanding and Characterizing Side Channels Exploiting Phase-Change Memories	1
The Fox and Shepherd Problem	1
Data Movement Accelerator Engines on a Prototype Power10 Processor	1
Analysis of Historical Patenting Behavior and Patent Characteristics of Computer Architecture Companies—Part III: Claims	1
Increasing Throughput of In-Memory DNN Accelerators by Flexible Layerwise DNN Approximation	1
Z80—The 1970s Microprocessor Still Alive	1
A Hardware/Software Co-Design Vision for Deep Learning at the Edge	1
Navigating the Seismic Shift of Post-Moore Computer Systems Design	1
Reliable and Time-Efficient Virtualized Function Placement	1
The Breakthrough Memory Solutions for Improved Performance on LLM Inference	1
EyeCoD: Eye Tracking System Acceleration via FlatCam-Based Algorithm and Hardware Co-Design	1
Economic Dependencies in Integrated Circuits	1
Yin-Yang: Programming Abstractions for Cross-Domain Multi-Acceleration	1
Adversarial Attacks Against Machine Learning-Based Resource Provisioning Systems	1
The Economics of Confrontational Conversation	1
Analysis of Historical Patenting Behavior and Patent Characteristics of Computer Architecture Companies—Part IX: Patent Families	1
Acceleration of a Classic McEliece Postquantum Cryptosystem With Cache Processing	1
Leaking Secrets Through Compressed Caches	1
Vector Runahead for Indirect Memory Accesses	1
On-Device Tiny Machine Learning for Anomaly Detection Based on the Extreme Values Theory	1
Hardware–Software Co-Design for Real-Time Latency–Accuracy Navigation in Tiny Machine Learning Applications	1
DVL-Lossy: Isolating Congesting Flows to Optimize Packet Dropping in Lossy Data-Center Networks	1
Online Code Layout Optimizations via OCOLOS	1
IEEE Computer Society	1
Special Issue on Artificial Intelligence at the Edge	1
Special Issue on Hot Interconnects	1
Addressing the Gap Between Training Data and Deployed Environment by On-Device Learning	1
speedAI240: A 2-Petaflop, 30-Teraflops/W At-Memory Inference Acceleration Device With 1456 RISC-V Cores	1
Early History of Texas Instrument's Digital Signal Processor	1
The Xbox Series X System Architecture	1
Special Issue on Artificial Intelligence, Edge, and Internet of Things for Smart Agriculture	1
Special Issue on Environmentally Sustainable Computing	1
Improving key-value cache performance with heterogeneous memory tiering: A case study of CXL-based memory expansion	1
Masthead	1
Fifty Years of the International Symposium on Computer Architecture: A Data-Driven Retrospective	1
Advancing TinyMLOps: Robust Model Updates in the Internet of Intelligent Vehicles	1
Making Machine Learning More Energy Efficient by Bringing It Closer to the Sensor	1
A Golden-Free Approach to Detect Trojans in COTS Multi-PCB Systems	1
Enabling Artificial Intelligence Supercomputers With Domain-Specific Networks	1
Special Issue on In-Memory Computing	1
A Brief History of Warehouse-Scale Computing	1
IEEE Computer Society: Volunteer Service Awards	1
Toward Developing High-Performance RISC-V Processors Using Agile Methodology	1
The 50 Year History of the Microprocessor as Five Technology Eras	1
An Architecture to Accelerate Computation on Encrypted Data	0
An Incoming World of Decoupling Siliconomy	0
Front Cover	0
Computing Edge	0
From the Memory Lane!	0
Reg-TuneV2: A Hardware-Aware and Multiobjective Regression-Based Fine-Tuning Approach for Deep Neural Networks on Embedded Platforms	0
IEEE TRANSACTIONS ON BIG DATA	0
Subscribe to CiSE Today!	0
IEEE Computer Society Has You Covered!	0
[Front cover]	0
IEEE Computer Society Has You Covered!	0
IT Professional	0
HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols	0
Call for Papers: IEEE Transactions on Computers	0
Review of Patents Issued to Computer Architecture Companies in 2021—Part II	0
Privacy by Memory Design: Visions and Open Problems	0
Call for Papers: IEEE Transactions on Computers	0
Masthead	0
Special Issue on Security and Privacy-Preserving Execution Environments	0
Table of Contents	0
Front Cover	0
Motorola MC68332: One of the First True SoCs	0
NetDistiller: Empowering Tiny Deep Learning via In Situ Distillation	0
IEEE Computer Graphics and Applications	0
IEEE Computer Society Has You Covered!	0
Get Published in the New IEEE Open Journal of the Computer Society	0
IEEE COMPUTER SOCIETY: Call for Papers	0
IEEE Computer Society Jobs Board	0
Masthead	0
Hot Chips 34 and More!	0
IEEE COMPUTER SOCIETY JOBS BOARD	0
COMPUTER: CALL FOR SPECIAL ISSUE PROPOSALS	0
IEEE Computer Society	0
Over the Rainbow: 21st Century Security & Privacy Podcast	0
IEEE Computer Society Jobs Board	0
Watts S. Humphrey Software Quality Award	0
Management of TinyML Enabled Internet of Things Devices	0
IEEE COMPUTER SOCIETY: Call for Papers	0
Computing in Science & Engineering	0
My Computer Journey	0
The Humphrey Award Nominations	0
From Mainframes to Microprocessors	0
IEEE Computer Society Jobs Board	0
The Next Security Frontier: Taking the Mystery Out of the Supply Chain	0
Get Published in the New IEEE Open Journal of the Computer Society	0
Masthead	0
Get Published in the New IEEE Open Journal of the Computer Society	0
Environmentally Sustainable Computing	0
Front Cover	0
Synchronous, Low-Latency, Off-Module Interface for the IBM z16™ Telum® Processor	0
IEEE Computer Society Information	0