Integration-The VLSI Journal

Article	Citations
A novel filter-bank architecture of 2D-FIR symmetry filters using LUT based multipliers	96
Model of a switched-capacitor programmable voltage reference for ultra low-power applications	94
Edge computing design space exploration for heart rate monitoring	59
Editorial Board	49
A new three-dimensional conservative system with non - Hamiltonian energy and its synchronization application	47
Design-for-reliability and on-the-fly fault tolerance procedure for paper-based digital microfluidic biochips with multiple faults	44
A high reliability under-voltage lock out circuit for power driver IC	43
Deep reinforcement learning assisted reticle floorplanning with rectilinear polygon modules for multiple-project wafer	35
Exploring BTI aging effects on spatial power density and temperature profiles of VLSI chips	33
Chaos based speech encryption using microcontroller	31
Emerging monolithic 3D integration: Opportunities and challenges from the computer system perspective	30
Generating pseudo-random numbers with a Brownian system	30
Accelerating large-scale multi-scalar multiplication in Zk-SNARK through exploiting its multilevel parallelism	30
mMIG: Inversion optimization in majority inverter graph with minority operations	28
A general and accurate pattern search method for various scenarios	28
Very compact 3D-printed folded branch-line hybrid coupler based on loaded helical-microstrip transmission lines	24
A transparent virtual channel power gating method for on-chip network routers	24
3-D coarse-grained reconfigurable array using multi-pole NEM relays for programmable routing	23
Design and implementation of virtual-single-length turbo decoder for multi-user parallel decoding	22
Design of high-efficiency complex multiplier for fault-tolerant computation	22
FPGA-based implementation of classification techniques: A survey	22
Plug N’ PIM: An integration strategy for Processing-in-Memory accelerators	22
Complete design approach of a 3rd order continuous-time sigma-delta ADC with FIR feedback and low-noise low-distortion op-amp achieving 101.8 dB SNDR and −110dB THD	19
Design and application of multiscroll chaotic attractors based on memristors	19
An LA-group based design of the non-linear component of block cipher	19

Lightweight encryption mechanism with discrete-time chaotic maps for Internet of Robotic Things	18
HDLBC: A lightweight block cipher with high diffusion	18
A four-dimensional chaotic system with coexisting attractors and its backstepping control and synchronization	17
ProHys PUF: A Proteresis - Hysteresis switch based Physical Unclonable Function	17
Digital synchronization of the MACM chaotic system by using PIC24-microcontrollers and the SPI-protocol	16
Hardware-efficient algorithm and architecture design with memory and complexity reduction for semi-global matching	16
A novel dual mode configurable and tunable high-gain, high-efficient CMOS power amplifier for 5G applications	16
Efficient design of decimation filter using linear programming and its FPGA implementation	16
LQNTL: Low-overhead quadruple-node-upset self-recovery latch based on triple-mode redundancy	15
A 2.69-ppm/°C curvature-compensated BJT-based bandgap voltage reference	15
Synchronization of mutual coupled fractional order one-sided lipschitz systems	15
Design and implementation of congestion aware router for network-on-chip	15
A 6.4-Gbps 0.41-pJ/b fully-digital die-to-die interconnect PHY for silicon interposer based 2.5D integration	14
Design of robust analog integrated circuit based on process corner performance variability minimization	14
Design of Flash analog-to-digital converter based on MoS2 FET	14
Approximate Toom–Cook FFT with sparsity aware error tuning in a shared memory architecture	14
Differential receiver with 2 × VDD input signals using 1 × VDD devices	14
Hardware designs for convolutional neural networks: Memoryful, memoryless and cached	14
Low power chaotic oscillator employing CMOS	14
A new low-power Dynamic-GDI full adder in CNFET technology	13
Hyperchaotic fractional Grassi–Miller map and its hardware implementation	13
Simple memristive chaotic systems with complex dynamics	13
An ant colony based mapping of quantum circuits to nearest neighbor architectures	12
Clock mesh synthesis through dynamic programming with physical parameters consideration	12
Efficient hardware mapping of Boolean substitution boxes based on functional decomposition for RFID and ISM band IoT applications	12
Design of novel low cost triple-node-upset self-recoverable hardened latch	11
Secure access microcontroller system based on fingerprint template with hyperchaotic encryption	11
Nonlinear analysis, circuit implementation, and application in image encryption of a four-dimensional multi-scroll hyper-chaotic system	11
A 20-Gb/s wideband AGC amplifier with 26-dB dynamic range in 0.18-μm SiGe BiCMOS	11
Real-time neural identification using a recurrent wavelet first-order neural network of a chaotic system implemented in an FPAA	11
Neurochaos feature transformation for Machine Learning	11
Matching constraint extraction for analog integrated circuits layout via edge classify	11
An improved algorithm for accelerating reconfiguration of VLSI array	11
FPGA-enhanced system-on-chip for finger vein-based biometric system using novel DL model	10
Designs for efficient low power cardinality and similarity sketches by Two-Step Hashing (TSH)	10
A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications	10
CAPUF: Design of a configurable circular arbiter PUF with enhanced security and hardware efficiency	10
Built-in Self-prevention (BISP) for runtime ageing effects of TSVs in 3D ICs	10
Integrating error correction and detection techniques in RISC-V processor microarchitecture for enhanced reliability	10
LBDR: A load-balanced deadlock-free routing strategy for chiplet systems	10
A 0.2-V 1.2 nW 1-KS/s SAR ADC with a novel comparator structure for biomedical applications	10
Editorial Board	10
Editorial Board	10
A self-control leakage-suppression block for low-power high-efficient static logic circuit design in 22 nm CMOS process	10
A simulation optimization method for Verilog-AMS IBIS model under overclocking	10
Concurrent Steiner Tree Selection for Global routing with EUVL Flare Reduction	10
Approximate digital-in analog-out multiplier with asymmetric nonvolatility and low energy consumption	9
Fast electromigration stress analysis using Low-Rank Balanced Truncation for general interconnect and power grid structures	9
Hot-spot aware thermoelectric array based cooling for multicore processors	9
Alternative method to reveal encoded images via Gaussian distribution functions	9

Symmetric synchronization behavior of multistable chaotic systems and circuits in attractive and repulsive couplings	9
Third-order resonance networks and their application to chaos generation	9
Fixed-point implementations for feed-forward artificial neural networks	9
Preferential fault-tolerance multiplier design to mitigate soft errors in FPGAs	8
Analytic estimation of jitter and eye diagram based on transmission line time domain response considering skin effect and stochastic crosstalk	8
Hardware architecture design for complementary ensemble empirical mode decomposition algorithm	8
Unified chip hardware architecture of KD-tree mean-based trainer and speeding-up classifier with repeat-point searching for various applications	8
AI/ML algorithms and applications in VLSI design and technology	8
Optimizing code allocation for hybrid on-chip memory in IoT systems	8
Novel low leakage and energy efficient dual-pullup/dual-pulldown repeater	8
An improved reconfigurable logic in resistive random access memory	8
JoBiS: Joint capacitance and inductance bit stuffing CAC for interposer based multi-chip Deep Learning Accelerator	8
High level synthesis strategies for ultra fast and low latency matrix inversion implementation for massive MIMO processing	8
Editorial Board	8
Multi-source data fusion technique for parametric fault diagnosis in analog circuits	8
Intelligent and kernelized placement: A survey	8
Comments on “New low power and fast SEC-DAEC and SEC-DAEC-TAEC codes for memories in space application”	7
Editorial Board	7
Editorial Board	7
CompreCity: Accelerating the Traveling Salesman Problem on GPU with data compression	7
The study of TSV-induced and strained silicon-enhanced stress in 3D-ICs	7
High-performance unified modular multiplication algorithm and hardware architecture over G(2m)	7
An optimised hardware architecture of the angular-domain cyclostationary detector for cognitive radio communications	7
Electronic equivalent of a pump-modulated erbium-doped fiber laser	7
BDD-based synthesis approach for in-memory logic realization utilizing Memristor Aided loGIC (MAGIC)	7
MVSym: Efficient symbiotic exploitation of HLS-kernel multi-versioning for collaborative CPU-FPGA cloud systems	7
Editorial Board	7
Picowatt 0.3-V MOS-only voltage reference based on a picoamp cascode current generator	7
A secure scan architecture using parallel latch-based lock	7
A 2.0–2.9 GHz ring-based injection-locked clock multiplier using a self-alignment frequency-tracking loop for reference spur reduction	7
Glitch-less hardware implementation of block ciphers based on an efficient glitch filter	7
Editorial Board	6
A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow	6
A 15.13 mW 3.2 GHz 8-bit carry look-ahead adder using single-phase all-N-transistor logic	6
A low-jitter and low-phase noise switched-loop filter PLL using fast phase-error correction and dual-edge phase comparison technique	6
Machine learning based fast and accurate High Level Synthesis design space exploration: From graph to synthesis	6
Language semantics to support secure computation and communication in embedded systems via hardware monitors	6
High-resolution calibrated successive-approximation-register analog-to-digital converter	6
On-board processing for autonomous drone racing: An overview	6
Digital background calibration algorithm for pipelined ADC based on time-delay neural network with genetic algorithm feature selection	6
Design and analysis of a frequency division and duty cycle control circuit for on-chip signal synthesis	6
An efficient XOR-free implementation of polar encoder for reconfigurable hardware	6
An efficient algorithm for disparity map compression based on spatial correlations and its low-cost hardware architecture	6
Comparison of integer-order chaotic attractors as randomness source in collision-free robotic exploration methods	6
Energy efficient multiply-accumulate unit using novel recursive multiplication for error-tolerant applications	6
Design-time exploration of voltage switching against power analysis attacks in 14 nm FinFET technology	6
An effective routability-driven packing algorithm for large-scale heterogeneous FPGAs	6
A broadband MVDR beamforming core for ultrasound imaging	6
VLFF — A very low-power flip-flop with only two clock transistors	6
A novel low-resource consumption and high-speed hardware implementation of HOG feature extraction on FPGA for human detection	6
A non-degenerate n-dimensional integer domain chaotic map model with application to PRNG	5
Hardware implementation of a robust image cryptosystem using reversible cellular-automata rules and 3-D chaotic systems	5
Design of CMOS fully differential multipath two-stage OTA with boosted slew rate and power efficiency	5
A high-performance convolution block oriented accelerator for MBConv-Based CNNs	5
Design of joint reconfigurable hybrid adder and subtractor using FinFET and GnrFET technologies	5
A very low output resistance and wide-swing class-AB level-shifted folded flipped voltage follower cell	5
An efficient image encryption scheme based on double affine substitution box and chaotic system	5
Approximate squaring circuits exploiting recursive architectures	5
Lorenz system as a filter	5
Design and implementation of current mode circuit for digital modulation	5
Fluid-to-cell assignment and fluid loading on programmable microfluidic devices for bioprotocol execution	5
A frequency boosting technique for cold-start charge pump units	5
A fine-grained mixed precision DNN accelerator using a two-stage big–little core RISC-V MCU	5
Study of the dynamical behavior of an Ikeda-based map with a discrete memristor	5
An energy-efficient image filtering interpolation algorithm using domain-specific dynamic reconfigurable array processor	5
Hardware design for blind source separation using fast time-frequency mask technique	5
Ultra-low power linearized FVF based BD double diffusor double differential pair transconductor	5
A wide-input-range boost converter with three-phase self-start and adaptive zero current detector for photovoltaic energy harvesting	5
An area and power efficient VLSI architecture for ECG feature extraction for wearable IoT healthcare applications	5
Introduction of a new technique for simultaneous reduction of the delay and leakage current in digital circuits	5
Time redundancy and gate sizing soft error-tolerant based adder design	5
A novel class-E class-D doherty power amplifier based on past matching network with linearity region extension and flat output power	5
Nested chopper instrument amplifier with noise modulation for physiological signal sensing	5
An on-chip temperature sensor with 0.5 °C resolution and 0.34% linearity error using 180-nm CMOS process	5
Design of A prototype 128 × 128 ROIC array for 2.6 μm-wavelength SWIR image sensor applications	5
Content-addressable memory using selective-charging and adaptive-discharging scheme for low-power hardware search engine	5
An ultra-wideband low noise amplifier with cascaded flipped-active inductor for cognitive radio applications	5
Automatic correction of RTL designs using a lightweight partial high level synthesis	5
Mixed-radix, virtually scaling-free CORDIC algorithm based rotator for DSP applications	5
FPGA-based Physical Unclonable Functions: A comprehensive overview of theory and architectures	5

Neural network ℒ1	5
Optimal design of mixed dielectric coaxial-annular TSV using GWO algorithm based on artificial neural network	5
Designing efficient FPGA tiles for power-constrained ultra-low-power applications	5
A hybrid memory polynomial digital predistortion model for RF transmitters	5