Integration-The VLSI Journal

Article	Citations
Editorial Board	105
A new three-dimensional conservative system with non - Hamiltonian energy and its synchronization application	103
Design-for-reliability and on-the-fly fault tolerance procedure for paper-based digital microfluidic biochips with multiple faults	63
Deep reinforcement learning assisted reticle floorplanning with rectilinear polygon modules for multiple-project wafer	54
Exploring BTI aging effects on spatial power density and temperature profiles of VLSI chips	51
Edge computing design space exploration for heart rate monitoring	51
A novel filter-bank architecture of 2D-FIR symmetry filters using LUT based multipliers	43
Model of a switched-capacitor programmable voltage reference for ultra low-power applications	39
A high reliability under-voltage lock out circuit for power driver IC	38
Generating pseudo-random numbers with a Brownian system	37
Chaos based speech encryption using microcontroller	36
A general and accurate pattern search method for various scenarios	35
Accelerating large-scale multi-scalar multiplication in Zk-SNARK through exploiting its multilevel parallelism	35
Very compact 3D-printed folded branch-line hybrid coupler based on loaded helical-microstrip transmission lines	30
3-D coarse-grained reconfigurable array using multi-pole NEM relays for programmable routing	29
Plug N’ PIM: An integration strategy for Processing-in-Memory accelerators	26
Design of high-efficiency complex multiplier for fault-tolerant computation	26
Design and implementation of virtual-single-length turbo decoder for multi-user parallel decoding	25
FPGA-based implementation of classification techniques: A survey	24
Emerging monolithic 3D integration: Opportunities and challenges from the computer system perspective	24
Lightweight encryption mechanism with discrete-time chaotic maps for Internet of Robotic Things	24
mMIG: Inversion optimization in majority inverter graph with minority operations	23
Design and application of multiscroll chaotic attractors based on memristors	22
HDLBC: A lightweight block cipher with high diffusion	20
High-robustness CMOS voltage reference for automotive applications with PVT variation tolerance	20

An LA-group based design of the non-linear component of block cipher	20
A transparent virtual channel power gating method for on-chip network routers	20
Complete design approach of a 3rd order continuous-time sigma-delta ADC with FIR feedback and low-noise low-distortion op-amp achieving 101.8 dB SNDR and −110dB THD	20
Hardware-efficient algorithm and architecture design with memory and complexity reduction for semi-global matching	19
ProHys PUF: A Proteresis - Hysteresis switch based Physical Unclonable Function	18
A novel dual mode configurable and tunable high-gain, high-efficient CMOS power amplifier for 5G applications	18
A four-dimensional chaotic system with coexisting attractors and its backstepping control and synchronization	18
A 2.69-ppm/°C curvature-compensated BJT-based bandgap voltage reference	17
LQNTL: Low-overhead quadruple-node-upset self-recovery latch based on triple-mode redundancy	17
Design of Flash analog-to-digital converter based on MoS2 FET	17
Design and implementation of congestion aware router for network-on-chip	16
Synchronization of mutual coupled fractional order one-sided lipschitz systems	16
Efficient CNFET-based ternary logic design with emphasis on half-adder and multiplier circuits	16
Low power chaotic oscillator employing CMOS	16
Clock mesh synthesis through dynamic programming with physical parameters consideration	15
Digital synchronization of the MACM chaotic system by using PIC24-microcontrollers and the SPI-protocol	15
Efficient hardware mapping of Boolean substitution boxes based on functional decomposition for RFID and ISM band IoT applications	15
A 6.4-Gbps 0.41-pJ/b fully-digital die-to-die interconnect PHY for silicon interposer based 2.5D integration	15
Design of novel low cost triple-node-upset self-recoverable hardened latch	14
A 20-Gb/s wideband AGC amplifier with 26-dB dynamic range in 0.18-μm SiGe BiCMOS	14
Hardware designs for convolutional neural networks: Memoryful, memoryless and cached	14
Matching constraint extraction for analog integrated circuits layout via edge classify	14
Approximate Toom–Cook FFT with sparsity aware error tuning in a shared memory architecture	13
Design of robust analog integrated circuit based on process corner performance variability minimization	13
Differential receiver with 2 × VDD input signals using 1 × VDD devices	13
Real-time neural identification using a recurrent wavelet first-order neural network of a chaotic system implemented in an FPAA	13
Fluid-control codesign for paper-based digital biochips using volumetric memory networks: A predictive modelling approach	12
Simple memristive chaotic systems with complex dynamics	12
Hyperchaotic fractional Grassi–Miller map and its hardware implementation	12
Lightweight FPGA acceleration framework for structurally tailored multi-version MobileNetV1	12
Nonlinear analysis, circuit implementation, and application in image encryption of a four-dimensional multi-scroll hyper-chaotic system	12
A novel intrinsic-parameters-correlation enhancement technology applied to accurately extract GaN HEMT small-signal model parameters	12
Neurochaos feature transformation for Machine Learning	12
A new low-power Dynamic-GDI full adder in CNFET technology	12
Designs for efficient low power cardinality and similarity sketches by Two-Step Hashing (TSH)	11
Concurrent Steiner Tree Selection for Global routing with EUVL Flare Reduction	11
Hot-spot aware thermoelectric array based cooling for multicore processors	11
Secure access microcontroller system based on fingerprint template with hyperchaotic encryption	11
Integrating error correction and detection techniques in RISC-V processor microarchitecture for enhanced reliability	11
A 0.2-V 1.2 nW 1-KS/s SAR ADC with a novel comparator structure for biomedical applications	11
Editorial Board	11
Editorial Board	11
A simulation optimization method for Verilog-AMS IBIS model under overclocking	11
Preferential fault-tolerance multiplier design to mitigate soft errors in FPGAs	10
Approximate subtractors designed for image processing applications	10
Symmetric synchronization behavior of multistable chaotic systems and circuits in attractive and repulsive couplings	10
FPGA-enhanced system-on-chip for finger vein-based biometric system using novel DL model	10
Spherical chaotic trajectory tracking and formation of unmanned aerial vehicles in master–slave configuration with intermediary system	10
A self-control leakage-suppression block for low-power high-efficient static logic circuit design in 22 nm CMOS process	10
Approximate digital-in analog-out multiplier with asymmetric nonvolatility and low energy consumption	10

Fixed-point implementations for feed-forward artificial neural networks	10
Fast electromigration stress analysis using Low-Rank Balanced Truncation for general interconnect and power grid structures	10
Built-in Self-prevention (BISP) for runtime ageing effects of TSVs in 3D ICs	10
LBDR: A load-balanced deadlock-free routing strategy for chiplet systems	10
A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications	10
An improved reconfigurable logic in resistive random access memory	10
Unified chip hardware architecture of KD-tree mean-based trainer and speeding-up classifier with repeat-point searching for various applications	10
Multi-source data fusion technique for parametric fault diagnosis in analog circuits	10
CAPUF: Design of a configurable circular arbiter PUF with enhanced security and hardware efficiency	10
The effect of ECG data variability on side-channel attack success rate in wearable devices	10
Alternative method to reveal encoded images via Gaussian distribution functions	10
AI/ML algorithms and applications in VLSI design and technology	9
Editorial Board	9
Robust optimization algorithm of RF MEMS switches considering uncertainties	9
High-performance unified modular multiplication algorithm and hardware architecture over G(2m)	9
Editorial Board	9
CompreCity: Accelerating the Traveling Salesman Problem on GPU with data compression	9
Third-order resonance networks and their application to chaos generation	9
JoBiS: Joint capacitance and inductance bit stuffing CAC for interposer based multi-chip Deep Learning Accelerator	9
Editorial Board	9
Intelligent and kernelized placement: A survey	9
The study of TSV-induced and strained silicon-enhanced stress in 3D-ICs	8
A hybrid entropy source scheme for true random number generator	8
A 2.0–2.9 GHz ring-based injection-locked clock multiplier using a self-alignment frequency-tracking loop for reference spur reduction	8
An effective routability-driven packing algorithm for large-scale heterogeneous FPGAs	8
An efficient XOR-free implementation of polar encoder for reconfigurable hardware	8
High level synthesis strategies for ultra fast and low latency matrix inversion implementation for massive MIMO processing	8
Design and analysis of faithful parallel mean filter using approximate adders and 4:2 compressors for low-power VLSI architectures	8
Electronic equivalent of a pump-modulated erbium-doped fiber laser	8
MVSym: Efficient symbiotic exploitation of HLS-kernel multi-versioning for collaborative CPU-FPGA cloud systems	8
Digital background calibration algorithm for pipelined ADC based on time-delay neural network with genetic algorithm feature selection	8
An optimised hardware architecture of the angular-domain cyclostationary detector for cognitive radio communications	8
Design and analysis of a frequency division and duty cycle control circuit for on-chip signal synthesis	8
Innovative nonlinear component generator inspired by squirrel search algorithm	8
ANAS: Software–hardware co-design of approximate neural network accelerators via neural architecture search	8
BDD-based synthesis approach for in-memory logic realization utilizing Memristor Aided loGIC (MAGIC)	8
Picowatt 0.3-V MOS-only voltage reference based on a picoamp cascode current generator	8
On-board processing for autonomous drone racing: An overview	8
Analytic estimation of jitter and eye diagram based on transmission line time domain response considering skin effect and stochastic crosstalk	8
Language semantics to support secure computation and communication in embedded systems via hardware monitors	7
Approximate squaring circuits exploiting recursive architectures	7
A novel low-resource consumption and high-speed hardware implementation of HOG feature extraction on FPGA for human detection	7
Editorial Board	7
Energy efficient multiply-accumulate unit using novel recursive multiplication for error-tolerant applications	7
Hardware architecture design for complementary ensemble empirical mode decomposition algorithm	7
Machine learning based fast and accurate High Level Synthesis design space exploration: From graph to synthesis	7
Comments on “New low power and fast SEC-DAEC and SEC-DAEC-TAEC codes for memories in space application”	7
Glitch-less hardware implementation of block ciphers based on an efficient glitch filter	7
High-resolution calibrated successive-approximation-register analog-to-digital converter	7
An area and power efficient VLSI architecture for ECG feature extraction for wearable IoT healthcare applications	7
Optimal design of mixed dielectric coaxial-annular TSV using GWO algorithm based on artificial neural network	7
A hybrid memory polynomial digital predistortion model for RF transmitters	7
A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow	7
Design-time exploration of voltage switching against power analysis attacks in 14 nm FinFET technology	7
A low-jitter and low-phase noise switched-loop filter PLL using fast phase-error correction and dual-edge phase comparison technique	7
Resource-efficient and ultra-high throughput LDPC decoder for CCSDS near-earth standard	7
Comparison of integer-order chaotic attractors as randomness source in collision-free robotic exploration methods	7
An efficient algorithm for disparity map compression based on spatial correlations and its low-cost hardware architecture	7
Lorenz system as a filter	7
Neural network ℒ1	7
A 15.13 mW 3.2 GHz 8-bit carry look-ahead adder using single-phase all-N-transistor logic	7
A broadband MVDR beamforming core for ultrasound imaging	7
A secure scan architecture using parallel latch-based lock	7
Optimizing code allocation for hybrid on-chip memory in IoT systems	7
VLFF — A very low-power flip-flop with only two clock transistors	7
A fine-grained mixed precision DNN accelerator using a two-stage big–little core RISC-V MCU	6
Electronically tunable floating DXCCDITA-based universal memelement emulator and its applications	6
Ultra-low power linearized FVF based BD double diffusor double differential pair transconductor	6
Content-addressable memory using selective-charging and adaptive-discharging scheme for low-power hardware search engine	6
Hardware design for blind source separation using fast time-frequency mask technique	6
An area and power efficient VLSI architecture for epileptic seizure detection using Transpose Form Retimed Delayed LMS filter and spiking neural networks	6
FPGA-based Physical Unclonable Functions: A comprehensive overview of theory and architectures	6
Design of A prototype 128 × 128 ROIC array for 2.6 μm-wavelength SWIR image sensor applications	6
An ultra-wideband low noise amplifier with cascaded flipped-active inductor for cognitive radio applications	6
A frequency boosting technique for cold-start charge pump units	6
Automatic correction of RTL designs using a lightweight partial high level synthesis	6
A novel class-E class-D doherty power amplifier based on past matching network with linearity region extension and flat output power	6
A wide-input-range boost converter with three-phase self-start and adaptive zero current detector for photovoltaic energy harvesting	6
An efficient image encryption scheme based on double affine substitution box and chaotic system	6
Integration mixer: An efficient mixed neural network for memory dynamic stability analysis in high dimensional variation space	5

A high-performance convolution block oriented accelerator for MBConv-Based CNNs	5
Chosen ciphertext correlation power analysis on Kyber	5
Design of CMOS VCO with XNOR and transmission gate based delay stages	5
Lorenz system manufacturing with a Butterworth filter	5
A logic device based on memristor-diode crossbar and CMOS periphery as spike router for hardware neural network	5
High-throughput and area-efficient architectures for image encryption using PRINCE cipher	5
Novel fault tolerance topology using corvus seek algorithm for application specific NoC	5
Novel hybrid TFET-FinFET 12T SRAM cells with enhanced write margin and read performance	5
Hardware implementation of a robust image cryptosystem using reversible cellular-automata rules and 3-D chaotic systems	5
Study of the dynamical behavior of an Ikeda-based map with a discrete memristor	5
A very low output resistance and wide-swing class-AB level-shifted folded flipped voltage follower cell	5
Design of joint reconfigurable hybrid adder and subtractor using FinFET and GnrFET technologies	5
Design and application of CMOS active inductor in bandpass filter and VCO for reconfigurable RF front-end	5
A fast and high-performance global router with enhanced congestion control	5
An on-chip temperature sensor with 0.5 °C resolution and 0.34% linearity error using 180-nm CMOS process	5
A precision programmable multilevel voltage output and low-temperature-variation CMOS bandgap reference with area-efficient transistor-array layout	5
Editorial Board	5
BonnLogic: Delay optimization by And-Or Path restructuring	5
156 dB low-voltage low-power CMOS exponential function generator circuit	5
A non-degenerate n-dimensional integer domain chaotic map model with application to PRNG	5
An energy-efficient image filtering interpolation algorithm using domain-specific dynamic reconfigurable array processor	5
A low power offset voltage calibration method for flash ADCs	5
Nested chopper instrument amplifier with noise modulation for physiological signal sensing	5
Integrated DC - DC converter design methodology for design cycle speed up	5
A high-efficiency feedforward compensation method for capacitor-less LDO	5
Design of CMOS fully differential multipath two-stage OTA with boosted slew rate and power efficiency	5
Compact MAX and MIN Stochastic Computing architectures	5
Novel logic and memory synthesis algorithm for Memristive Hardware Description Language (HDL)	5