Integration-The VLSI Journal

Article	Citations
A new multi-scroll Chua’s circuit with composite hyperbolic tangent-cubic nonlinearity: Complex dynamics, Hardware implementation and Image encryption application	75
Defense-in-depth: A recipe for logic locking to prevail	44
Review: Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test	42
A new adaptive selection strategy for reducing latency in networks on chip	40
A novel dual mode configurable and tunable high-gain, high-efficient CMOS power amplifier for 5G applications	37
Dynamics analysis, FPGA realization and image encryption application of a 5D memristive exponential hyperchaotic system	34
A survey on fault injection methods of digital integrated circuits	31
Vulnerable objects detection for autonomous driving: A review	30
Secure image encryption scheme using 4D-Hyperchaotic systems based reconfigurable pseudo-random number generator and S-Box	29
FPGA-based Physical Unclonable Functions: A comprehensive overview of theory and architectures	28
MOS based pseudo-resistors exhibiting Tera Ohms of Incremental Resistance for biomedical applications: Analysis and proof of concept	26
Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework	22
A two-directional grid multiscroll hidden attractor based on piecewise linear system and its application in pseudo-random bit generator	20
Cryptanalysis of nonlinear confusion component based encryption algorithm	18
A fast approach for bitcoin blockchain cryptocurrency mining system	17
Design of hyperchaotic system based on multi-scroll and its encryption algorithm in color image	17
A new 4D Memristor chaotic system: Analysis and implementation	16
Experimental verification of the multi-scroll chaotic attractors synchronization in PWL arbitrary-order systems using direct coupling and passivity-based control	16
FPGA implementation of high-performance, resource-efficient Radix-16 CORDIC rotator based FFT algorithm	16
Verification of physical designs using an integrated reverse engineering flow for nanoscale technologies	16
FPGA implementation of a chaotic oscillator with odd/even symmetry and its application	16
An efficient memristor crossbar architecture for mapping Boolean functions using Binary Decision Diagrams (BDD)	15
Realizations of fractional-order PID loop-shaping controller for mechatronic applications	13
An efficient image encryption scheme based on double affine substitution box and chaotic system	13
Constructing keyed strong S-Box with higher nonlinearity based on 2D hyper chaotic map and algebraic operation	13

A comprehensive analysis on the resilience of adiabatic logic families against transient faults	13
RESET: A real-time scheduler for energy and temperature aware heterogeneous multi-core systems	13
Approximate multipliers based on a novel unbiased approximate 4-2 compressor	13
FPGA-based implementation of classification techniques: A survey	13
Electronically tunable third-order dual-mode quadrature sinusoidal oscillators employing VDCCs and all grounded components	12
A Novel four - Wing chaotic system with multiple attractors based on hyperbolic sine: Application to image encryption*	12
Compact and efficient structure of 8-bit S-box for lightweight cryptography	12
Coexistence of infinite attractors in a fractional-order chaotic system with two nonlinear functions and its DSP implementation	12
High-performance area-efficient polynomial ring processor for CRYSTALS-Kyber on FPGAs	12
On malicious implants in PCBs throughout the supply chain	12
A novel memristive chaotic system without any equilibrium point	11
On-board processing for autonomous drone racing: An overview	11
Hyperchaotic fractional Grassi–Miller map and its hardware implementation	11
A bulk-driven quasi-floating gate FVF current mirror for low voltage, low power applications	11
A Survey of FIR Filter Design Techniques: Low-complexity, Narrow Transition-band and Variable Bandwidth	11
A memristive chaotic system with rich dynamical behavior and circuit implementation	11
Accelerating Deep Convolutional Neural Network base on stochastic computing	10
High-performance hardware architecture of a robust block-cipher algorithm based on different chaotic maps and DNA sequence encoding	10
A low latency modular-level deeply integrated MFCC feature extraction architecture for speech recognition	10
Analysis of SRAM metrics for data dependent BTI degradation and process variability	10
Multi-source data fusion technique for parametric fault diagnosis in analog circuits	10
A novel current-controlled memristor-based chaotic circuit	10
Design of novel SMS4-BSK encryption transmission system	10
Design automation for continuous-flow microfluidic biochips: A comprehensive review	10
Power density aware application mapping in mesh-based network-on-chip architecture: An evolutionary multi-objective approach	10
A robust and automated methodology for the analysis of Time-Dependent Variability at transistor level	9
Mixed-radix, virtually scaling-free CORDIC algorithm based rotator for DSP applications	9
Logarithm-approximate floating-point multiplier is applicable to power-efficient neural network training	9
VLSI mask optimization: From shallow to deep learning	9
Improving power analysis attack resistance using intrinsic noise in 3D ICs	9
Low power chaotic oscillator employing CMOS	9
A non-autonomous chaotic system with no equilibrium	9
Machine learning and structural characteristics for reverse engineering	9
Design space exploration of low-power flip-flops in FinFET technology	9
A new hardware Trojan detection technique using deep convolutional neural network	9
Real-time medical image encryption for H-IoT applications using improved sequences from chaotic maps	9
New lightweight Anti-SAT block design and obfuscation technique to thwart removal attack	8
An efficient background calibration technique for analog-to-digital converters based on neural network	8
Methods increasing inherent resistance of ECC designs against horizontal attacks	8
Flipped voltage follower based fourth order filter and its application to portable ECG acquisition system	8
A transformer with high coupling coefficient and small area based on TSV	7
High-throughput and area-efficient architectures for image encryption using PRINCE cipher	7
A chaotic PRNG tested with the heuristic Differential Evolution	7
Design of a real-time face detection architecture for heterogeneous systems-on-chips	7
A formal model for proving hardware timing properties and identifying timing channels	7
A new low-power Dynamic-GDI full adder in CNFET technology	7
The Involution Tool for Accurate Digital Timing and Power Analysis	7
A survey on machine learning-based routing for VLSI physical design	7
An effective watermarking technique using BTC and SVD for image authentication and quality recovery	7
Proposal and analysis of relative stability in mixed CNT bundle for sub-threshold interconnects	7

New memristor-less, resistor-less, two-OTA based grounded and floating meminductor emulators and their applications in chaotic oscillators	6
Efficient design of magnitude and 2's complement comparators	6
WDP-BNN: Efficient wafer defect pattern classification via binarized neural network	6
Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient Challenge–Response pair acquisition using Built-In Self-Test before shipping	6
Experimental study of terrain coverage of an autonomous chaotic mobile robot	6
Simulated annealing assisted NSGA-III-based multi-objective analog IC sizing tool	6
A 0.3nV/√Hz input-referred-noise analog front-end for radiation-induced thermo-acoustic pulses	6
A four-dimensional chaotic system with coexisting attractors and its backstepping control and synchronization	6
Convex optimization of random dynamic voltage and frequency scaling against power attacks	6
Quantization aware approximate multiplier and hardware accelerator for edge computing of deep learning applications	6
Agile-AES: Implementation of configurable AES primitive with agile design approach	6
On the superiority of modularity-based clustering for determining placement-relevant clusters	6
Breaking LPA-resistant cryptographic circuits with principal component analysis	6
Chaotic encryption of real-time ECG signal in embedded system for secure telemedicine	6
Study of the dynamical behavior of an Ikeda-based map with a discrete memristor	6
2.3–21 GHz broadband and high linearity distributed low noise amplifier	6
An area and power efficient VLSI architecture for ECG feature extraction for wearable IoT healthcare applications	6
Application driven routing for mesh based Network-on-Chip architectures	6
Avoidance vs. repair: New approaches to increasing electromigration robustness in VLSI routing	6
A broadband MVDR beamforming core for ultrasound imaging	5
Batch generating keyed strong S-Boxes with high nonlinearity using 2D hyper chaotic map	5
Novel gate-overlap tunnel FET based innovative ultra-low-power ternary flash ADC	5
An improved algorithm for accelerating reconfiguration of VLSI array	5
An Enhanced Memetic Algorithm using SKB tree representation for fixed-outline and temperature driven non-slicing floorplanning	5
PV-MAC: Multiply-and-accumulate unit structure exploiting precision variability in on-device convolutional neural networks	5
Emerging monolithic 3D integration: Opportunities and challenges from the computer system perspective	5
An efficient multiple shortest augmenting paths algorithm for constructing high performance VLSI subarray	5
Sizing of multi-stage Op Amps by combining design equations with the gm/ID method	5
Machine learning classification algorithm for VLSI test cost reduction	5
TRACK: An algorithm for fault-tolerant, dynamic and scalable 2D mesh network-on-chip routing reconfiguration	5
Reliable and low power Negative Capacitance Junctionless FinFET based 6T SRAM cell	5
High speed VLSI architecture for improved region based active contour segmentation technique	5
A 0.6V 44.6 ppm/ºC subthreshold CMOS voltage reference with wide temperature range and inherent leakage compensation	5
Invasive weed optimization based scheduling for digital microfluidic biochip operations	5
Valid test pattern identification for VLSI adaptive test	5
A new family of CMOS inverter-based OTAs for biomedical and healthcare applications	5
Test patterns reordering method based on Gamma distribution	5
Neurochaos feature transformation for Machine Learning	5
Efficient design of decimation filter using linear programming and its FPGA implementation	5
Passivity-based non-fragile control of a class of uncertain fractional-order nonlinear systems	5
A novel tunable gain CMOS buffer amplifier for large resistive loads	5
Low-power content addressable memory design using two-layer P-N match-line control and sensing	4
An improved heuristic technique for nearest neighbor realization of quantum circuits in 2D architecture	4
Design and analysis of a flat gain and linear low noise amplifier using modified current reused structure with feedforward structure	4
Machine learning based fast and accurate High Level Synthesis design space exploration: From graph to synthesis	4
Design of FIR filter ISOTA with the aid of genetic algorithm	4
Investigating the influence of adiabatic load on the 4-phase adiabatic system design	4
Statistical traffic pattern for mixed torus topology and pathfinder based traffic and thermal aware routing protocol on NoC	4
Secure access microcontroller system based on fingerprint template with hyperchaotic encryption	4
Research progress of time-interleaved analog-to-digital converters	4
Fluid-to-cell assignment and fluid loading on programmable microfluidic devices for bioprotocol execution	4
FPGA-based parallel implementation to classify Hyperspectral images by using a Convolutional Neural Network	4
Hw/Sw Co-Design technique for 2D fast fourier transform algorithm on Zynq SoC	4
Radiation-aware analog circuit design via fully-automated simulation environment	4
Graph-based STA for asynchronous controllers	4
Real-time infrared small target detection network and accelerator design	4
Monolithic 3D stacked multiply-accumulate units	4
PCoSA: A product error correction code for use in memory devices targeting space applications	4
Novel tunable current feedback instrumentation amplifier based on BBFC OP-AMP for biomedical applications with low power and high CMRR	4
Integrated DC - DC converter design methodology for design cycle speed up	4
A very low output resistance and wide-swing class-AB level-shifted folded flipped voltage follower cell	4
Design and implementation of current mode circuit for digital modulation	4
An efficient and reliable MRF-based methodology for designing low-power VLSI circuits	4
Litho-NeuralODE 2.0: Improving hotspot detection accuracy with advanced data augmentation, DCT-based features, and neural ordinary differential equations	4
Design of highly reliable radiation hardened 10T SRAM cell for low voltage applications	4
Transmission synchronization of multiple memristor chaotic circuits via single input controller and its application in secure communication	4
Multicast-enabled network-on-chip routers leveraging partitioned allocation and switching	4
A DRV-based bit selection method for SRAM PUF key generation and its impact on ECCs	4
A PVT aware differential delay circuit and its performance variation due to power supply noise	4
A fast transient response current-feedback low-dropout regulator with dynamic current-enhancement technique	4
A transparent virtual channel power gating method for on-chip network routers	4
A split-based fully digital feedforward background calibration technique for timing mismatch in TIADC	3
Custom NoC topology generation using Discrete Antlion Trapping Mechanism	3
Building discrete maps with memristor and multiple nonlinear terms	3
Mathematical analysis and circuit emulator design of the three-valued memristor	3
Designing efficient FPGA tiles for power-constrained ultra-low-power applications	3
Picowatt 0.3-V MOS-only voltage reference based on a picoamp cascode current generator	3
An optimal analytical solution for maximizing expected battery lifetime using the calculus of variations	3
READ: A fixed restoring array based accuracy-configurable approximate divider for energy efficiency	3
Development of micro computer based mobile random number generator with an encryption application	3

Hardware implementation of a robust image cryptosystem using reversible cellular-automata rules and 3-D chaotic systems	3
VDTA and DO-CCII based incremental/decremental floating memductance/meminductance simulator: A novel realization	3
A novel systolic array processor with dynamic dataflows	3
On circuit developments to enable large scale circuit design while computing with noise	3
An accelerated modulus-based matrix splitting iteration method for mixed-size cell circuits legalization	3
An innovative two-stage data compression scheme using adaptive block merging technique	3
HashHeat: A hashing-based spatiotemporal filter for dynamic vision sensor	3
DULBC: A dynamic ultra-lightweight block cipher with high-throughput	3
New low power and fast SEC-DAEC and SEC-DAEC-TAEC codes for memories in space application	3
A CMOS rectified linear unit operating in weak inversion for memristive neuromorphic circuits	3
A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications	3
A functional block decomposition method for automatic op-amp design	3
Low power time-domain rail-to-rail comparator with a new delay element for ADC applications	3
Verification and revision of the power-down mode for hierarchical analog circuits	3
Grammar-based fuzz testing for microprocessor RTL design	3
Low voltage fully differential OTA using DTMOS based self cascode transistor with slew-rate enhancement and its filter application	3
High-throughput architecture for post-quantum DME cryptosystem	3
Improved thermal network modeling of die stacking DRAM and optimization	3
A passive and low-complexity Compressed Sensing architecture based on a charge-redistribution SAR ADC	3
Neural network ℒ1	3
An energy efficient synthesis flow for application specific SoC design	3
A self-control leakage-suppression block for low-power high-efficient static logic circuit design in 22 nm CMOS process	3
An efficient NBTI-aware wake-up strategy: Concept, design, and manipulation	3
Mixed-cell-height legalization considering complex minimum width constraints and half-row fragmentation effect	3
An energy-efficient single-cycle RV32I microprocessor for edge computing applications	3
Efficient FPGA implementation of RNS Montgomery multiplication using balanced RNS bases	3
Complex exponential functions: A high-precision hardware realization	3
A fast piecewise image encryption scheme combining NC1DNSM and P-Box	2
Modeling and design of 3-D MPPT for ultra low power RF energy harvesters	2
Power-aware hold optimization for ASIC physical synthesis	2
Highly stable soft-error immune SRAM with multi-node upset recovery for aerospace applications	2
A High Performance Early Acknowledged Asynchronous Pipeline using Hybrid-logic Encoding	2
OPCoSA: an Optimized Product Code for space applications	2
High-performance multiply-accumulate unit by integrating binary carry select adder and counter-based modular wallace tree multiplier for embedding system	2
Fast algorithms for test optimization of core based 3D SoC	2
Novel fault tolerance topology using corvus seek algorithm for application specific NoC	2
Heterogenous ensemble learning driven multi-parametric assessment model for hardware Trojan detection	2
A precision programmable multilevel voltage output and low-temperature-variation CMOS bandgap reference with area-efficient transistor-array layout	2
An ultra-wideband 6–14 GHz frequency modulated continuous wave primary radar with 3 cm range resolution	2
DCNN search and accelerator co-design: Improve the adaptability between NAS frameworks and embedded platforms	2
The synthesis method of logic circuits based on the iMemComp gates	2
An efficient construction of S-box based on the fractional-order Rabinovich–Fabrikant chaotic system	2
Synthesis of representative critical path circuits considering BEOL variations for deep sub-micron circuits	2
COPRICSI: COnstraint-PRogrammed Initial Circuit SIzing	2
The study of TSV-induced and strained silicon-enhanced stress in 3D-ICs	2
A high-efficiency feedforward compensation method for capacitor-less LDO	2
Chosen ciphertext correlation power analysis on Kyber	2
Design of a low-power CMOS transceiver for semi-passive wireless sensor network application	2
A new realization scheme for dynamic PFSCL style	2
A high-performance convolution block oriented accelerator for MBConv-Based CNNs	2
A hybrid method for signal probability and reliability estimation with combinational circuits	2
A sequential strong PUF architecture based on reconfigurable neural networks (RNNs) against state-of-the-art modeling attacks	2
Efficient hardware implementations of lightweight Simeck Cipher for resource-constrained applications	2
Boundary scan based interconnect testing design for silicon interposer in 2.5D ICs	2
A Sub-1 V nanopower subthreshold current and voltage reference using current subtraction technique and cascoded active load	2
A 0.2-V 1.2 nW 1-KS/s SAR ADC with a novel comparator structure for biomedical applications	2
On the quadrature accuracy of in-phase coupled quadrature LC oscillator	2
Design and implementation of SVM OTPC searching based on Shared Dot Product Matrix	2
Introduction of a new technique for simultaneous reduction of the delay and leakage current in digital circuits	2
An automated parallel simulation flow for cyber-physical system design	2
Electronically tunable positive and negative fractional order inductor circuit using single topology	2
A survey on attack vectors in stack cache memory	2
Edge computing design space exploration for heart rate monitoring	2
Low-power and high-speed SRAM cells for double-node-upset recovery	2
High level synthesis strategies for ultra fast and low latency matrix inversion implementation for massive MIMO processing	2
Design and application of CMOS active inductor in bandpass filter and VCO for reconfigurable RF front-end	2
On reverse converters for arbitrary multi-moduli RNS	2
Design of an ultra-wideband LNA using transformer matching method	2
Deep learning aided efficient yield analysis for multi-objective analog integrated circuit synthesis	2
Performance-aware predictive-model-based on-chip body-bias regulation strategy for an ULP multi-core cluster in 28 nm UTBB FD-SOI	2
A CMOS transimpedance amplifier with broad-band and high gain based on negative Miller capacitance	2
High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic	2
Resource allocation applied to flexible printed circuit routing based on constrained Delaunay triangulation	2
A cellular automata guided two level obfuscation of Finite-State-Machine for IP protection	2
A novel approach to fractional-N PLLs generating ultra-fast low-noise chirps for FMCW radar	2
Synchronization of fractional-order chaotic networks in Presnov form via homogeneous controllers	2
High quality hypergraph partitioning for logic emulation	2
VLSI architecture design and implementation of 5/3 and 9/7 lifting Discrete Wavelet Transform	2
A robust Euclidean metric based ID extraction method using RO-PUFs in FPGA	2
Hot-spot aware thermoelectric array based cooling for multicore processors	2
A novel filter-bank architecture of 2D-FIR symmetry filters using LUT based multipliers	2
An ant colony based mapping of quantum circuits to nearest neighbor architectures	2
Electronic equivalent of a pump-modulated erbium-doped fiber laser	2
A 20-Gb/s wideband AGC amplifier with 26-dB dynamic range in 0.18-μm SiGe BiCMOS	2
A 85dB-SNDR 50 kHz bootstrapping-free resistor-less SC Delta-Sigma modulator IP block for PVT-robust low-power ADCs	1
A low offset low power CMOS dynamic comparator for analog to digital converters	1
Design of an adaptive winner takes all circuit explaining features of binocular rivalry in visual brain	1
Novel low leakage and energy efficient dual-pullup/dual-pulldown repeater	1
Test and diagnosis pattern generation for distinguishing stuck-at faults and bridging faults	1
A low-jitter and low-phase noise switched-loop filter PLL using fast phase-error correction and dual-edge phase comparison technique	1
Low power, high speed approximate multiplier for error resilient applications	1
Hardware architecture design for complementary ensemble empirical mode decomposition algorithm	1
Robust power grid network design considering EM aging effects for multi-segment wires	1
A highly-linear, sub-mW LNA at 2.4 GHz in 40 nm CMOS process	1
Design-time exploration of voltage switching against power analysis attacks in 14 nm FinFET technology	1