Integration-The VLSI Journal

Article	Citations
A new three-dimensional conservative system with non - Hamiltonian energy and its synchronization application	108
Editorial Board	68
A high reliability under-voltage lock out circuit for power driver IC	62
Deep reinforcement learning assisted reticle floorplanning with rectilinear polygon modules for multiple-project wafer	43
Design-for-reliability and on-the-fly fault tolerance procedure for paper-based digital microfluidic biochips with multiple faults	41
Exploring BTI aging effects on spatial power density and temperature profiles of VLSI chips	41
Edge computing design space exploration for heart rate monitoring	41
Model of a switched-capacitor programmable voltage reference for ultra low-power applications	39
Generating pseudo-random numbers with a Brownian system	37
Chaos based speech encryption using microcontroller	35
Low-power hardware architecture of optimized logarithmic square rooter with enhanced error compensation for error-tolerant systems	30
A novel filter-bank architecture of 2D-FIR symmetry filters using LUT based multipliers	30
Accelerating large-scale multi-scalar multiplication in Zk-SNARK through exploiting its multilevel parallelism	27
Design and application of multiscroll chaotic attractors based on memristors	27
A general and accurate pattern search method for various scenarios	26
A transparent virtual channel power gating method for on-chip network routers	25
High-robustness CMOS voltage reference for automotive applications with PVT variation tolerance	25
HDLBC: A lightweight block cipher with high diffusion	24
Design and implementation of virtual-single-length turbo decoder for multi-user parallel decoding	21
3-D coarse-grained reconfigurable array using multi-pole NEM relays for programmable routing	21
Plug N’ PIM: An integration strategy for Processing-in-Memory accelerators	20
An LA-group based design of the non-linear component of block cipher	20
Design of high-efficiency complex multiplier for fault-tolerant computation	20
Very compact 3D-printed folded branch-line hybrid coupler based on loaded helical-microstrip transmission lines	20
Complete design approach of a 3rd order continuous-time sigma-delta ADC with FIR feedback and low-noise low-distortion op-amp achieving 101.8 dB SNDR and −110dB THD	19

Lightweight encryption mechanism with discrete-time chaotic maps for Internet of Robotic Things	18
Emerging monolithic 3D integration: Opportunities and challenges from the computer system perspective	17
Efficient processor verification by tautologies-derived universal properties model checking	17
Hardware-efficient algorithm and architecture design with memory and complexity reduction for semi-global matching	16
Design insights for implementing a PRNG with fractional Lorenz system on ESP32 and FPGA	16
Design of Flash analog-to-digital converter based on MoS2 FET	15
Design and implementation of congestion aware router for network-on-chip	15
A 2.69-ppm/°C curvature-compensated BJT-based bandgap voltage reference	15
A novel dual mode configurable and tunable high-gain, high-efficient CMOS power amplifier for 5G applications	15
LQNTL: Low-overhead quadruple-node-upset self-recovery latch based on triple-mode redundancy	15
Low power chaotic oscillator employing CMOS	14
A four-dimensional chaotic system with coexisting attractors and its backstepping control and synchronization	14
Error expectation-driven design and energy optimization of approximate multipliers	14
ProHys PUF: A Proteresis - Hysteresis switch based Physical Unclonable Function	14
Digital synchronization of the MACM chaotic system by using PIC24-microcontrollers and the SPI-protocol	14
Efficient CNFET-based ternary logic design with emphasis on half-adder and multiplier circuits	14
Differential receiver with 2 × VDD input signals using 1 × VDD devices	13
Matching constraint extraction for analog integrated circuits layout via edge classify	13
Approximate Toom–Cook FFT with sparsity aware error tuning in a shared memory architecture	13
Efficient hardware mapping of Boolean substitution boxes based on functional decomposition for RFID and ISM band IoT applications	13
Clock mesh synthesis through dynamic programming with physical parameters consideration	13
Hardware designs for convolutional neural networks: Memoryful, memoryless and cached	13
Fluid-control codesign for paper-based digital biochips using volumetric memory networks: A predictive modelling approach	13
Nonlinear analysis, circuit implementation, and application in image encryption of a four-dimensional multi-scroll hyper-chaotic system	12
Simple memristive chaotic systems with complex dynamics	12
Low-	12
Area-efficient architectures of Midori lightweight block cipher for resource constrained devices	12
A 6.4-Gbps 0.41-pJ/b fully-digital die-to-die interconnect PHY for silicon interposer based 2.5D integration	12
Design of robust analog integrated circuit based on process corner performance variability minimization	12
A novel intrinsic-parameters-correlation enhancement technology applied to accurately extract GaN HEMT small-signal model parameters	12
Secure access microcontroller system based on fingerprint template with hyperchaotic encryption	11
Design of novel low cost triple-node-upset self-recoverable hardened latch	11
Editorial Board	11
CAPUF: Design of a configurable circular arbiter PUF with enhanced security and hardware efficiency	11
Real-time neural identification using a recurrent wavelet first-order neural network of a chaotic system implemented in an FPAA	11
Neurochaos feature transformation for Machine Learning	11
A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications	11
Editorial Board	11
Lightweight FPGA acceleration framework for structurally tailored multi-version MobileNetV1	11
A new low-power Dynamic-GDI full adder in CNFET technology	11
Built-in Self-prevention (BISP) for runtime ageing effects of TSVs in 3D ICs	11
FPGA-enhanced system-on-chip for finger vein-based biometric system using novel DL model	10
FPGA routing congestion prediction combining DAGNN and GCN	10
Spherical chaotic trajectory tracking and formation of unmanned aerial vehicles in master–slave configuration with intermediary system	10
Approximate subtractors designed for image processing applications	10
Symmetric synchronization behavior of multistable chaotic systems and circuits in attractive and repulsive couplings	10
A simulation optimization method for Verilog-AMS IBIS model under overclocking	10
A parametric, scalable and efficient architecture for schoolbook polynomial multiplier for lattice-based cryptography	10
LBDR: A load-balanced deadlock-free routing strategy for chiplet systems	10
A self-control leakage-suppression block for low-power high-efficient static logic circuit design in 22 nm CMOS process	10

Fast electromigration stress analysis using Low-Rank Balanced Truncation for general interconnect and power grid structures	10
An improved reconfigurable logic in resistive random access memory	10
Concurrent Steiner Tree Selection for Global routing with EUVL Flare Reduction	10
Integrating error correction and detection techniques in RISC-V processor microarchitecture for enhanced reliability	10
A 0.2-V 1.2 nW 1-KS/s SAR ADC with a novel comparator structure for biomedical applications	10
Hot-spot aware thermoelectric array based cooling for multicore processors	10
Fixed-point implementations for feed-forward artificial neural networks	10
The effect of ECG data variability on side-channel attack success rate in wearable devices	10
Approximate digital-in analog-out multiplier with asymmetric nonvolatility and low energy consumption	9
Multi-source data fusion technique for parametric fault diagnosis in analog circuits	9
Alternative method to reveal encoded images via Gaussian distribution functions	9
An efficient XOR-free implementation of polar encoder for reconfigurable hardware	9
Preferential fault-tolerance multiplier design to mitigate soft errors in FPGAs	9
Incremental/decremental memristor utilizing solely a voltage controlled second-generation current conveyor	9
AI/ML algorithms and applications in VLSI design and technology	9
Design and analysis of faithful parallel mean filter using approximate adders and 4:2 compressors for low-power VLSI architectures	9
Unified chip hardware architecture of KD-tree mean-based trainer and speeding-up classifier with repeat-point searching for various applications	9
Third-order resonance networks and their application to chaos generation	9
Intelligent and kernelized placement: A survey	9
Digital background calibration algorithm for pipelined ADC based on time-delay neural network with genetic algorithm feature selection	9
Robust optimization algorithm of RF MEMS switches considering uncertainties	9
Design and analysis of a frequency division and duty cycle control circuit for on-chip signal synthesis	8
A secure scan architecture using parallel latch-based lock	8
Editorial Board	8
A hybrid entropy source scheme for true random number generator	8
Comments on “New low power and fast SEC-DAEC and SEC-DAEC-TAEC codes for memories in space application”	8
High level synthesis strategies for ultra fast and low latency matrix inversion implementation for massive MIMO processing	8
MVSym: Efficient symbiotic exploitation of HLS-kernel multi-versioning for collaborative CPU-FPGA cloud systems	8
High-performance unified modular multiplication algorithm and hardware architecture over G(2m)	8
An optimised hardware architecture of the angular-domain cyclostationary detector for cognitive radio communications	8
Electronic equivalent of a pump-modulated erbium-doped fiber laser	8
A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow	8
An effective routability-driven packing algorithm for large-scale heterogeneous FPGAs	8
Editorial Board	8
Design-time exploration of voltage switching against power analysis attacks in 14 nm FinFET technology	8
Editorial Board	8
Optimizing code allocation for hybrid on-chip memory in IoT systems	8
Analytic estimation of jitter and eye diagram based on transmission line time domain response considering skin effect and stochastic crosstalk	8
A 2.0–2.9 GHz ring-based injection-locked clock multiplier using a self-alignment frequency-tracking loop for reference spur reduction	8
Energy efficient multiply-accumulate unit using novel recursive multiplication for error-tolerant applications	7
JoBiS: Joint capacitance and inductance bit stuffing CAC for interposer based multi-chip Deep Learning Accelerator	7
Language semantics to support secure computation and communication in embedded systems via hardware monitors	7
An area and power efficient VLSI architecture for epileptic seizure detection using Transpose Form Retimed Delayed LMS filter and spiking neural networks	7
Hardware architecture design for complementary ensemble empirical mode decomposition algorithm	7
Machine learning based fast and accurate High Level Synthesis design space exploration: From graph to synthesis	7
A real-time integrated eye tracker with in-pixel image processing in 0.18-μm CMOS technology	7
ANAS: Software–hardware co-design of approximate neural network accelerators via neural architecture search	7
Hardware efficient design and implementation of multiplierless FIR filters using Sparse PSO on FPGA and ASIC	7
Comparison of integer-order chaotic attractors as randomness source in collision-free robotic exploration methods	7
A low-jitter and low-phase noise switched-loop filter PLL using fast phase-error correction and dual-edge phase comparison technique	7
Glitch-less hardware implementation of block ciphers based on an efficient glitch filter	7
CompreCity: Accelerating the Traveling Salesman Problem on GPU with data compression	7
A 15.13 mW 3.2 GHz 8-bit carry look-ahead adder using single-phase all-N-transistor logic	7
Picowatt 0.3-V MOS-only voltage reference based on a picoamp cascode current generator	7
Lorenz system as a filter	7
VLFF — A very low-power flip-flop with only two clock transistors	7
Innovative nonlinear component generator inspired by squirrel search algorithm	7
The study of TSV-induced and strained silicon-enhanced stress in 3D-ICs	7
Resource-efficient and ultra-high throughput LDPC decoder for CCSDS near-earth standard	7
Automatic correction of RTL designs using a lightweight partial high level synthesis	6
A novel low-resource consumption and high-speed hardware implementation of HOG feature extraction on FPGA for human detection	6
Neural network ℒ1	6
High-resolution calibrated successive-approximation-register analog-to-digital converter	6
A wide-input-range boost converter with three-phase self-start and adaptive zero current detector for photovoltaic energy harvesting	6
A novel class-E class-D doherty power amplifier based on past matching network with linearity region extension and flat output power	6
A fine-grained mixed precision DNN accelerator using a two-stage big–little core RISC-V MCU	6
A frequency boosting technique for cold-start charge pump units	6
Electronically tunable floating DXCCDITA-based universal memelement emulator and its applications	6
Optimal design of mixed dielectric coaxial-annular TSV using GWO algorithm based on artificial neural network	6
Approximate squaring circuits exploiting recursive architectures	6
Ultra-low power linearized FVF based BD double diffusor double differential pair transconductor	6
Content-addressable memory using selective-charging and adaptive-discharging scheme for low-power hardware search engine	6
An ultra-wideband low noise amplifier with cascaded flipped-active inductor for cognitive radio applications	6
Study of the dynamical behavior of an Ikeda-based map with a discrete memristor	6
A hybrid memory polynomial digital predistortion model for RF transmitters	6
An area and power efficient VLSI architecture for ECG feature extraction for wearable IoT healthcare applications	6
An efficient algorithm for disparity map compression based on spatial correlations and its low-cost hardware architecture	6
A systematic review of machine learning-driven design space exploration in high-level synthesis	6
A high-performance convolution block oriented accelerator for MBConv-Based CNNs	6
Design of A prototype 128 × 128 ROIC array for 2.6 μm-wavelength SWIR image sensor applications	6

Design of CMOS fully differential multipath two-stage OTA with boosted slew rate and power efficiency	6
Novel fault tolerance topology using corvus seek algorithm for application specific NoC	5
Design and application of CMOS active inductor in bandpass filter and VCO for reconfigurable RF front-end	5
Integrated DC - DC converter design methodology for design cycle speed up	5
Hardware design for blind source separation using fast time-frequency mask technique	5
An on-chip temperature sensor with 0.5 °C resolution and 0.34% linearity error using 180-nm CMOS process	5
Integration mixer: An efficient mixed neural network for memory dynamic stability analysis in high dimensional variation space	5
A high-efficiency feedforward compensation method for capacitor-less LDO	5
156 dB low-voltage low-power CMOS exponential function generator circuit	5
Compact MAX and MIN Stochastic Computing architectures	5
Efficient and cost-effective maximum power point tracking technique for solar photovoltaic systems with Li-ion battery charging	5
A precision programmable multilevel voltage output and low-temperature-variation CMOS bandgap reference with area-efficient transistor-array layout	5
Novel logic and memory synthesis algorithm for Memristive Hardware Description Language (HDL)	5
Hardware implementation of a robust image cryptosystem using reversible cellular-automata rules and 3-D chaotic systems	5
Nested chopper instrument amplifier with noise modulation for physiological signal sensing	5
A low power offset voltage calibration method for flash ADCs	5
Lorenz system manufacturing with a Butterworth filter	5
A fast and high-performance global router with enhanced congestion control	5
Editorial Board	5
A non-degenerate n-dimensional integer domain chaotic map model with application to PRNG	5
Reliability-aware design of Integrate-and-Fire silicon neurons	5
rel-SLIFMEM: Design and analysis of a reliability-aware neuromorphic system	5
Novel hybrid TFET-FinFET 12T SRAM cells with enhanced write margin and read performance	5
BonnLogic: Delay optimization by And-Or Path restructuring	5
Design of CMOS VCO with XNOR and transmission gate based delay stages	5
High-throughput and area-efficient architectures for image encryption using PRINCE cipher	5
Resource-efficient hardware architecture for low-light image enhancement	5
Chosen ciphertext correlation power analysis on Kyber	5
Design of joint reconfigurable hybrid adder and subtractor using FinFET and GnrFET technologies	5
An energy-efficient image filtering interpolation algorithm using domain-specific dynamic reconfigurable array processor	5
Reference-free power supply monitor with enhanced robustness against process and temperature variations	5
A 158 nw, 2.877 ppm/°C resistorless bandgap reference circuit	5
A fully integrated VLSI architecture using chaotic PWM for RF transmitter design with electromagnetic interference reduction	5
A logic device based on memristor-diode crossbar and CMOS periphery as spike router for hardware neural network	5
Circuit implementation of on-chip trainable spiking neural network using CMOS based memristive STDP synapses and LIF neurons	5
Fractional-Order PI/PD and PID Controllers in Power Electronics: The step-down converter case	4
Dynamics analysis, FPGA implementation, and application in image encryption of a quadruple-wing chaotic system based on hyperbolic sine functions	4
Universal gates as a cornerstone for next-generation configurable ring oscillator PUFs	4
Using ANNs to predict the evolution of spectrum occupancy in cognitive-radio systems	4
Artificial synapse topologies using arbitrary-order memristors	4
Real-time infrared small target detection network and accelerator design	4
Intra-class CutMix data augmentation based deep learning side channel attacks	4
A novel on-chip linear and switching mixed regulation against power analysis attacks	4
CCTA based four different pairs of mutually coupled circuit using single topology	4
Design of synthesizable period-jitter sensor IP with high power reduction and variation resiliency	4
LA-ring based non-linear components: Application to image security	4
CTSNet: Collaborative temporal–spatial net with dual-branch cross-attention for dynamic IR drop prediction	4
A wide-output buck DC-DC power management IC	4
A thermal-aware layer-wise quantization framework for ReRAM-Based DNN CIM systems	4
Resource allocation applied to flexible printed circuit routing based on constrained Delaunay triangulation	4
A 28-GHz wideband power amplifier with dual-pole tuning superposition technique in 55-nm RF CMOS	4
Editorial Board	4
Enhanced FPGA implementation of Echo State Networks for chaotic time series prediction	4
Comparative study of planar stacked integrated transformers for MMICs	4
Batch generating keyed strong S-Boxes with high nonlinearity using 2D hyper chaotic map	4
Design of high performance energy efficient CMOS voltage level shifter for mixed signal circuits applications	4
A programmable delay chain for the source-synchronous interface	4
Rich dynamics and analog implementation of a Hopfield neural network in integer and fractional order domains	4
A Parity-based Multi-bit Fault-Tolerant Instruction Decoder for RISC-V pipelined soft processor	4
Machine learning application for cell delay accuracy improvement at post-placement stage: A case study for combinational cells	3
A novel systolic array processor with dynamic dataflows	3
SIEAA: Significant input extraction-based error optimized approximate adder for error resilient application	3
A robust radiation resistant SRAM cell for space and military applications	3
Design and implementation of filterbank for MPEG-2/4 AAC system	3
Low computational complexity digital predistortion for power amplifiers based on A-CNN-GRU	3
Optimizing value prediction for ILP processors: A design space exploration approach	3
Design of an adaptive winner takes all circuit explaining features of binocular rivalry in visual brain	3
An aging monitoring scheme for SRAM decoders	3
Delay based hardware Trojan detection exploiting spatial correlations to suppress variations	3
Scalable layout decomposition implemented by a distribution evolutionary algorithm	3
A chaotic PRNG tested with the heuristic Differential Evolution	3
A high current efficiency multipath nested feedforward compensation technique for two-stage amplifier	3
SAND-2: An optimized implementation of lightweight block cipher	3
Electronically tunable single FTFNTA-based universal memelement emulator using only grounded passive elements	3
Lorenz’s state equations as RC filters	3
Improved Shimizu-Morioka system and its application in image encryption	3
A Novel four - Wing chaotic system with multiple attractors based on hyperbolic sine: Application to image encryption*	3
Radiation-aware analog circuit design via fully-automated simulation environment	3
WF-SPR: A weighted single fanout approach for signal probability-based reliability estimation	3
The art of temporal decoupling	3
GATOR: A Graph Neural Network based Design Anomaly Predictor	3
Implementation of two new 10-bit 1 GS/s hybrid DACs with a novel gain error calibration technique	3
WITHDRAWN: Design of a novel 1-bit full adder with hybrid logic for full-swing, area-efficiency, and high-speed	3
Grammar-based fuzz testing for microprocessor RTL design	3
Cascode subthreshold PTAT source bandgap voltage reference circuit	3
Litho-NeuralODE 2.0: Improving hotspot detection accuracy with advanced data augmentation, DCT-based features, and neural ordinary differential equations	3
Efficient VLSI architecture of 3D discrete transformation	3
BΔ-NIS: Performance analysis of an efficient data compression technique for on-chip communication network	3
O.O: Optimized one-die placement for face-to-face bonded 3D ICs	3
A new die-level flexible design-for-test architecture for 3D stacked ICs	3
VLSI implementation of low-power and area efficient parallel memory allocation with EC-TCAM	3
A Low cost area-efficient modified Russian peasant multiplier(MRPM) for biomedical applications	3
Design and implementation of deep learning-based object detection and tracking system	3
Efficient FPGA implementation of RNS Montgomery multiplication using balanced RNS bases	3
Design of a low-power, low-PDP dual modulus CML frequency divider for ZigBee application	3