Integration-The VLSI Journal

Article	Citations
Editorial Board	114
A high reliability under-voltage lock out circuit for power driver IC	82
Generating pseudo-random numbers with a Brownian system	77
Chaos based speech encryption using microcontroller	49
Model of a switched-capacitor programmable voltage reference for ultra low-power applications	47
Enhancing logic optimization of Alliance tool based on directed acyclic graphs	44
Dynamics analysis and application of multi-stable Hopfield neural networks under pulsed current stimulation	44
Weak signal detection and circuit implementation based on a novel 3D chaotic synchronization system	43
Low-power hardware architecture of optimized logarithmic square rooter with enhanced error compensation for error-tolerant systems	42
A new three-dimensional conservative system with non - Hamiltonian energy and its synchronization application	38
Deep reinforcement learning assisted reticle floorplanning with rectilinear polygon modules for multiple-project wafer	37
Design-for-reliability and on-the-fly fault tolerance procedure for paper-based digital microfluidic biochips with multiple faults	36
Exploring BTI aging effects on spatial power density and temperature profiles of VLSI chips	36
Lightweight encryption mechanism with discrete-time chaotic maps for Internet of Robotic Things	33
A general and accurate pattern search method for various scenarios	30
Accelerating large-scale multi-scalar multiplication in Zk-SNARK through exploiting its multilevel parallelism	29
Efficient processor verification by tautologies-derived universal properties model checking	29
HDLBC: A lightweight block cipher with high diffusion	28
Design insights for implementing a PRNG with fractional Lorenz system on ESP32 and FPGA	26
A transparent virtual channel power gating method for on-chip network routers	25
Higher-order filters based on the Mittag-Leffler function	25
An LA-group based design of the non-linear component of block cipher	24
Design and implementation of virtual-single-length turbo decoder for multi-user parallel decoding	22
3-D coarse-grained reconfigurable array using multi-pole NEM relays for programmable routing	21
Plug N’ PIM: An integration strategy for Processing-in-Memory accelerators	21

Emerging monolithic 3D integration: Opportunities and challenges from the computer system perspective	20
Inductorless dynamic logic based on 2ϕ-Josephson junctions	20
A 180-nm CMOS fully digital chaotic Lorenz system	20
Design and application of multiscroll chaotic attractors based on memristors	19
Hardware-efficient architecture of spiking neural networks based on sign-magnitude stochastic computing	18
Encoding and decoding devices based on memristor-diode crossbar-array and CMOS logic for spiking neural networks	18
High-robustness CMOS voltage reference for automotive applications with PVT variation tolerance	17
Design of high-efficiency complex multiplier for fault-tolerant computation	17
Design of Flash analog-to-digital converter based on MoS2 FET	17
Complete design approach of a 3rd order continuous-time sigma-delta ADC with FIR feedback and low-noise low-distortion op-amp achieving 101.8 dB SNDR and −110dB THD	17
Design and implementation of congestion aware router for network-on-chip	16
ProHys PUF: A Proteresis - Hysteresis switch based Physical Unclonable Function	16
Error expectation-driven design and energy optimization of approximate multipliers	16
Digital synchronization of the MACM chaotic system by using PIC24-microcontrollers and the SPI-protocol	16
Efficient CNFET-based ternary logic design with emphasis on half-adder and multiplier circuits	16
Hardware-efficient algorithm and architecture design with memory and complexity reduction for semi-global matching	15
A four-dimensional chaotic system with coexisting attractors and its backstepping control and synchronization	15
A 2.69-ppm/°C curvature-compensated BJT-based bandgap voltage reference	15
LQNTL: Low-overhead quadruple-node-upset self-recovery latch based on triple-mode redundancy	15
Low power chaotic oscillator employing CMOS	15
A novel switched-capacitor two-phase single-amplifier 2nd-order Sigma-Delta modulator architecture for area-efficient zoom ADCs	15
Hardware designs for convolutional neural networks: Memoryful, memoryless and cached	14
Real-time neural identification using a recurrent wavelet first-order neural network of a chaotic system implemented in an FPAA	14
A Configurable Delay Transient-Effect Ring Oscillator PUF against modeling attacks	14
Differential receiver with 2 × VDD input signals using 1 × VDD devices	14
Fluid-control codesign for paper-based digital biochips using volumetric memory networks: A predictive modelling approach	14
Approximate Toom–Cook FFT with sparsity aware error tuning in a shared memory architecture	14
Design of novel low cost triple-node-upset self-recoverable hardened latch	14
Matching constraint extraction for analog integrated circuits layout via edge classify	14
Lightweight FPGA acceleration framework for structurally tailored multi-version MobileNetV1	13
A 6.4-Gbps 0.41-pJ/b fully-digital die-to-die interconnect PHY for silicon interposer based 2.5D integration	13
Simple memristive chaotic systems with complex dynamics	13
A novel intrinsic-parameters-correlation enhancement technology applied to accurately extract GaN HEMT small-signal model parameters	13
Nonlinear analysis, circuit implementation, and application in image encryption of a four-dimensional multi-scroll hyper-chaotic system	13
Low-	13
Design of robust analog integrated circuit based on process corner performance variability minimization	13
Clock mesh synthesis through dynamic programming with physical parameters consideration	13
Neurochaos feature transformation for Machine Learning	13
Built-in Self-prevention (BISP) for runtime ageing effects of TSVs in 3D ICs	12
A parametric, scalable and efficient architecture for schoolbook polynomial multiplier for lattice-based cryptography	12
Hot-spot aware thermoelectric array based cooling for multicore processors	12
Fine-grained data integration for high throughput and bandwidth-efficient computation on FPGAs	12
Secure access microcontroller system based on fingerprint template with hyperchaotic encryption	12
CAPUF: Design of a configurable circular arbiter PUF with enhanced security and hardware efficiency	12
The effect of ECG data variability on side-channel attack success rate in wearable devices	12
Genetic algorithm-optimized fuzzy controller for the calibration of pipelined ADCs	12
Area-efficient architectures of Midori lightweight block cipher for resource constrained devices	12
Editorial Board	12
Concurrent Steiner Tree Selection for Global routing with EUVL Flare Reduction	12
Spherical chaotic trajectory tracking and formation of unmanned aerial vehicles in master–slave configuration with intermediary system	12

Efficient hardware mapping of Boolean substitution boxes based on functional decomposition for RFID and ISM band IoT applications	12
FPGA routing congestion prediction combining DAGNN and GCN	11
LBDR: A load-balanced deadlock-free routing strategy for chiplet systems	11
Non-equilibrium oscillator with a diode: Dynamics and application	11
A 0.2-V 1.2 nW 1-KS/s SAR ADC with a novel comparator structure for biomedical applications	11
Alternative method to reveal encoded images via Gaussian distribution functions	11
A self-control leakage-suppression block for low-power high-efficient static logic circuit design in 22 nm CMOS process	11
Design of a dynamic obfuscation-based strong PUF resistant to modeling attacks and mutual authentication protocol	11
A simulation optimization method for Verilog-AMS IBIS model under overclocking	11
Approximate subtractors designed for image processing applications	11
Intelligent and kernelized placement: A survey	11
A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications	11
Power Gated-SRAM and novel header–footer multiplexer based ultra low power Look-Up Table design	11
FPGA-enhanced system-on-chip for finger vein-based biometric system using novel DL model	11
Symmetric synchronization behavior of multistable chaotic systems and circuits in attractive and repulsive couplings	11
Integrating error correction and detection techniques in RISC-V processor microarchitecture for enhanced reliability	11
MORL-IC: Multi-objective reinforcement learning approaches for analog integrated circuit optimization	10
An improved reconfigurable logic in resistive random access memory	10
High speed and high performance approximate multipliers for error resilient applications	10
Fast electromigration stress analysis using Low-Rank Balanced Truncation for general interconnect and power grid structures	10
Double-node-upset-hardened full-subtractor applying MTJ for the high energy physics experiments	10
Unified chip hardware architecture of KD-tree mean-based trainer and speeding-up classifier with repeat-point searching for various applications	10
Third-order resonance networks and their application to chaos generation	10
Preferential fault-tolerance multiplier design to mitigate soft errors in FPGAs	10
An efficient open-source design and implementation framework for non-quantized CNNs on FPGAs	10
Robust optimization algorithm of RF MEMS switches considering uncertainties	10
Approximate digital-in analog-out multiplier with asymmetric nonvolatility and low energy consumption	10
A lossless floating capacitance multiplier based on the single DDCC−	10
Fixed-point implementations for feed-forward artificial neural networks	10
Gated logic controlled 10T-SRAM for low-power bidirectional ring oscillators	9
AI/ML algorithms and applications in VLSI design and technology	9
Editorial Board	9
An efficient XOR-free implementation of polar encoder for reconfigurable hardware	9
Optimizing code allocation for hybrid on-chip memory in IoT systems	9
Analytic estimation of jitter and eye diagram based on transmission line time domain response considering skin effect and stochastic crosstalk	9
Incremental/decremental memristor utilizing solely a voltage controlled second-generation current conveyor	9
Design and analysis of a frequency division and duty cycle control circuit for on-chip signal synthesis	9
MVSym: Efficient symbiotic exploitation of HLS-kernel multi-versioning for collaborative CPU-FPGA cloud systems	9
Picowatt 0.3-V MOS-only voltage reference based on a picoamp cascode current generator	9
Hardware architecture design for complementary ensemble empirical mode decomposition algorithm	9
Editorial Board	9
EOHEAA: Error-Optimized Hardware-Efficient Approximate Adder for energy-aware error-resilient applications	9
An optimised hardware architecture of the angular-domain cyclostationary detector for cognitive radio communications	9
Editorial Board	9
Hardware efficient design and implementation of multiplierless FIR filters using Sparse PSO on FPGA and ASIC	9
Electronic equivalent of a pump-modulated erbium-doped fiber laser	9
Innovative nonlinear component generator inspired by squirrel search algorithm	8
Comments on “New low power and fast SEC-DAEC and SEC-DAEC-TAEC codes for memories in space application”	8
Machine learning based fast and accurate High Level Synthesis design space exploration: From graph to synthesis	8
High-performance unified modular multiplication algorithm and hardware architecture over G(2m)	8
A hybrid entropy source scheme for true random number generator	8
JoBiS: Joint capacitance and inductance bit stuffing CAC for interposer based multi-chip Deep Learning Accelerator	8
An efficient architecture of truncated booth multiplier for AI application	8
A secure scan architecture using parallel latch-based lock	8
CompreCity: Accelerating the Traveling Salesman Problem on GPU with data compression	8
A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow	8
A low-jitter and low-phase noise switched-loop filter PLL using fast phase-error correction and dual-edge phase comparison technique	8
ANAS: Software–hardware co-design of approximate neural network accelerators via neural architecture search	8
Resource-efficient and ultra-high throughput LDPC decoder for CCSDS near-earth standard	8
Design and analysis of faithful parallel mean filter using approximate adders and 4:2 compressors for low-power VLSI architectures	8
Design-time exploration of voltage switching against power analysis attacks in 14 nm FinFET technology	8
An efficient algorithm for disparity map compression based on spatial correlations and its low-cost hardware architecture	7
Review: Application and development of machine learning in semiconductor manufacturing for automated wafer map pattern recognition and classification	7
Comparison of integer-order chaotic attractors as randomness source in collision-free robotic exploration methods	7
A hybrid memory polynomial digital predistortion model for RF transmitters	7
Language semantics to support secure computation and communication in embedded systems via hardware monitors	7
Ultra-low power linearized FVF based BD double diffusor double differential pair transconductor	7
Optimal design of mixed dielectric coaxial-annular TSV using GWO algorithm based on artificial neural network	7
Glitch-less hardware implementation of block ciphers based on an efficient glitch filter	7
A 15.13 mW 3.2 GHz 8-bit carry look-ahead adder using single-phase all-N-transistor logic	7
Digital background calibration algorithm for pipelined ADC based on time-delay neural network with genetic algorithm feature selection	7
A progressive self-training semi-supervised model to enhance discontinuous change detection	7
Lorenz system as a filter	7
Electronically tunable floating DXCCDITA-based universal memelement emulator and its applications	7
An area and power efficient VLSI architecture for epileptic seizure detection using Transpose Form Retimed Delayed LMS filter and spiking neural networks	7
A wide-input-range boost converter with three-phase self-start and adaptive zero current detector for photovoltaic energy harvesting	7
High-resolution calibrated successive-approximation-register analog-to-digital converter	7
A real-time integrated eye tracker with in-pixel image processing in 0.18-μm CMOS technology	7
The study of TSV-induced and strained silicon-enhanced stress in 3D-ICs	7
Energy efficient multiply-accumulate unit using novel recursive multiplication for error-tolerant applications	7

VLFF — A very low-power flip-flop with only two clock transistors	7
Automatic correction of RTL designs using a lightweight partial high level synthesis	7
AI-enabled image processing approach for efficient clustering and identification of hardware Trojans	7
Approximate squaring circuits exploiting recursive architectures	7
A novel low-resource consumption and high-speed hardware implementation of HOG feature extraction on FPGA for human detection	7
Design of a soft error resilient 13T SRAM architecture for radiation-prone environments in FinFET 18 nm technology	7
An effective routability-driven packing algorithm for large-scale heterogeneous FPGAs	7
A fine-grained mixed precision DNN accelerator using a two-stage big–little core RISC-V MCU	6
Low-cost compression architecture based on extended DCT algorithm	6
A novel class-E class-D doherty power amplifier based on past matching network with linearity region extension and flat output power	6
An ultra-wideband low noise amplifier with cascaded flipped-active inductor for cognitive radio applications	6
An energy-efficient image filtering interpolation algorithm using domain-specific dynamic reconfigurable array processor	6
Design of A prototype 128 × 128 ROIC array for 2.6 μm-wavelength SWIR image sensor applications	6
A fast and high-performance global router with enhanced congestion control	6
Adaptive-precision SIMD architecture for high-throughput and resource-efficient DNN acceleration	6
Study of the dynamical behavior of an Ikeda-based map with a discrete memristor	6
A non-degenerate n-dimensional integer domain chaotic map model with application to PRNG	6
Editorial: 5th meeting for the dissemination and research in the study of complex systems and their applications	6
A systematic review of machine learning-driven design space exploration in high-level synthesis	6
True canonical third-order resonance-based oscillators and application to chaos generation	6
A high-performance convolution block oriented accelerator for MBConv-Based CNNs	6
Integrated DC - DC converter design methodology for design cycle speed up	6
Low-temperature-drift voltage reference design using magnetic tunnel junctions	6
A frequency boosting technique for cold-start charge pump units	6
Design of joint reconfigurable hybrid adder and subtractor using FinFET and GnrFET technologies	6
Design of CMOS fully differential multipath two-stage OTA with boosted slew rate and power efficiency	6
Content-addressable memory using selective-charging and adaptive-discharging scheme for low-power hardware search engine	6
A 158 nw, 2.877 ppm/°C resistorless bandgap reference circuit	6
Lorenz system manufacturing with a Butterworth filter	6
Reinforcement learning-driven net order selection for efficient analog IC routing	6
Integration mixer: An efficient mixed neural network for memory dynamic stability analysis in high dimensional variation space	5
An on-chip temperature sensor with 0.5 °C resolution and 0.34% linearity error using 180-nm CMOS process	5
Hardware implementation of a robust image cryptosystem using reversible cellular-automata rules and 3-D chaotic systems	5
BonnLogic: Delay optimization by And-Or Path restructuring	5
Chosen ciphertext correlation power analysis on Kyber	5
Novel hybrid TFET-FinFET 12T SRAM cells with enhanced write margin and read performance	5
Reliability-aware design of Integrate-and-Fire silicon neurons	5
Novel logic and memory synthesis algorithm for Memristive Hardware Description Language (HDL)	5
MICSim: A modular pre-circuit simulator for mixed-signal compute-in-memory accelerators in CNNs and transformers	5
Compact MAX and MIN Stochastic Computing architectures	5
Novel fault tolerance topology using corvus seek algorithm for application specific NoC	5
A Power-efficient Schmitt-trigger integrated Radiation Hardened single-bitline 12T SRAM cell for High Performance applications	5
A low power offset voltage calibration method for flash ADCs	5
A high-efficiency feedforward compensation method for capacitor-less LDO	5
Resource-efficient hardware architecture for low-light image enhancement	5
Nested chopper instrument amplifier with noise modulation for physiological signal sensing	5
Highly robust power efficient Full Adder and Full Subtractor CiM architecture using 10T SRAM cell	5
Circuit implementation of on-chip trainable spiking neural network using CMOS based memristive STDP synapses and LIF neurons	5
Design of CMOS VCO with XNOR and transmission gate based delay stages	5
True random number generator design based on the fractional-order Sprott H chaotic system with statistical validation	5
rel-SLIFMEM: Design and analysis of a reliability-aware neuromorphic system	5
Editorial Board	5
Advanced fault diagnosis in analog and digital VLSI circuits utilizing multi-anchor space-aware temporal convolutional neural network for efficient circuit reliability assessment	5
High-throughput and area-efficient architectures for image encryption using PRINCE cipher	5
RapidPnR: Accelerating the physical design for FPGAs via design-level parallelism	5
Online detection of hardware Trojan enabled packet tampering attack on network-on-chip: A Bayesian approach	5
A precision programmable multilevel voltage output and low-temperature-variation CMOS bandgap reference with area-efficient transistor-array layout	5
Design of high performance energy efficient CMOS voltage level shifter for mixed signal circuits applications	5
156 dB low-voltage low-power CMOS exponential function generator circuit	5
A programmable delay chain for the source-synchronous interface	5
A logic device based on memristor-diode crossbar and CMOS periphery as spike router for hardware neural network	5
An area-efficient 1st order noise shaping SAR using C-2C ladder DAC for biomedical applications	5
A method for mathematically synthesizing double-exponential signal generation on-the-fly on FPGA and its evaluation	4
Intra-class CutMix data augmentation based deep learning side channel attacks	4
Using ANNs to predict the evolution of spectrum occupancy in cognitive-radio systems	4
A 28-GHz wideband power amplifier with dual-pole tuning superposition technique in 55-nm RF CMOS	4
Batch generating keyed strong S-Boxes with high nonlinearity using 2D hyper chaotic map	4
LA-ring based non-linear components: Application to image security	4
WF-SPR: A weighted single fanout approach for signal probability-based reliability estimation	4
Rich dynamics and analog implementation of a Hopfield neural network in integer and fractional order domains	4
A thermal-aware layer-wise quantization framework for ReRAM-Based DNN CIM systems	4
Enhanced functional verification models that ensure the full functionality of an A-PLL device	4
Micro-display backplane power reduction techniques: Column segmentation and row charge sharing	4
Artificial synapse topologies using arbitrary-order memristors	4
Enhanced FPGA implementation of Echo State Networks for chaotic time series prediction	4
X-RAM: a novel and efficient multi-ported memory for AI accelerator	4
A Parity-based Multi-bit Fault-Tolerant Instruction Decoder for RISC-V pipelined soft processor	4
Radiation-aware analog circuit design via fully-automated simulation environment	4
Universal gates as a cornerstone for next-generation configurable ring oscillator PUFs	4
Resource allocation applied to flexible printed circuit routing based on constrained Delaunay triangulation	4
A novel on-chip linear and switching mixed regulation against power analysis attacks	4
CTSNet: Collaborative temporal–spatial net with dual-branch cross-attention for dynamic IR drop prediction	4
A wide-output buck DC-DC power management IC	4
First-order universal filters with two CCII+s and a grounded capacitor: Theory and experimental validation	4
Efficient and cost-effective maximum power point tracking technique for solar photovoltaic systems with Li-ion battery charging	4
Real-time infrared small target detection network and accelerator design	4
A PSRR enhanced capacitorless LDO with gate capacitance cancellation technique	4
VLSI implementation of low-power and area efficient parallel memory allocation with EC-TCAM	4
Comparative study of planar stacked integrated transformers for MMICs	4
Design of an adaptive winner takes all circuit explaining features of binocular rivalry in visual brain	4
Editorial Board	3
A local positive feedback loop-reused technique for enhancing performance of folded cascode amplifier	3
A high current efficiency multipath nested feedforward compensation technique for two-stage amplifier	3
VLSI implementation of adaptable threshold and projection aware OMP with reconfigurable LUT-based MAC unit for ECG signal reconstruction	3
Machine learning application for cell delay accuracy improvement at post-placement stage: A case study for combinational cells	3