Integration-The VLSI Journal

Papers
(The median citation count of Integration-The VLSI Journal is 1. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-04-01 to 2025-04-01.)
ArticleCitations
Optimizing code allocation for hybrid on-chip memory in IoT systems94
Coexistence of infinite attractors in a fractional-order chaotic system with two nonlinear functions and its DSP implementation91
High-performance and low-power decoder circuits for SRAMs using mixed-logic scheme58
Design and implementation of deep learning-based object detection and tracking system46
Energy efficient and high throughput prefix-based pattern matching technique on TCAMs for NIDS44
Design of synthesizable period-jitter sensor IP with high power reduction and variation resiliency44
Improved adaptive sliding mode control for non-ideal single-inductor dual-output boost converter43
High level synthesis strategies for ultra fast and low latency matrix inversion implementation for massive MIMO processing35
Model of a switched-capacitor programmable voltage reference for ultra low-power applications31
Neuro-inspired hardware solutions for high-performance computing: A TiO2-based nano-synaptic device approach with backpropagation31
Multi-harvesting smart solution for self-powered wearable objects: System-level model and transistor-level design27
Test and diagnosis pattern generation for distinguishing stuck-at faults and bridging faults25
Editorial Board25
Edge computing design space exploration for heart rate monitoring23
Editorial Board22
Stumped nature hyperjerk system with fractional order and exponential nonlinearity: Analog simulation, bifurcation analysis and cryptographic applications21
Novel low leakage and energy efficient dual-pullup/dual-pulldown repeater21
Design-time exploration of voltage switching against power analysis attacks in 14 nm FinFET technology21
Editorial Board20
Editorial Board19
Editorial Board19
An optimised hardware architecture of the angular-domain cyclostationary detector for cognitive radio communications19
Design of an adaptive winner takes all circuit explaining features of binocular rivalry in visual brain17
Design of highly reliable radiation hardened 10T SRAM cell for low voltage applications17
VLSI implementation of low-power and area efficient parallel memory allocation with EC-TCAM17
Picowatt 0.3-V MOS-only voltage reference based on a picoamp cascode current generator17
Analytic estimation of jitter and eye diagram based on transmission line time domain response considering skin effect and stochastic crosstalk16
Qualitative data augmentation for performance prediction in VLSI circuits15
A PVT tolerant low power wide tuning range differential voltage controlled oscillator design in 90 nm CMOS technology15
Editorial Board15
Editorial Board15
Radiation-aware analog circuit design via fully-automated simulation environment15
On-chip oscillator based temperature-to-digital converter exploiting channel length modulation coefficient λ15
Comments on “New low power and fast SEC-DAEC and SEC-DAEC-TAEC codes for memories in space application”14
High-performance unified modular multiplication algorithm and hardware architecture over G(2m)14
Design of self-recovering low-cost multiple-node-upset-tolerant latch14
Electronically tunable positive and negative fractional order inductor circuit using single topology14
SEAM: A synergetic energy-efficient approximate multiplier for application demanding substantial computational resources14
A low offset low power CMOS dynamic comparator for analog to digital converters13
Energy efficient multiply-accumulate unit using novel recursive multiplication for error-tolerant applications13
A non-autonomous chaotic system with no equilibrium13
Chaos based speech encryption using microcontroller13
Editorial Board12
Efficient co-planar adder designs in quantum dot cellular automata: Energy and cost optimization with crossover elimination12
Design and analysis of a frequency division and duty cycle control circuit for on-chip signal synthesis11
A 10T SRAM architecture with 40 % enhanced throughput for IMC applications benchmarked with CIFAR-10 dataset11
Multi-cut based architectural obfuscation and handprint biometric signature for securing transient fault detectable IP cores during HLS11
Design-for-reliability and on-the-fly fault tolerance procedure for paper-based digital microfluidic biochips with multiple faults11
Synthesis of representative critical path circuits considering BEOL variations for deep sub-micron circuits11
BDD-based synthesis approach for in-memory logic realization utilizing Memristor Aided loGIC (MAGIC)11
A low voltage input boost converter with novel switch driver enhancement technology for indoor solar energy harvesting11
Breaking LPA-resistant cryptographic circuits with principal component analysis10
MVSym: Efficient symbiotic exploitation of HLS-kernel multi-versioning for collaborative CPU-FPGA cloud systems10
Real-time medical image encryption for H-IoT applications using improved sequences from chaotic maps10
The study of TSV-induced and strained silicon-enhanced stress in 3D-ICs10
A high reliability under-voltage lock out circuit for power driver IC10
Ultra-low-power one-hot transmission-gate multiplexer (OTG-MUX) scalable into large fan-in circuits in 28 nm CMOS10
Design of analog front-end integrated circuit of tactile sensor for human-machine interface10
A secure scan architecture using parallel latch-based lock10
A Machine Learning approach for anomaly detection on the Internet of Things based on Locality-Sensitive Hashing9
Generating pseudo-random numbers with a Brownian system9
Exploring BTI aging effects on spatial power density and temperature profiles of VLSI chips9
A low-jitter and low-phase noise switched-loop filter PLL using fast phase-error correction and dual-edge phase comparison technique9
A rail-to-rail high speed comparator with LVDS output in 0.18-μ9
Deep reinforcement learning assisted reticle floorplanning with rectilinear polygon modules for multiple-project wafer9
A 15.13 mW 3.2 GHz 8-bit carry look-ahead adder using single-phase all-N-transistor logic8
Ensemble learning model for effective thermal simulation of multi-core CPUs8
Proposal and analysis of relative stability in mixed CNT bundle for sub-threshold interconnects8
An effective routability-driven packing algorithm for large-scale heterogeneous FPGAs8
Multi-bit error detection and correction technique using HVDK (Horizontal-Vertical-Diagonal-Knight) parity8
On-board processing for autonomous drone racing: An overview8
Self calibrated cooler-less microbolometer readout architecture8
APoX-M: Accelerate deep point cloud analysis via adaptive graph construction8
ARS-Flow 2.0: An enhanced design space exploration flow for accelerator-rich system based on active learning8
Learning placement order for constructive floorplanning8
Digital background calibration algorithm for pipelined ADC based on time-delay neural network with genetic algorithm feature selection8
Universal gates as a cornerstone for next-generation configurable ring oscillator PUFs7
A 85dB-SNDR 50 kHz bootstrapping-free resistor-less SC Delta-Sigma modulator IP block for PVT-robust low-power ADCs7
CCTA based four different pairs of mutually coupled circuit using single topology7
A new three-dimensional conservative system with non - Hamiltonian energy and its synchronization application7
A novel architecture of high performance fully differential two stage RFC OTA designed using DFVF and hybrid cascode compensation techniques7
Innovative feedback approach for high-performance low-voltage current mirror7
A 2.0–2.9 GHz ring-based injection-locked clock multiplier using a self-alignment frequency-tracking loop for reference spur reduction7
Design and research of grounding current monitoring device for converter transformer core and clamp7
Low power, high speed approximate multiplier for error resilient applications7
A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow7
LA-ring based non-linear components: Application to image security7
A novel filter-bank architecture of 2D-FIR symmetry filters using LUT based multipliers7
A highly-linear, sub-mW LNA at 2.4 GHz in 40 nm CMOS process7
Simulated annealing assisted NSGA-III-based multi-objective analog IC sizing tool7
An efficient XOR-free implementation of polar encoder for reconfigurable hardware7
A three-stage single-miller CMOS OTA with no lower load capacitor limit7
FPGA-based parallel implementation to classify Hyperspectral images by using a Convolutional Neural Network6
Re-configurable parallel Feed-Forward Neural Network implementation using FPGA6
A mathematical programming method for constructing the shortest interconnection VLSI arrays6
Vulnerable objects detection for autonomous driving: A review6
The art of temporal decoupling6
A compact structure for triple-memristor maps with a hyperplane of fixed points6
An 8 bits, RF UHF-Band DAC based on interleaved bandpass delta sigma modulator assisted by background digital calibration6
Hardware architecture design for complementary ensemble empirical mode decomposition algorithm6
Electronic equivalent of a pump-modulated erbium-doped fiber laser6
A broadband MVDR beamforming core for ultrasound imaging6
VLFF — A very low-power flip-flop with only two clock transistors6
Electronically tunable single FTFNTA-based universal memelement emulator using only grounded passive elements6
Editorial Board6
PDQRRFF: Poisson-distributed quantum random reversible flip flop generator for BIST6
Glitch-less hardware implementation of block ciphers based on an efficient glitch filter6
Machine learning based fast and accurate High Level Synthesis design space exploration: From graph to synthesis6
Hw/Sw Co-Design technique for 2D fast fourier transform algorithm on Zynq SoC6
A novel low-resource consumption and high-speed hardware implementation of HOG feature extraction on FPGA for human detection6
An area and power efficient VLSI architecture for ECG feature extraction for wearable IoT healthcare applications6
An optimal channel coding scheme for high-speed data communication5
Design of novel SMS4-BSK encryption transmission system5
Passivity-based non-fragile control of a class of uncertain fractional-order nonlinear systems5
New approach for digital calibration of pipelined analog to digital converters based on secant method5
High-resolution calibrated successive-approximation-register analog-to-digital converter5
Automatic correction of RTL designs using a lightweight partial high level synthesis5
Editorial Board5
Approximate squaring circuits exploiting recursive architectures5
High-performance multiply-accumulate unit by integrating binary carry select adder and counter-based modular wallace tree multiplier for embedding system5
Design and analysis of a flat gain and linear low noise amplifier using modified current reused structure with feedforward structure5
Editorial Board5
Design and implementation of filterbank for MPEG-2/4 AAC system5
BΔ-NIS: Performance analysis of an efficient data compression technique for on-chip communication network5
New partitioned domino circuit for power-efficient wide gates5
Editorial Board5
Accuracy recovery: A decomposition procedure for the synthesis of partially-specified Boolean functions5
Complete design approach of a 3rd order continuous-time sigma-delta ADC with FIR feedback and low-noise low-distortion op-amp achieving 101.8 dB SNDR and −110dB THD5
TeRa: Ternary and Range based packet classification engine5
An energy efficient synthesis flow for application specific SoC design5
Calibration of optimized minimum inductor bandpass filter with controllable bandwidth and stopband rejection5
Optimizing machine learning logic circuits with constant signal propagation5
Design of a 3-bit 2.2 ps step 357.5 ps range 0.247 μm2 0.85 μW 45 nm All-MOS delay element5
An efficient algorithm for disparity map compression based on spatial correlations and its low-cost hardware architecture5
High-speed binary coded decimal digit multipliers with multiple error detection5
Designing efficient FPGA tiles for power-constrained ultra-low-power applications4
Design and application of multiscroll chaotic attractors based on memristors4
Design and implementation of current mode circuit for digital modulation4
A transparent virtual channel power gating method for on-chip network routers4
AiTO: Simultaneous gate sizing and buffer insertion for timing optimization with GNNs and RL4
Design of high-efficiency complex multiplier for fault-tolerant computation4
High quality hypergraph partitioning for logic emulation4
Lorenz system as a filter4
Efficient VLSI architecture of 3D discrete transformation4
High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic4
An LA-group based design of the non-linear component of block cipher4
A robust radiation resistant SRAM cell for space and military applications4
A memristive chaotic system with rich dynamical behavior and circuit implementation4
Accelerating large-scale multi-scalar multiplication in Zk-SNARK through exploiting its multilevel parallelism4
On Minimizing Charge Injection Error Using Multi-Dummy Switches With Enhanced Linearity4
BJT induced dark current in CMOS image sensors4
Design and implementation of virtual-single-length turbo decoder for multi-user parallel decoding4
A C-band low-power sub-1volt current-reused multiphase oscillator4
A robust Euclidean metric based ID extraction method using RO-PUFs in FPGA4
Application driven routing for mesh based Network-on-Chip architectures4
mMIG: Inversion optimization in majority inverter graph with minority operations4
3-D coarse-grained reconfigurable array using multi-pole NEM relays for programmable routing4
Optimal design of mixed dielectric coaxial-annular TSV using GWO algorithm based on artificial neural network4
A novel one-equilibrium memristive chaotic system with multi-parameter amplitude modulation and large-scale offset boosting4
An aging monitoring scheme for SRAM decoders4
A sequential strong PUF architecture based on reconfigurable neural networks (RNNs) against state-of-the-art modeling attacks4
Plug N’ PIM: An integration strategy for Processing-in-Memory accelerators4
High-performance anti-series diode ring amplifier for switched capacitor circuits3
Lorenz’s state equations as RC filters3
FPGA implementation of PUF based key generator for secure communication in IoT3
Very compact 3D-printed folded branch-line hybrid coupler based on loaded helical-microstrip transmission lines3
Standard-compliant parallel SystemC simulation of loosely-timed transaction level models: From baremetal to Linux-based applications support3
Introduction of a new technique for simultaneous reduction of the delay and leakage current in digital circuits3
A PUS based nets weighting mechanism for power, hold, and setup timing optimization3
Experimental study of terrain coverage of an autonomous chaotic mobile robot3
Compact agile Tchebycheff transform variant for temporal compression of neural signals on brain-implantable microsystems3
Synchronous control of memristive hindmarsh-rose neuron models with extreme multistability3
Functional validation of highly synthesizable voltage comparator on FPGA3
Litho-NeuralODE 2.0: Improving hotspot detection accuracy with advanced data augmentation, DCT-based features, and neural ordinary differential equations3
A general and accurate pattern search method for various scenarios3
Multi-frequency weak signal detection based on Liu-like chaotic synchronization system and its hardware circuit implementation3
Lightweight encryption mechanism with discrete-time chaotic maps for Internet of Robotic Things3
Agile-AES: Implementation of configurable AES primitive with agile design approach3
An effective watermarking technique using BTC and SVD for image authentication and quality recovery3
A Novel four - Wing chaotic system with multiple attractors based on hyperbolic sine: Application to image encryption*3
Mathematical analysis and circuit emulator design of the three-valued memristor3
Time redundancy and gate sizing soft error-tolerant based adder design3
The Levene test based-leakage assessment3
Fluid-to-cell assignment and fluid loading on programmable microfluidic devices for bioprotocol execution3
A chaotic PRNG tested with the heuristic Differential Evolution3
Two stage Ordered Escape Routing combined with LP and heuristic algorithm for large scaled PCB3
DULBC: A dynamic ultra-lightweight block cipher with high-throughput3
A hybrid memory polynomial digital predistortion model for RF transmitters3
Delay based hardware Trojan detection exploiting spatial correlations to suppress variations3
HDLBC: A lightweight block cipher with high diffusion3
High-efficiency CMOS charge pump for ultra-low power RF energy harvesting applications3
Efficient FPGA implementation of RNS Montgomery multiplication using balanced RNS bases3
Neural network 13
Efficient design of decimation filter using linear programming and its FPGA implementation3
Heterogenous ensemble learning driven multi-parametric assessment model for hardware Trojan detection3
A digitally controlled adaptive LDO for power management unit in sensor node3
FPGA-based Physical Unclonable Functions: A comprehensive overview of theory and architectures3
Synchronization of mutual coupled fractional order one-sided lipschitz systems3
FPGA-based implementation of classification techniques: A survey3
New low power and fast SEC-DAEC and SEC-DAEC-TAEC codes for memories in space application3
A novel class-E class-D doherty power amplifier based on past matching network with linearity region extension and flat output power3
Emerging monolithic 3D integration: Opportunities and challenges from the computer system perspective3
SIEAA: Significant input extraction-based error optimized approximate adder for error resilient application3
Design and implementation of congestion aware router for network-on-chip2
Design of A prototype 128 × 128 ROIC array for 2.6 μm-wavelength SWIR image sensor applications2
An ultra-wideband low noise amplifier with cascaded flipped-active inductor for cognitive radio applications2
A four-dimensional chaotic system with coexisting attractors and its backstepping control and synchronization2
ProHys PUF: A Proteresis - Hysteresis switch based Physical Unclonable Function2
Design of an ultra-wideband LNA using transformer matching method2
A new hardware Trojan detection technique using deep convolutional neural network2
Dynamic detection of wireless interface faults and fault-tolerant routing algorithm in WiNoC2
An analytical placement algorithm with looking-ahead routing topology optimization2
An accelerated modulus-based matrix splitting iteration method for mixed-size cell circuits legalization2
Hardware-efficient algorithm and architecture design with memory and complexity reduction for semi-global matching2
LQNTL: Low-overhead quadruple-node-upset self-recovery latch based on triple-mode redundancy2
Design of a novel 1-bit full adder with hybrid logic for full-swing, area-efficiency, and high-speed2
HashHeat: A hashing-based spatiotemporal filter for dynamic vision sensor2
Scalable layout decomposition implemented by a distribution evolutionary algorithm2
Content-addressable memory using selective-charging and adaptive-discharging scheme for low-power hardware search engine2
A frequency boosting technique for cold-start charge pump units2
A new die-level flexible design-for-test architecture for 3D stacked ICs2
Linear Clock Tree Topology for Dynamic Source Synchronous and Fully Synchronous 3-D Interfaces2
Experimental analysis of irregularly shaped octagonal on-chip inductors for improving area-efficiency in CMOS RFICs for millimeter wave applications2
Energy-efficient architecture for high-performance FIR adaptive filter using hybridizing CSDTCSE-CRABRA based distributed arithmetic design: Noise removal application in IoT-based WSN2
A new multi-scroll Chua’s circuit with composite hyperbolic tangent-cubic nonlinearity: Complex dynamics, Hardware implementation and Image encryption application2
Improving the thermal reliability of photonic chiplets on multicore processors2
A fast transient response current-feedback low-dropout regulator with dynamic current-enhancement technique2
Convex optimization of random dynamic voltage and frequency scaling against power attacks2
A reference sampling ΔΣ subsa2
Design and optimization of on-chip thick-plated copper-transformers for galvanic isolated DC-DC converter achieving up to 38.9% peak efficiency2
Machine learning application for cell delay accuracy improvement at post-placement stage: A case study for combinational cells2
A novel systolic array processor with dynamic dataflows2
WDP-BNN: Efficient wafer defect pattern classification via binarized neural network2
Lightweight high-throughput true random number generator based on state switchable ring oscillator2
A pseudo resistor with temperature self-adaptive scheme2
A fine-grained mixed precision DNN accelerator using a two-stage big–little core RISC-V MCU2
An energy-efficient image filtering interpolation algorithm using domain-specific dynamic reconfigurable array processor2
Mixed-radix, virtually scaling-free CORDIC algorithm based rotator for DSP applications2
An energy-efficient single-cycle RV32I microprocessor for edge computing applications2
Comparison of two new chaos-based pseudorandom number generators implemented in microcontroller2
Quantization aware approximate multiplier and hardware accelerator for edge computing of deep learning applications2
Analysis of memristive maps with asymmetry2
Grammar-based fuzz testing for microprocessor RTL design2
Editorial Board2
A highly robust RF 65 nm CMOS power amplifier design using Quasi-Newton control algorithm for wireless system2
Low power chaotic oscillator employing CMOS2
Implementation of a fully integrated memristive Chua’s chaotic circuit with a voltage-controlled oscillator2
FPGA realization of an image encryption system using the DCSK-CDMA technique2
A local positive feedback loop-reused technique for enhancing performance of folded cascode amplifier2
A self-training end-to-end mask optimization framework based on semantic segmentation network1
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