Integration-The VLSI Journal

Article	Citations
Exploring BTI aging effects on spatial power density and temperature profiles of VLSI chips	87
Machine learning based fast and accurate High Level Synthesis design space exploration: From graph to synthesis	77
Optimizing code allocation for hybrid on-chip memory in IoT systems	64
Design and implementation of deep learning-based object detection and tracking system	49
Hardware architecture design for complementary ensemble empirical mode decomposition algorithm	42
Design-for-reliability and on-the-fly fault tolerance procedure for paper-based digital microfluidic biochips with multiple faults	39
A rail-to-rail high speed comparator with LVDS output in 0.18-μ	36
Ensemble learning model for effective thermal simulation of multi-core CPUs	35
Design of synthesizable period-jitter sensor IP with high power reduction and variation resiliency	29
Proposal and analysis of relative stability in mixed CNT bundle for sub-threshold interconnects	27
Neuro-inspired hardware solutions for high-performance computing: A TiO2-based nano-synaptic device approach with backpropagation	26
A 15.13 mW 3.2 GHz 8-bit carry look-ahead adder using single-phase all-N-transistor logic	25
Model of a switched-capacitor programmable voltage reference for ultra low-power applications	21
High-performance and low-power decoder circuits for SRAMs using mixed-logic scheme	19
Generating pseudo-random numbers with a Brownian system	19
Robust power grid network design considering EM aging effects for multi-segment wires	18
Multi-harvesting smart solution for self-powered wearable objects: System-level model and transistor-level design	18
A 2.0–2.9 GHz ring-based injection-locked clock multiplier using a self-alignment frequency-tracking loop for reference spur reduction	17
Test and diagnosis pattern generation for distinguishing stuck-at faults and bridging faults	17
Editorial Board	17
Edge computing design space exploration for heart rate monitoring	16
Editorial Board	15
Breaking LPA-resistant cryptographic circuits with principal component analysis	15
Editorial Board	15
Glitch-less hardware implementation of block ciphers based on an efficient glitch filter	15

Stumped nature hyperjerk system with fractional order and exponential nonlinearity: Analog simulation, bifurcation analysis and cryptographic applications	15
Editorial Board	15
Design-time exploration of voltage switching against power analysis attacks in 14 nm FinFET technology	15
Novel low leakage and energy efficient dual-pullup/dual-pulldown repeater	15
Editorial Board	14
Editorial Board	14
An optimised hardware architecture of the angular-domain cyclostationary detector for cognitive radio communications	13
Design of highly reliable radiation hardened 10T SRAM cell for low voltage applications	13
Picowatt 0.3-V MOS-only voltage reference based on a picoamp cascode current generator	13
Self calibrated cooler-less microbolometer readout architecture	13
VLSI implementation of low-power and area efficient parallel memory allocation with EC-TCAM	13
Coexistence of infinite attractors in a fractional-order chaotic system with two nonlinear functions and its DSP implementation	13
Design of an adaptive winner takes all circuit explaining features of binocular rivalry in visual brain	13
On-chip oscillator based temperature-to-digital converter exploiting channel length modulation coefficient λ	12
A low-jitter and low-phase noise switched-loop filter PLL using fast phase-error correction and dual-edge phase comparison technique	12
Editorial Board	12
Analytic estimation of jitter and eye diagram based on transmission line time domain response considering skin effect and stochastic crosstalk	12
Editorial Board	11
MVSym: Efficient symbiotic exploitation of HLS-kernel multi-versioning for collaborative CPU-FPGA cloud systems	11
An effective routability-driven packing algorithm for large-scale heterogeneous FPGAs	11
A PVT tolerant low power wide tuning range differential voltage controlled oscillator design in 90 nm CMOS technology	11
Radiation-aware analog circuit design via fully-automated simulation environment	11
Ultra-low-power one-hot transmission-gate multiplexer (OTG-MUX) scalable into large fan-in circuits in 28 nm CMOS	10
The study of TSV-induced and strained silicon-enhanced stress in 3D-ICs	10
A high reliability under-voltage lock out circuit for power driver IC	10
Comments on “New low power and fast SEC-DAEC and SEC-DAEC-TAEC codes for memories in space application”	10
Qualitative data augmentation for performance prediction in VLSI circuits	10
Electronically tunable positive and negative fractional order inductor circuit using single topology	10
Deep reinforcement learning assisted reticle floorplanning with rectilinear polygon modules for multiple-project wafer	10
A low offset low power CMOS dynamic comparator for analog to digital converters	9
Design of analog front-end integrated circuit of tactile sensor for human-machine interface	9
Design and analysis of a frequency division and duty cycle control circuit for on-chip signal synthesis	8
High-performance unified modular multiplication algorithm and hardware architecture over G(2m)	8
A broadband MVDR beamforming core for ultrasound imaging	8
A Machine Learning approach for anomaly detection on the Internet of Things based on Locality-Sensitive Hashing	8
A secure scan architecture using parallel latch-based lock	8
A highly-linear, sub-mW LNA at 2.4 GHz in 40 nm CMOS process	8
Multi-cut based architectural obfuscation and handprint biometric signature for securing transient fault detectable IP cores during HLS	8
A non-autonomous chaotic system with no equilibrium	7
Chaos based speech encryption using microcontroller	7
Editorial Board	7
Energy efficient multiply-accumulate unit using novel recursive multiplication for error-tolerant applications	7
Design and research of grounding current monitoring device for converter transformer core and clamp	7
Synthesis of representative critical path circuits considering BEOL variations for deep sub-micron circuits	7
BDD-based synthesis approach for in-memory logic realization utilizing Memristor Aided loGIC (MAGIC)	7
High level synthesis strategies for ultra fast and low latency matrix inversion implementation for massive MIMO processing	7
A novel filter-bank architecture of 2D-FIR symmetry filters using LUT based multipliers	7
A low voltage input boost converter with novel switch driver enhancement technology for indoor solar energy harvesting	7
Efficient co-planar adder designs in quantum dot cellular automata: Energy and cost optimization with crossover elimination	7
A 10T SRAM architecture with 40 % enhanced throughput for IMC applications benchmarked with CIFAR-10 dataset	7

CCTA based four different pairs of mutually coupled circuit using single topology	7
A 85dB-SNDR 50 kHz bootstrapping-free resistor-less SC Delta-Sigma modulator IP block for PVT-robust low-power ADCs	7
An efficient XOR-free implementation of polar encoder for reconfigurable hardware	6
LA-ring based non-linear components: Application to image security	6
A three-stage single-miller CMOS OTA with no lower load capacitor limit	6
Universal gates as a cornerstone for next-generation configurable ring oscillator PUFs	6
Simulated annealing assisted NSGA-III-based multi-objective analog IC sizing tool	6
On-board processing for autonomous drone racing: An overview	6
Real-time medical image encryption for H-IoT applications using improved sequences from chaotic maps	6
Learning placement order for constructive floorplanning	6
Digital background calibration algorithm for pipelined ADC based on time-delay neural network with genetic algorithm feature selection	6
A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow	6
Low power, high speed approximate multiplier for error resilient applications	6
Vulnerable objects detection for autonomous driving: A review	6
A new three-dimensional conservative system with non - Hamiltonian energy and its synchronization application	6
A novel architecture of high performance fully differential two stage RFC OTA designed using DFVF and hybrid cascode compensation techniques	6
Multi-bit error detection and correction technique using HVDK (Horizontal-Vertical-Diagonal-Knight) parity	6
Innovative feedback approach for high-performance low-voltage current mirror	6
Electronic equivalent of a pump-modulated erbium-doped fiber laser	6
VLSI mask optimization: From shallow to deep learning	6
A novel tunable gain CMOS buffer amplifier for large resistive loads	6
Neural network ℒ1	5
Time redundancy and gate sizing soft error-tolerant based adder design	5
mMIG: Inversion optimization in majority inverter graph with minority operations	5
An energy efficient synthesis flow for application specific SoC design	5
A C-band low-power sub-1volt current-reused multiphase oscillator	5
Synchronous control of memristive hindmarsh-rose neuron models with extreme multistability	5
Multi-frequency weak signal detection based on Liu-like chaotic synchronization system and its hardware circuit implementation	5
Litho-NeuralODE 2.0: Improving hotspot detection accuracy with advanced data augmentation, DCT-based features, and neural ordinary differential equations	5
1Lossless Grounded Capacitance Multipliers Using Two CFOAs and a Grounded Capacitor	5
Experimental study of terrain coverage of an autonomous chaotic mobile robot	5
Design of novel SMS4-BSK encryption transmission system	5
Editorial Board	5
Calibration of optimized minimum inductor bandpass filter with controllable bandwidth and stopband rejection	5
High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic	5
A hybrid memory polynomial digital predistortion model for RF transmitters	5
Lorenz’s state equations as RC filters	5
Re-configurable parallel Feed-Forward Neural Network implementation using FPGA	5
A general and accurate pattern search method for various scenarios	5
A sequential strong PUF architecture based on reconfigurable neural networks (RNNs) against state-of-the-art modeling attacks	5
A robust Euclidean metric based ID extraction method using RO-PUFs in FPGA	5
Passivity-based non-fragile control of a class of uncertain fractional-order nonlinear systems	5
Design and analysis of a flat gain and linear low noise amplifier using modified current reused structure with feedforward structure	5
Designing efficient FPGA tiles for power-constrained ultra-low-power applications	5
Accelerating large-scale multi-scalar multiplication in Zk-SNARK through exploiting its multilevel parallelism	5
FPGA-based parallel implementation to classify Hyperspectral images by using a Convolutional Neural Network	5
High-performance anti-series diode ring amplifier for switched capacitor circuits	5
Functional validation of highly synthesizable voltage comparator on FPGA	4
An 8 bits, RF UHF-Band DAC based on interleaved bandpass delta sigma modulator assisted by background digital calibration	4
Heterogenous ensemble learning driven multi-parametric assessment model for hardware Trojan detection	4
An optimal channel coding scheme for high-speed data communication	4
High-speed binary coded decimal digit multipliers with multiple error detection	4
Lorenz system as a filter	4
High-performance multiply-accumulate unit by integrating binary carry select adder and counter-based modular wallace tree multiplier for embedding system	4
New approach for digital calibration of pipelined analog to digital converters based on secant method	4
Agile-AES: Implementation of configurable AES primitive with agile design approach	4
Very compact 3D-printed folded branch-line hybrid coupler based on loaded helical-microstrip transmission lines	4
New partitioned domino circuit for power-efficient wide gates	4
A novel one-equilibrium memristive chaotic system with multi-parameter amplitude modulation and large-scale offset boosting	4
Editorial Board	4
Delay based hardware Trojan detection exploiting spatial correlations to suppress variations	4
Editorial Board	4
3-D coarse-grained reconfigurable array using multi-pole NEM relays for programmable routing	4
An aging monitoring scheme for SRAM decoders	4
High-resolution calibrated successive-approximation-register analog-to-digital converter	4
Design and implementation of filterbank for MPEG-2/4 AAC system	4
Efficient VLSI architecture of 3D discrete transformation	4
Orthogonal obfuscation based key management for multiple IP protection	4
Complete design approach of a 3rd order continuous-time sigma-delta ADC with FIR feedback and low-noise low-distortion op-amp achieving 101.8 dB SNDR and −110dB THD	4
Accuracy recovery: A decomposition procedure for the synthesis of partially-specified Boolean functions	4
Approximate squaring circuits exploiting recursive architectures	4
New low power and fast SEC-DAEC and SEC-DAEC-TAEC codes for memories in space application	4
Plug N’ PIM: An integration strategy for Processing-in-Memory accelerators	4
BJT induced dark current in CMOS image sensors	4
Optimizing machine learning logic circuits with constant signal propagation	4
A mathematical programming method for constructing the shortest interconnection VLSI arrays	3
Design and implementation of virtual-single-length turbo decoder for multi-user parallel decoding	3
HashHeat: A hashing-based spatiotemporal filter for dynamic vision sensor	3
A chaotic PRNG tested with the heuristic Differential Evolution	3
AiTO: Simultaneous gate sizing and buffer insertion for timing optimization with GNNs and RL	3

DULBC: A dynamic ultra-lightweight block cipher with high-throughput	3
Compact agile Tchebycheff transform variant for temporal compression of neural signals on brain-implantable microsystems	3
A novel low-resource consumption and high-speed hardware implementation of HOG feature extraction on FPGA for human detection	3
Fluid-to-cell assignment and fluid loading on programmable microfluidic devices for bioprotocol execution	3
Hw/Sw Co-Design technique for 2D fast fourier transform algorithm on Zynq SoC	3
VLFF — A very low-power flip-flop with only two clock transistors	3
Design and application of multiscroll chaotic attractors based on memristors	3
Design of a 3-bit 2.2 ps step 357.5 ps range 0.247 μm2 0.85 μW 45 nm All-MOS delay element	3
FPGA-based implementation of classification techniques: A survey	3
Design of high-efficiency complex multiplier for fault-tolerant computation	3
Application driven routing for mesh based Network-on-Chip architectures	3
Approximate multipliers based on a novel unbiased approximate 4-2 compressor	3
O.O: Optimized one-die placement for face-to-face bonded 3D ICs	3
Optimal design of mixed dielectric coaxial-annular TSV using GWO algorithm based on artificial neural network	3
Design and implementation of current mode circuit for digital modulation	3
High quality hypergraph partitioning for logic emulation	3
An LA-group based design of the non-linear component of block cipher	3
Partial evaluation based triple modular redundancy for single event upset mitigation	3
PDQRRFF: Poisson-distributed quantum random reversible flip flop generator for BIST	3
A robust radiation resistant SRAM cell for space and military applications	3
HDLBC: A lightweight block cipher with high diffusion	3
Lightweight encryption mechanism with discrete-time chaotic maps for Internet of Robotic Things	3
Automatic correction of RTL designs using a lightweight partial high level synthesis	3
An efficient algorithm for disparity map compression based on spatial correlations and its low-cost hardware architecture	3
On Minimizing Charge Injection Error Using Multi-Dummy Switches With Enhanced Linearity	3
Electronically tunable single FTFNTA-based universal memelement emulator using only grounded passive elements	3
An area and power efficient VLSI architecture for ECG feature extraction for wearable IoT healthcare applications	3
Comparison of integer-order chaotic attractors as randomness source in collision-free robotic exploration methods	3
A transparent virtual channel power gating method for on-chip network routers	3
Emerging monolithic 3D integration: Opportunities and challenges from the computer system perspective	3
A Novel four - Wing chaotic system with multiple attractors based on hyperbolic sine: Application to image encryption*	3
A memristive chaotic system with rich dynamical behavior and circuit implementation	3
Introduction of a new technique for simultaneous reduction of the delay and leakage current in digital circuits	3
Two stage Ordered Escape Routing combined with LP and heuristic algorithm for large scaled PCB	3
TeRa: Ternary and Range based packet classification engine	3
BΔ-NIS: Performance analysis of an efficient data compression technique for on-chip communication network	3
FPGA-based Physical Unclonable Functions: A comprehensive overview of theory and architectures	3
Editorial Board	3
On malicious implants in PCBs throughout the supply chain	2
Efficient FPGA implementation of RNS Montgomery multiplication using balanced RNS bases	2
A fine-grained mixed precision DNN accelerator using a two-stage big–little core RISC-V MCU	2
Low power chaotic oscillator employing CMOS	2
Improving the thermal reliability of photonic chiplets on multicore processors	2
A high current efficiency multipath nested feedforward compensation technique for two-stage amplifier	2
A non-degenerate n-dimensional integer domain chaotic map model with application to PRNG	2
Hardware design for blind source separation using fast time-frequency mask technique	2
Experimental analysis of irregularly shaped octagonal on-chip inductors for improving area-efficiency in CMOS RFICs for millimeter wave applications	2
A local positive feedback loop-reused technique for enhancing performance of folded cascode amplifier	2
A new die-level flexible design-for-test architecture for 3D stacked ICs	2
Design of CMOS fully differential multipath two-stage OTA with boosted slew rate and power efficiency	2
Efficient design of decimation filter using linear programming and its FPGA implementation	2
Grammar-based fuzz testing for microprocessor RTL design	2
Content-addressable memory using selective-charging and adaptive-discharging scheme for low-power hardware search engine	2
A novel class-E class-D doherty power amplifier based on past matching network with linearity region extension and flat output power	2
An ultra-wideband low noise amplifier with cascaded flipped-active inductor for cognitive radio applications	2
Power density aware application mapping in mesh-based network-on-chip architecture: An evolutionary multi-objective approach	2
An energy-efficient single-cycle RV32I microprocessor for edge computing applications	2
Low power time-domain rail-to-rail comparator with a new delay element for ADC applications	2
Quantization aware approximate multiplier and hardware accelerator for edge computing of deep learning applications	2
Synchronization of mutual coupled fractional order one-sided lipschitz systems	2
Design of a novel 1-bit full adder with hybrid logic for full-swing, area-efficiency, and high-speed	2
An analytical placement algorithm with looking-ahead routing topology optimization	2
Design of A prototype 128 × 128 ROIC array for 2.6 μm-wavelength SWIR image sensor applications	2
A four-dimensional chaotic system with coexisting attractors and its backstepping control and synchronization	2
An effective watermarking technique using BTC and SVD for image authentication and quality recovery	2
Standard-compliant parallel SystemC simulation of loosely-timed transaction level models: From baremetal to Linux-based applications support	2
A digitally controlled adaptive LDO for power management unit in sensor node	2
Study of the dynamical behavior of an Ikeda-based map with a discrete memristor	2
Design of an ultra-wideband LNA using transformer matching method	2
An Enhanced Memetic Algorithm using SKB tree representation for fixed-outline and temperature driven non-slicing floorplanning	2
The Levene test based-leakage assessment	2
A frequency boosting technique for cold-start charge pump units	2
A novel systolic array processor with dynamic dataflows	2
An energy-efficient image filtering interpolation algorithm using domain-specific dynamic reconfigurable array processor	2
Research progress of time-interleaved analog-to-digital converters	2
A pseudo resistor with temperature self-adaptive scheme	2
Lightweight high-throughput true random number generator based on state switchable ring oscillator	2
An accelerated modulus-based matrix splitting iteration method for mixed-size cell circuits legalization	2
Linear Clock Tree Topology for Dynamic Source Synchronous and Fully Synchronous 3-D Interfaces	2
A very low output resistance and wide-swing class-AB level-shifted folded flipped voltage follower cell	2
Mathematical analysis and circuit emulator design of the three-valued memristor	2
30 GHz SiGe active inductor with voltage controlled Q	2
Convex optimization of random dynamic voltage and frequency scaling against power attacks	2
B2N	1
A 10-Gb/s low-power inverter-based optical receiver front-end in 0.13-	1
A self-training end-to-end mask optimization framework based on semantic segmentation network	1
Integrated electrical silicon interconnects for short-range high-speed millimeter-wave and terahertz communications	1
Editorial Board	1
A 8.83 ppm/°C temperature coefficient, 75 dB PSRR subthreshold CMOS voltage reference with piecewise curvature compensation	1
Reduction of variation and leakage in wide fan-in OR Logic domino gate	1
Design of novel low cost triple-node-upset self-recoverable hardened latch	1
A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process	1
Extrinsic calibration of complex machine vision system for mobile robot	1
Nonlinear analysis, circuit implementation, and application in image encryption of a four-dimensional multi-scroll hyper-chaotic system	1
A CAFVF-based output-capacitor-less LDO with PSRR improvement by feed forward and negative capacitance	1