Integration-The VLSI Journal

Article	Citations
A new multi-scroll Chua’s circuit with composite hyperbolic tangent-cubic nonlinearity: Complex dynamics, Hardware implementation and Image encryption application	87
A new adaptive selection strategy for reducing latency in networks on chip	66
Review: Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test	64
Dynamics analysis, FPGA realization and image encryption application of a 5D memristive exponential hyperchaotic system	49
A novel dual mode configurable and tunable high-gain, high-efficient CMOS power amplifier for 5G applications	42
Vulnerable objects detection for autonomous driving: A review	39
FPGA-based Physical Unclonable Functions: A comprehensive overview of theory and architectures	36
Secure image encryption scheme using 4D-Hyperchaotic systems based reconfigurable pseudo-random number generator and S-Box	35
MOS based pseudo-resistors exhibiting Tera Ohms of Incremental Resistance for biomedical applications: Analysis and proof of concept	30
Design of hyperchaotic system based on multi-scroll and its encryption algorithm in color image	29
Constructing keyed strong S-Box with higher nonlinearity based on 2D hyper chaotic map and algebraic operation	26
A new 4D Memristor chaotic system: Analysis and implementation	25
A two-directional grid multiscroll hidden attractor based on piecewise linear system and its application in pseudo-random bit generator	23
Experimental verification of the multi-scroll chaotic attractors synchronization in PWL arbitrary-order systems using direct coupling and passivity-based control	19
Cryptanalysis of nonlinear confusion component based encryption algorithm	19
FPGA-based implementation of classification techniques: A survey	18
Design automation for continuous-flow microfluidic biochips: A comprehensive review	18
On malicious implants in PCBs throughout the supply chain	18
On-board processing for autonomous drone racing: An overview	17
An efficient image encryption scheme based on double affine substitution box and chaotic system	17
Compact and efficient structure of 8-bit S-box for lightweight cryptography	16
Real-time medical image encryption for H-IoT applications using improved sequences from chaotic maps	16
Batch generating keyed strong S-Boxes with high nonlinearity using 2D hyper chaotic map	15
RESET: A real-time scheduler for energy and temperature aware heterogeneous multi-core systems	15
Hyperchaotic fractional Grassi–Miller map and its hardware implementation	15

A Survey of FIR Filter Design Techniques: Low-complexity, Narrow Transition-band and Variable Bandwidth	15
An efficient construction of S-box based on the fractional-order Rabinovich–Fabrikant chaotic system	15
Approximate multipliers based on a novel unbiased approximate 4-2 compressor	15
Electronically tunable third-order dual-mode quadrature sinusoidal oscillators employing VDCCs and all grounded components	15
Realizations of fractional-order PID loop-shaping controller for mechatronic applications	15
A memristive chaotic system with rich dynamical behavior and circuit implementation	15
A novel current-controlled memristor-based chaotic circuit	14
A Novel four - Wing chaotic system with multiple attractors based on hyperbolic sine: Application to image encryption*	14
Accelerating Deep Convolutional Neural Network base on stochastic computing	14
Multi-source data fusion technique for parametric fault diagnosis in analog circuits	13
Design space exploration of low-power flip-flops in FinFET technology	13
AI/ML algorithms and applications in VLSI design and technology	13
New memristor-less, resistor-less, two-OTA based grounded and floating meminductor emulators and their applications in chaotic oscillators	13
A four-dimensional chaotic system with coexisting attractors and its backstepping control and synchronization	13
High-performance area-efficient polynomial ring processor for CRYSTALS-Kyber on FPGAs	13
High-throughput and area-efficient architectures for image encryption using PRINCE cipher	13
VLSI mask optimization: From shallow to deep learning	13
Coexistence of infinite attractors in a fractional-order chaotic system with two nonlinear functions and its DSP implementation	12
A novel memristive chaotic system without any equilibrium point	12
Chaotic encryption of real-time ECG signal in embedded system for secure telemedicine	12
A new hardware Trojan detection technique using deep convolutional neural network	12
High-performance hardware architecture of a robust block-cipher algorithm based on different chaotic maps and DNA sequence encoding	12
A chaotic PRNG tested with the heuristic Differential Evolution	11
A non-autonomous chaotic system with no equilibrium	11
WDP-BNN: Efficient wafer defect pattern classification via binarized neural network	11
A new low-power Dynamic-GDI full adder in CNFET technology	11
Emerging monolithic 3D integration: Opportunities and challenges from the computer system perspective	11
Reliable and low power Negative Capacitance Junctionless FinFET based 6T SRAM cell	10
Low power chaotic oscillator employing CMOS	10
A low latency modular-level deeply integrated MFCC feature extraction architecture for speech recognition	10
An effective watermarking technique using BTC and SVD for image authentication and quality recovery	10
2.3–21 GHz broadband and high linearity distributed low noise amplifier	10
Design of novel SMS4-BSK encryption transmission system	10
Reveal the correlation between randomness and Lyapunov exponent of n-dimensional non-degenerate hyper chaotic map	10
Power density aware application mapping in mesh-based network-on-chip architecture: An evolutionary multi-objective approach	10
Mixed-radix, virtually scaling-free CORDIC algorithm based rotator for DSP applications	10
Sizing of multi-stage Op Amps by combining design equations with the gm/ID method	9
Color image encryption based on discrete memristor logistic map and DNA encoding	8
Study of the dynamical behavior of an Ikeda-based map with a discrete memristor	8
Simulated annealing assisted NSGA-III-based multi-objective analog IC sizing tool	8
New lightweight Anti-SAT block design and obfuscation technique to thwart removal attack	8
Quantization aware approximate multiplier and hardware accelerator for edge computing of deep learning applications	8
Hardware implementation of a robust image cryptosystem using reversible cellular-automata rules and 3-D chaotic systems	8
The Involution Tool for Accurate Digital Timing and Power Analysis	8
Design and implementation of current mode circuit for digital modulation	7
HDLBC: A lightweight block cipher with high diffusion	7
A transformer with high coupling coefficient and small area based on TSV	7
Novel tunable current feedback instrumentation amplifier based on BBFC OP-AMP for biomedical applications with low power and high CMRR	7
A transparent virtual channel power gating method for on-chip network routers	7
Experimental study of terrain coverage of an autonomous chaotic mobile robot	7

A broadband MVDR beamforming core for ultrasound imaging	7
Machine learning classification algorithm for VLSI test cost reduction	7
A survey on machine learning-based routing for VLSI physical design	7
FPGA-based parallel implementation to classify Hyperspectral images by using a Convolutional Neural Network	7
An area and power efficient VLSI architecture for ECG feature extraction for wearable IoT healthcare applications	7
Proposal and analysis of relative stability in mixed CNT bundle for sub-threshold interconnects	7
Transmission synchronization of multiple memristor chaotic circuits via single input controller and its application in secure communication	7
A fast piecewise image encryption scheme combining NC1DNSM and P-Box	7
High speed VLSI architecture for improved region based active contour segmentation technique	7
Design and application of CMOS active inductor in bandpass filter and VCO for reconfigurable RF front-end	6
Convex optimization of random dynamic voltage and frequency scaling against power attacks	6
An Enhanced Memetic Algorithm using SKB tree representation for fixed-outline and temperature driven non-slicing floorplanning	6
Agile-AES: Implementation of configurable AES primitive with agile design approach	6
Breaking LPA-resistant cryptographic circuits with principal component analysis	6
Valid test pattern identification for VLSI adaptive test	6
Neurochaos feature transformation for Machine Learning	6
Building discrete maps with memristor and multiple nonlinear terms	6
Dynamic analysis and FPGA implementation of a 5D multi-wing fractional-order memristive chaotic system with hidden attractors	6
Construction of algebraic complex 9-bit lookup tables using non-chain-ring and its applications in data security	6
Avoidance vs. repair: New approaches to increasing electromigration robustness in VLSI routing	6
Hw/Sw Co-Design technique for 2D fast fourier transform algorithm on Zynq SoC	6
An efficient multiple shortest augmenting paths algorithm for constructing high performance VLSI subarray	6
Multicast-enabled network-on-chip routers leveraging partitioned allocation and switching	6
An improved algorithm for accelerating reconfiguration of VLSI array	6
An accelerated modulus-based matrix splitting iteration method for mixed-size cell circuits legalization	6
VDTA and DO-CCII based incremental/decremental floating memductance/meminductance simulator: A novel realization	6
Application driven routing for mesh based Network-on-Chip architectures	6
A novel tunable gain CMOS buffer amplifier for large resistive loads	6
Construction and implementation of discrete memristive hyperchaotic map with hidden attractors and self-excited attractors	6
Hot-spot aware thermoelectric array based cooling for multicore processors	6
Design of FIR filter ISOTA with the aid of genetic algorithm	5
READ: A fixed restoring array based accuracy-configurable approximate divider for energy efficiency	5
A new post-processing approach for improvement of nonlinearity property in substitution boxes	5
A PVT aware differential delay circuit and its performance variation due to power supply noise	5
Design and implementation of congestion aware router for network-on-chip	5
An energy-efficient single-cycle RV32I microprocessor for edge computing applications	5
DULBC: A dynamic ultra-lightweight block cipher with high-throughput	5
Low-power content addressable memory design using two-layer P-N match-line control and sensing	5
Invasive weed optimization based scheduling for digital microfluidic biochip operations	5
Four-input-C-element-based multiple-node-upset-self-recoverable latch designs	5
Statistical traffic pattern for mixed torus topology and pathfinder based traffic and thermal aware routing protocol on NoC	5
A 0.2-V 1.2 nW 1-KS/s SAR ADC with a novel comparator structure for biomedical applications	5
Integrated DC - DC converter design methodology for design cycle speed up	5
A very low output resistance and wide-swing class-AB level-shifted folded flipped voltage follower cell	5
A novel systolic array processor with dynamic dataflows	5
Design of joint reconfigurable hybrid adder and subtractor using FinFET and GnrFET technologies	5
Passivity-based non-fragile control of a class of uncertain fractional-order nonlinear systems	5
A novel filter-bank architecture of 2D-FIR symmetry filters using LUT based multipliers	5
Machine learning based fast and accurate High Level Synthesis design space exploration: From graph to synthesis	5
OTA-C signal delay compensation circuit for transimpedance-mode audio signal processing systems	5
A 1Gpixel 10FPS CMOS image sensor using pixel array high-speed readout technology	5
A DRV-based bit selection method for SRAM PUF key generation and its impact on ECCs	5
Secure access microcontroller system based on fingerprint template with hyperchaotic encryption	5
Nonlinear analysis, circuit implementation, and application in image encryption of a four-dimensional multi-scroll hyper-chaotic system	5
Efficient design of decimation filter using linear programming and its FPGA implementation	5
Low power time-domain rail-to-rail comparator with a new delay element for ADC applications	5
An improved heuristic technique for nearest neighbor realization of quantum circuits in 2D architecture	5
Design and analysis of a flat gain and linear low noise amplifier using modified current reused structure with feedforward structure	5
Design of highly reliable radiation hardened 10T SRAM cell for low voltage applications	5
Real-time infrared small target detection network and accelerator design	5
Custom NoC topology generation using Discrete Antlion Trapping Mechanism	4
A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications	4
Quantitative comparison and performance evaluation of deep learning-based object detection models on edge computing devices	4
Development of micro computer based mobile random number generator with an encryption application	4
HashHeat: A hashing-based spatiotemporal filter for dynamic vision sensor	4
The Levene test based-leakage assessment	4
Litho-NeuralODE 2.0: Improving hotspot detection accuracy with advanced data augmentation, DCT-based features, and neural ordinary differential equations	4
High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic	4
BDD-based synthesis approach for in-memory logic realization utilizing Memristor Aided loGIC (MAGIC)	4
Enhanced FPGA implementation of Echo State Networks for chaotic time series prediction	4
Graph-based STA for asynchronous controllers	4
A novel approach to fractional-N PLLs generating ultra-fast low-noise chirps for FMCW radar	4
Design of approximate Booth multipliers based on error compensation	4
A self-control leakage-suppression block for low-power high-efficient static logic circuit design in 22 nm CMOS process	4
Low-power and high-speed SRAM cells for double-node-upset recovery	4
Efficient and low-cost approximate multipliers for image processing applications	4
A high-performance convolution block oriented accelerator for MBConv-Based CNNs	4
Research progress of time-interleaved analog-to-digital converters	4
High quality hypergraph partitioning for logic emulation	4
Lightweight encryption mechanism with discrete-time chaotic maps for Internet of Robotic Things	4

Radiation-aware analog circuit design via fully-automated simulation environment	4
Highly stable soft-error immune SRAM with multi-node upset recovery for aerospace applications	4
Monolithic 3D stacked multiply-accumulate units	4
A CMOS rectified linear unit operating in weak inversion for memristive neuromorphic circuits	4
Investigating the influence of adiabatic load on the 4-phase adiabatic system design	4
Chosen ciphertext correlation power analysis on Kyber	4
B2N	4
Mathematical analysis and circuit emulator design of the three-valued memristor	4
A fast transient response current-feedback low-dropout regulator with dynamic current-enhancement technique	4
Fluid-to-cell assignment and fluid loading on programmable microfluidic devices for bioprotocol execution	4
Heterogenous ensemble learning driven multi-parametric assessment model for hardware Trojan detection	4
An enhanced logistic chaotic map based tweakable speech encryption algorithm	4
Picowatt 0.3-V MOS-only voltage reference based on a picoamp cascode current generator	4
A hybrid method for signal probability and reliability estimation with combinational circuits	4
Low voltage fully differential OTA using DTMOS based self cascode transistor with slew-rate enhancement and its filter application	3
CAPUF: Design of a configurable circular arbiter PUF with enhanced security and hardware efficiency	3
Novel fault tolerance topology using corvus seek algorithm for application specific NoC	3
A functional block decomposition method for automatic op-amp design	3
A passive and low-complexity Compressed Sensing architecture based on a charge-redistribution SAR ADC	3
High-throughput architecture for post-quantum DME cryptosystem	3
Comparison of two new chaos-based pseudorandom number generators implemented in microcontroller	3
Chaos based speech encryption using microcontroller	3
Introduction of a new technique for simultaneous reduction of the delay and leakage current in digital circuits	3
Memristor-cascaded hopfield neural network with attractor scroll growth and STM32 hardware experiment	3
Design-for-reliability and on-the-fly fault tolerance procedure for paper-based digital microfluidic biochips with multiple faults	3
An energy efficient synthesis flow for application specific SoC design	3
FRDS: An efficient unique on-Chip interconnection network architecture	3
New low power and fast SEC-DAEC and SEC-DAEC-TAEC codes for memories in space application	3
Improved thermal network modeling of die stacking DRAM and optimization	3
A new three-dimensional conservative system with non - Hamiltonian energy and its synchronization application	3
On circuit developments to enable large scale circuit design while computing with noise	3
VLSI architecture design and implementation of 5/3 and 9/7 lifting Discrete Wavelet Transform	3
Comparative evaluation of background-rejection techniques for SPAD-based LiDAR systems	3
Area and power efficient hard multiple generator for radix-8 modulo 2  − 1 multiplier	3
Efficient FPGA implementation of RNS Montgomery multiplication using balanced RNS bases	3
Analysis of memristive maps with asymmetry	3
High level synthesis strategies for ultra fast and low latency matrix inversion implementation for massive MIMO processing	3
An ultra-wideband low noise amplifier with cascaded flipped-active inductor for cognitive radio applications	3
Approximate digital-in analog-out multiplier with asymmetric nonvolatility and low energy consumption	3
A low offset low power CMOS dynamic comparator for analog to digital converters	3
Designing efficient FPGA tiles for power-constrained ultra-low-power applications	3
Efficient hardware implementations of lightweight Simeck Cipher for resource-constrained applications	3
Hardware architecture design for complementary ensemble empirical mode decomposition algorithm	3
On the quadrature accuracy of in-phase coupled quadrature LC oscillator	3
Design and implementation of low power Advanced Encryption Standard cryptocore utilizing dynamic pipelined asynchronous model	3
Neural network ℒ1	3
Resource allocation applied to flexible printed circuit routing based on constrained Delaunay triangulation	3
DCNN search and accelerator co-design: Improve the adaptability between NAS frameworks and embedded platforms	3
Second-order cascode-based filters	3
An efficient NBTI-aware wake-up strategy: Concept, design, and manipulation	3
A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process	3
Grammar-based fuzz testing for microprocessor RTL design	3
SAND-2: An optimized implementation of lightweight block cipher	3
Synthesis of representative critical path circuits considering BEOL variations for deep sub-micron circuits	3
A robust radiation resistant SRAM cell for space and military applications	3
Exploring the dynamics of a multistable general model of discrete memristor-based map featuring an exponentially varying memristance	3
Electronically tunable positive and negative fractional order inductor circuit using single topology	3
A robust Euclidean metric based ID extraction method using RO-PUFs in FPGA	3
Low delay non-binary error correction codes based on Orthogonal Latin Squares	3
Delay based hardware Trojan detection exploiting spatial correlations to suppress variations	3
Deep learning aided efficient yield analysis for multi-objective analog integrated circuit synthesis	3
Electronic equivalent of a pump-modulated erbium-doped fiber laser	3
30 GHz SiGe active inductor with voltage controlled Q	2
Design of an ultra-wideband LNA using transformer matching method	2
ProHys PUF: A Proteresis - Hysteresis switch based Physical Unclonable Function	2
An ultra-wideband 6–14 GHz frequency modulated continuous wave primary radar with 3 cm range resolution	2
A sequential strong PUF architecture based on reconfigurable neural networks (RNNs) against state-of-the-art modeling attacks	2
Low power, high speed approximate multiplier for error resilient applications	2
Stumped nature hyperjerk system with fractional order and exponential nonlinearity: Analog simulation, bifurcation analysis and cryptographic applications	2
RECO-ASCON: Reconfigurable ASCON hash functions for IoT applications	2
Generating pseudo-random numbers with a Brownian system	2
COPRICSI: COnstraint-PRogrammed Initial Circuit SIzing	2
A 20-Gb/s wideband AGC amplifier with 26-dB dynamic range in 0.18-μm SiGe BiCMOS	2
DAFA: Dynamic approximate full adders for high area and energy efficiency	2
Power-aware hold optimization for ASIC physical synthesis	2
Improving the thermal reliability of photonic chiplets on multicore processors	2
Time-domain writing architecture for multilevel RRAM cells resilient to temperature and process variations	2
Partial evaluation based triple modular redundancy for single event upset mitigation	2
High-performance multiply-accumulate unit by integrating binary carry select adder and counter-based modular wallace tree multiplier for embedding system	2
A 85dB-SNDR 50 kHz bootstrapping-free resistor-less SC Delta-Sigma modulator IP block for PVT-robust low-power ADCs	2
Edge computing design space exploration for heart rate monitoring	2
Synchronization of fractional-order chaotic networks in Presnov form via homogeneous controllers	2
An ant colony based mapping of quantum circuits to nearest neighbor architectures	2
Analysis of a new three-dimensional jerk chaotic system with transient chaos and its adaptive backstepping synchronous control	2
A fine-grained mixed precision DNN accelerator using a two-stage big–little core RISC-V MCU	2
A novel class-E class-D doherty power amplifier based on past matching network with linearity region extension and flat output power	2
Compact agile Tchebycheff transform variant for temporal compression of neural signals on brain-implantable microsystems	2
An LA-group based design of the non-linear component of block cipher	2
Efficient VLSI architecture of 3D discrete transformation	2
A mathematical programming method for constructing the shortest interconnection VLSI arrays	2
The study of TSV-induced and strained silicon-enhanced stress in 3D-ICs	2
Robust power grid network design considering EM aging effects for multi-segment wires	2
Inexact radix-4 Booth multipliers based on new partial product generation scheme for image multiplication	2
A high-efficiency feedforward compensation method for capacitor-less LDO	2
On reverse converters for arbitrary multi-moduli RNS	2