Integration-The VLSI Journal

Article	Citations
Machine learning based fast and accurate High Level Synthesis design space exploration: From graph to synthesis	94
Optimizing code allocation for hybrid on-chip memory in IoT systems	77
Design and implementation of deep learning-based object detection and tracking system	76
Hardware architecture design for complementary ensemble empirical mode decomposition algorithm	49
High level synthesis strategies for ultra fast and low latency matrix inversion implementation for massive MIMO processing	42
Design of synthesizable period-jitter sensor IP with high power reduction and variation resiliency	39
Neuro-inspired hardware solutions for high-performance computing: A TiO2-based nano-synaptic device approach with backpropagation	36
Vulnerable objects detection for autonomous driving: A review	35
Model of a switched-capacitor programmable voltage reference for ultra low-power applications	35
Energy efficient and high throughput prefix-based pattern matching technique on TCAMs for NIDS	31
Improved adaptive sliding mode control for non-ideal single-inductor dual-output boost converter	27
Multi-harvesting smart solution for self-powered wearable objects: System-level model and transistor-level design	25
Test and diagnosis pattern generation for distinguishing stuck-at faults and bridging faults	25
Editorial Board	25
Edge computing design space exploration for heart rate monitoring	23
Editorial Board	21
Editorial Board	21
Design-time exploration of voltage switching against power analysis attacks in 14 nm FinFET technology	19
Novel low leakage and energy efficient dual-pullup/dual-pulldown repeater	19
Stumped nature hyperjerk system with fractional order and exponential nonlinearity: Analog simulation, bifurcation analysis and cryptographic applications	19
Glitch-less hardware implementation of block ciphers based on an efficient glitch filter	18
Editorial Board	17
Editorial Board	17
Editorial Board	16
An optimised hardware architecture of the angular-domain cyclostationary detector for cognitive radio communications	16

A PVT tolerant low power wide tuning range differential voltage controlled oscillator design in 90 nm CMOS technology	15
Analytic estimation of jitter and eye diagram based on transmission line time domain response considering skin effect and stochastic crosstalk	15
Picowatt 0.3-V MOS-only voltage reference based on a picoamp cascode current generator	15
Editorial Board	15
Design of an adaptive winner takes all circuit explaining features of binocular rivalry in visual brain	15
Design of highly reliable radiation hardened 10T SRAM cell for low voltage applications	15
On-chip oscillator based temperature-to-digital converter exploiting channel length modulation coefficient λ	15
VLSI implementation of low-power and area efficient parallel memory allocation with EC-TCAM	15
Radiation-aware analog circuit design via fully-automated simulation environment	14
Qualitative data augmentation for performance prediction in VLSI circuits	14
Editorial Board	14
Electronically tunable positive and negative fractional order inductor circuit using single topology	13
A low offset low power CMOS dynamic comparator for analog to digital converters	13
Chaos based speech encryption using microcontroller	13
Comments on “New low power and fast SEC-DAEC and SEC-DAEC-TAEC codes for memories in space application”	13
High-performance unified modular multiplication algorithm and hardware architecture over G(2m)	13
Editorial Board	12
Efficient co-planar adder designs in quantum dot cellular automata: Energy and cost optimization with crossover elimination	12
A non-autonomous chaotic system with no equilibrium	12
A low voltage input boost converter with novel switch driver enhancement technology for indoor solar energy harvesting	11
Design-for-reliability and on-the-fly fault tolerance procedure for paper-based digital microfluidic biochips with multiple faults	11
A 10T SRAM architecture with 40 % enhanced throughput for IMC applications benchmarked with CIFAR-10 dataset	11
A high reliability under-voltage lock out circuit for power driver IC	11
BDD-based synthesis approach for in-memory logic realization utilizing Memristor Aided loGIC (MAGIC)	11
A novel filter-bank architecture of 2D-FIR symmetry filters using LUT based multipliers	11
A highly-linear, sub-mW LNA at 2.4 GHz in 40 nm CMOS process	11
The study of TSV-induced and strained silicon-enhanced stress in 3D-ICs	10
A secure scan architecture using parallel latch-based lock	10
Design and analysis of a frequency division and duty cycle control circuit for on-chip signal synthesis	10
MVSym: Efficient symbiotic exploitation of HLS-kernel multi-versioning for collaborative CPU-FPGA cloud systems	10
Real-time medical image encryption for H-IoT applications using improved sequences from chaotic maps	10
A low-jitter and low-phase noise switched-loop filter PLL using fast phase-error correction and dual-edge phase comparison technique	10
Design of analog front-end integrated circuit of tactile sensor for human-machine interface	10
Ultra-low-power one-hot transmission-gate multiplexer (OTG-MUX) scalable into large fan-in circuits in 28 nm CMOS	10
Deep reinforcement learning assisted reticle floorplanning with rectilinear polygon modules for multiple-project wafer	10
A rail-to-rail high speed comparator with LVDS output in 0.18-μ	9
Generating pseudo-random numbers with a Brownian system	9
High-performance and low-power decoder circuits for SRAMs using mixed-logic scheme	8
Multi-bit error detection and correction technique using HVDK (Horizontal-Vertical-Diagonal-Knight) parity	8
A 15.13 mW 3.2 GHz 8-bit carry look-ahead adder using single-phase all-N-transistor logic	8
Digital background calibration algorithm for pipelined ADC based on time-delay neural network with genetic algorithm feature selection	8
Learning placement order for constructive floorplanning	8
A Machine Learning approach for anomaly detection on the Internet of Things based on Locality-Sensitive Hashing	8
APoX-M: Accelerate deep point cloud analysis via adaptive graph construction	8
Ensemble learning model for effective thermal simulation of multi-core CPUs	8
An effective routability-driven packing algorithm for large-scale heterogeneous FPGAs	8
Exploring BTI aging effects on spatial power density and temperature profiles of VLSI chips	8
ARS-Flow 2.0: An enhanced design space exploration flow for accelerator-rich system based on active learning	8
A 2.0–2.9 GHz ring-based injection-locked clock multiplier using a self-alignment frequency-tracking loop for reference spur reduction	7
Multi-cut based architectural obfuscation and handprint biometric signature for securing transient fault detectable IP cores during HLS	7

VLSI mask optimization: From shallow to deep learning	7
Design and research of grounding current monitoring device for converter transformer core and clamp	7
Coexistence of infinite attractors in a fractional-order chaotic system with two nonlinear functions and its DSP implementation	7
Breaking LPA-resistant cryptographic circuits with principal component analysis	7
Synthesis of representative critical path circuits considering BEOL variations for deep sub-micron circuits	7
On-board processing for autonomous drone racing: An overview	7
Energy efficient multiply-accumulate unit using novel recursive multiplication for error-tolerant applications	7
Self calibrated cooler-less microbolometer readout architecture	7
A broadband MVDR beamforming core for ultrasound imaging	7
Proposal and analysis of relative stability in mixed CNT bundle for sub-threshold interconnects	7
A 85dB-SNDR 50 kHz bootstrapping-free resistor-less SC Delta-Sigma modulator IP block for PVT-robust low-power ADCs	7
Robust power grid network design considering EM aging effects for multi-segment wires	7
LA-ring based non-linear components: Application to image security	6
SEAM: A synergetic energy-efficient approximate multiplier for application demanding substantial computational resources	6
Litho-NeuralODE 2.0: Improving hotspot detection accuracy with advanced data augmentation, DCT-based features, and neural ordinary differential equations	6
A novel architecture of high performance fully differential two stage RFC OTA designed using DFVF and hybrid cascode compensation techniques	6
CCTA based four different pairs of mutually coupled circuit using single topology	6
Electronic equivalent of a pump-modulated erbium-doped fiber laser	6
An efficient XOR-free implementation of polar encoder for reconfigurable hardware	6
Innovative feedback approach for high-performance low-voltage current mirror	6
Design of self-recovering low-cost multiple-node-upset-tolerant latch	6
A novel tunable gain CMOS buffer amplifier for large resistive loads	6
A new three-dimensional conservative system with non - Hamiltonian energy and its synchronization application	6
Simulated annealing assisted NSGA-III-based multi-objective analog IC sizing tool	6
A three-stage single-miller CMOS OTA with no lower load capacitor limit	6
Re-configurable parallel Feed-Forward Neural Network implementation using FPGA	6
A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow	6
Low power, high speed approximate multiplier for error resilient applications	6
Universal gates as a cornerstone for next-generation configurable ring oscillator PUFs	6
Design and analysis of a flat gain and linear low noise amplifier using modified current reused structure with feedforward structure	5
Partial evaluation based triple modular redundancy for single event upset mitigation	5
FPGA-based parallel implementation to classify Hyperspectral images by using a Convolutional Neural Network	5
New approach for digital calibration of pipelined analog to digital converters based on secant method	5
An 8 bits, RF UHF-Band DAC based on interleaved bandpass delta sigma modulator assisted by background digital calibration	5
Complete design approach of a 3rd order continuous-time sigma-delta ADC with FIR feedback and low-noise low-distortion op-amp achieving 101.8 dB SNDR and −110dB THD	5
High-resolution calibrated successive-approximation-register analog-to-digital converter	5
Functional validation of highly synthesizable voltage comparator on FPGA	5
Passivity-based non-fragile control of a class of uncertain fractional-order nonlinear systems	5
A C-band low-power sub-1volt current-reused multiphase oscillator	5
Synchronous control of memristive hindmarsh-rose neuron models with extreme multistability	5
Calibration of optimized minimum inductor bandpass filter with controllable bandwidth and stopband rejection	5
Lorenz’s state equations as RC filters	5
Editorial Board	5
Heterogenous ensemble learning driven multi-parametric assessment model for hardware Trojan detection	5
Optimizing machine learning logic circuits with constant signal propagation	5
New partitioned domino circuit for power-efficient wide gates	5
An energy efficient synthesis flow for application specific SoC design	5
Design of novel SMS4-BSK encryption transmission system	5
Multi-frequency weak signal detection based on Liu-like chaotic synchronization system and its hardware circuit implementation	5
A novel low-resource consumption and high-speed hardware implementation of HOG feature extraction on FPGA for human detection	5
Design and implementation of filterbank for MPEG-2/4 AAC system	5
High-performance multiply-accumulate unit by integrating binary carry select adder and counter-based modular wallace tree multiplier for embedding system	5
New low power and fast SEC-DAEC and SEC-DAEC-TAEC codes for memories in space application	5
Agile-AES: Implementation of configurable AES primitive with agile design approach	5
Editorial Board	5
BΔ-NIS: Performance analysis of an efficient data compression technique for on-chip communication network	4
Editorial Board	4
Editorial Board	4
Design and application of multiscroll chaotic attractors based on memristors	4
A mathematical programming method for constructing the shortest interconnection VLSI arrays	4
VLFF — A very low-power flip-flop with only two clock transistors	4
Application driven routing for mesh based Network-on-Chip architectures	4
Introduction of a new technique for simultaneous reduction of the delay and leakage current in digital circuits	4
A robust radiation resistant SRAM cell for space and military applications	4
Approximate squaring circuits exploiting recursive architectures	4
Design of a 3-bit 2.2 ps step 357.5 ps range 0.247 μm2 0.85 μW 45 nm All-MOS delay element	4
Accuracy recovery: A decomposition procedure for the synthesis of partially-specified Boolean functions	4
High-speed binary coded decimal digit multipliers with multiple error detection	4
An efficient algorithm for disparity map compression based on spatial correlations and its low-cost hardware architecture	4
The art of temporal decoupling	4
HDLBC: A lightweight block cipher with high diffusion	4
FPGA-based Physical Unclonable Functions: A comprehensive overview of theory and architectures	4
Hw/Sw Co-Design technique for 2D fast fourier transform algorithm on Zynq SoC	4
Electronically tunable single FTFNTA-based universal memelement emulator using only grounded passive elements	4
TeRa: Ternary and Range based packet classification engine	4
Automatic correction of RTL designs using a lightweight partial high level synthesis	4
An optimal channel coding scheme for high-speed data communication	4
Delay based hardware Trojan detection exploiting spatial correlations to suppress variations	4
FPGA-based implementation of classification techniques: A survey	4
Two stage Ordered Escape Routing combined with LP and heuristic algorithm for large scaled PCB	4

An area and power efficient VLSI architecture for ECG feature extraction for wearable IoT healthcare applications	4
Emerging monolithic 3D integration: Opportunities and challenges from the computer system perspective	4
DULBC: A dynamic ultra-lightweight block cipher with high-throughput	4
Fluid-to-cell assignment and fluid loading on programmable microfluidic devices for bioprotocol execution	3
A memristive chaotic system with rich dynamical behavior and circuit implementation	3
A sequential strong PUF architecture based on reconfigurable neural networks (RNNs) against state-of-the-art modeling attacks	3
mMIG: Inversion optimization in majority inverter graph with minority operations	3
Efficient VLSI architecture of 3D discrete transformation	3
The Levene test based-leakage assessment	3
Very compact 3D-printed folded branch-line hybrid coupler based on loaded helical-microstrip transmission lines	3
Compact agile Tchebycheff transform variant for temporal compression of neural signals on brain-implantable microsystems	3
A robust Euclidean metric based ID extraction method using RO-PUFs in FPGA	3
Design and implementation of current mode circuit for digital modulation	3
Experimental study of terrain coverage of an autonomous chaotic mobile robot	3
A novel one-equilibrium memristive chaotic system with multi-parameter amplitude modulation and large-scale offset boosting	3
On Minimizing Charge Injection Error Using Multi-Dummy Switches With Enhanced Linearity	3
A Novel four - Wing chaotic system with multiple attractors based on hyperbolic sine: Application to image encryption*	3
A novel class-E class-D doherty power amplifier based on past matching network with linearity region extension and flat output power	3
High-performance anti-series diode ring amplifier for switched capacitor circuits	3
BJT induced dark current in CMOS image sensors	3
High quality hypergraph partitioning for logic emulation	3
An aging monitoring scheme for SRAM decoders	3
Neural network ℒ1	3
AiTO: Simultaneous gate sizing and buffer insertion for timing optimization with GNNs and RL	3
Time redundancy and gate sizing soft error-tolerant based adder design	3
A chaotic PRNG tested with the heuristic Differential Evolution	3
Designing efficient FPGA tiles for power-constrained ultra-low-power applications	3
Orthogonal obfuscation based key management for multiple IP protection	3
PDQRRFF: Poisson-distributed quantum random reversible flip flop generator for BIST	3
Design of high-efficiency complex multiplier for fault-tolerant computation	3
A general and accurate pattern search method for various scenarios	3
A hybrid memory polynomial digital predistortion model for RF transmitters	3
Accelerating large-scale multi-scalar multiplication in Zk-SNARK through exploiting its multilevel parallelism	3
A transparent virtual channel power gating method for on-chip network routers	3
Design and implementation of virtual-single-length turbo decoder for multi-user parallel decoding	3
Lightweight encryption mechanism with discrete-time chaotic maps for Internet of Robotic Things	3
Plug N’ PIM: An integration strategy for Processing-in-Memory accelerators	3
Hardware design for blind source separation using fast time-frequency mask technique	3
High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic	3
A compact structure for triple-memristor maps with a hyperplane of fixed points	3
An LA-group based design of the non-linear component of block cipher	3
Synchronization of mutual coupled fractional order one-sided lipschitz systems	3
3-D coarse-grained reconfigurable array using multi-pole NEM relays for programmable routing	3
Lorenz system as a filter	3
Optimal design of mixed dielectric coaxial-annular TSV using GWO algorithm based on artificial neural network	3
SIEAA: Significant input extraction-based error optimized approximate adder for error resilient application	3
A fine-grained mixed precision DNN accelerator using a two-stage big–little core RISC-V MCU	2
Analysis of memristive maps with asymmetry	2
Design and implementation of congestion aware router for network-on-chip	2
High-efficiency CMOS charge pump for ultra-low power RF energy harvesting applications	2
Efficient FPGA implementation of RNS Montgomery multiplication using balanced RNS bases	2
Standard-compliant parallel SystemC simulation of loosely-timed transaction level models: From baremetal to Linux-based applications support	2
Collision-free arbitrary-order chaotic path generator for differential robots	2
Comparison of two new chaos-based pseudorandom number generators implemented in microcontroller	2
WDP-BNN: Efficient wafer defect pattern classification via binarized neural network	2
Energy-efficient architecture for high-performance FIR adaptive filter using hybridizing CSDTCSE-CRABRA based distributed arithmetic design: Noise removal application in IoT-based WSN	2
A new hardware Trojan detection technique using deep convolutional neural network	2
An analytical placement algorithm with looking-ahead routing topology optimization	2
Convex optimization of random dynamic voltage and frequency scaling against power attacks	2
Hardware-efficient algorithm and architecture design with memory and complexity reduction for semi-global matching	2
An ultra-wideband low noise amplifier with cascaded flipped-active inductor for cognitive radio applications	2
Building discrete maps with memristor and multiple nonlinear terms	2
A frequency boosting technique for cold-start charge pump units	2
SAND-2: An optimized implementation of lightweight block cipher	2
Linear Clock Tree Topology for Dynamic Source Synchronous and Fully Synchronous 3-D Interfaces	2
FPGA implementation of PUF based key generator for secure communication in IoT	2
An effective watermarking technique using BTC and SVD for image authentication and quality recovery	2
Mathematical analysis and circuit emulator design of the three-valued memristor	2
A non-degenerate n-dimensional integer domain chaotic map model with application to PRNG	2
Improving the thermal reliability of photonic chiplets on multicore processors	2
A novel systolic array processor with dynamic dataflows	2
Mixed-radix, virtually scaling-free CORDIC algorithm based rotator for DSP applications	2
Implementation of a fully integrated memristive Chua’s chaotic circuit with a voltage-controlled oscillator	2
A reference sampling ΔΣ subsa	2
Design of CMOS fully differential multipath two-stage OTA with boosted slew rate and power efficiency	2
A highly robust RF 65 nm CMOS power amplifier design using Quasi-Newton control algorithm for wireless system	2
Low power time-domain rail-to-rail comparator with a new delay element for ADC applications	2
Digital synchronization of the MACM chaotic system by using PIC24-microcontrollers and the SPI-protocol	2
A new adaptive selection strategy for reducing latency in networks on chip	2
A digitally controlled adaptive LDO for power management unit in sensor node	2
A PUS based nets weighting mechanism for power, hold, and setup timing optimization	2
A new 4D Memristor chaotic system: Analysis and implementation	2
Efficient design of decimation filter using linear programming and its FPGA implementation	2
Design of a novel 1-bit full adder with hybrid logic for full-swing, area-efficiency, and high-speed	2
Design and optimization of on-chip thick-plated copper-transformers for galvanic isolated DC-DC converter achieving up to 38.9% peak efficiency	2
HashHeat: A hashing-based spatiotemporal filter for dynamic vision sensor	2
Low power chaotic oscillator employing CMOS	2
Machine learning application for cell delay accuracy improvement at post-placement stage: A case study for combinational cells	2
ProHys PUF: A Proteresis - Hysteresis switch based Physical Unclonable Function	2
High speed VLSI architecture for improved region based active contour segmentation technique	2
Editorial Board	2
Study of the dynamical behavior of an Ikeda-based map with a discrete memristor	2
LQNTL: Low-overhead quadruple-node-upset self-recovery latch based on triple-mode redundancy	2
A new low-power Dynamic-GDI full adder in CNFET technology	1
A high-speed 13-bit two-step single-slope ADC for large array CMOS image sensors	1