Integration-The VLSI Journal

Article	Citations
A high reliability under-voltage lock out circuit for power driver IC	118
Generating pseudo-random numbers with a Brownian system	86
Model of a switched-capacitor programmable voltage reference for ultra low-power applications	82
Dynamics analysis and application of multi-stable Hopfield neural networks under pulsed current stimulation	65
Enhancing logic optimization of Alliance tool based on directed acyclic graphs	51
Design-for-reliability and on-the-fly fault tolerance procedure for paper-based digital microfluidic biochips with multiple faults	51
Low-power hardware architecture of optimized logarithmic square rooter with enhanced error compensation for error-tolerant systems	49
Deep reinforcement learning assisted reticle floorplanning with rectilinear polygon modules for multiple-project wafer	48
Weak signal detection and circuit implementation based on a novel 3D chaotic synchronization system	47
A sub-1V wide-temperature-range voltage reference with low line sensitivity and high temperature stability	45
Real-time FPGA implementation of a blind audio watermarking scheme based on discrete cosine transform and improved spread spectrum	45
An adaptive discrete dynamic filled function algorithm for directed acyclic graph partitioning	43
An absolute capacitive rotary encoder with DC offset correction capacitor arrays	41
Exploring BTI aging effects on spatial power density and temperature profiles of VLSI chips	39
Chaos based speech encryption using microcontroller	33
A general and accurate pattern search method for various scenarios	30
A new three-dimensional conservative system with non - Hamiltonian energy and its synchronization application	30
Accelerating large-scale multi-scalar multiplication in Zk-SNARK through exploiting its multilevel parallelism	26
Efficient processor verification by tautologies-derived universal properties model checking	26
HDLBC: A lightweight block cipher with high diffusion	26
Design insights for implementing a PRNG with fractional Lorenz system on ESP32 and FPGA	25
A transparent virtual channel power gating method for on-chip network routers	24
An LA-group based design of the non-linear component of block cipher	24
Design and implementation of virtual-single-length turbo decoder for multi-user parallel decoding	23
Plug N’ PIM: An integration strategy for Processing-in-Memory accelerators	22

Inductorless dynamic logic based on 2ϕ-Josephson junctions	21
Hardware-efficient architecture of spiking neural networks based on sign-magnitude stochastic computing	21
Design and application of multiscroll chaotic attractors based on memristors	21
Encoding and decoding devices based on memristor-diode crossbar-array and CMOS logic for spiking neural networks	20
Design of high-efficiency complex multiplier for fault-tolerant computation	19
Higher-order filters based on the Mittag-Leffler function	18
Complete design approach of a 3rd order continuous-time sigma-delta ADC with FIR feedback and low-noise low-distortion op-amp achieving 101.8 dB SNDR and −110dB THD	18
High-robustness CMOS voltage reference for automotive applications with PVT variation tolerance	18
3-D coarse-grained reconfigurable array using multi-pole NEM relays for programmable routing	18
A 180-nm CMOS fully digital chaotic Lorenz system	18
Lightweight encryption mechanism with discrete-time chaotic maps for Internet of Robotic Things	17
Design of Flash analog-to-digital converter based on MoS2 FET	17
Cooperative control of multi-scroll attractors in chaotic neural network with double potential wells and staircase wells and its application in image encryption	17
Efficient CNFET-based ternary logic design with emphasis on half-adder and multiplier circuits	17
Dynamical probing of pendulum arm spurred by a Rayleigh-duffing oscillator implemented on a microcontroller	17
On-chip SRAM macro with 0.45μW/Mbit-leakage data retention using simultaneous control of source-line and body-line biasing	17
Digital synchronization of the MACM chaotic system by using PIC24-microcontrollers and the SPI-protocol	16
Hardware-efficient algorithm and architecture design with memory and complexity reduction for semi-global matching	16
ProHys PUF: A Proteresis - Hysteresis switch based Physical Unclonable Function	16
A 2.69-ppm/°C curvature-compensated BJT-based bandgap voltage reference	16
A four-dimensional chaotic system with coexisting attractors and its backstepping control and synchronization	15
Design and implementation of congestion aware router for network-on-chip	15
Error expectation-driven design and energy optimization of approximate multipliers	15
Slow and fast dynamics in neural model: Effects of fast and slow variable assignments	15
LQNTL: Low-overhead quadruple-node-upset self-recovery latch based on triple-mode redundancy	15
Fluid-control codesign for paper-based digital biochips using volumetric memory networks: A predictive modelling approach	15
Differential receiver with 2 × VDD input signals using 1 × VDD devices	14
Lightweight FPGA acceleration framework for structurally tailored multi-version MobileNetV1	14
Real-time neural identification using a recurrent wavelet first-order neural network of a chaotic system implemented in an FPAA	14
Hardware designs for convolutional neural networks: Memoryful, memoryless and cached	14
A novel intrinsic-parameters-correlation enhancement technology applied to accurately extract GaN HEMT small-signal model parameters	14
Design of novel low cost triple-node-upset self-recoverable hardened latch	14
Design of robust analog integrated circuit based on process corner performance variability minimization	14
Approximate Toom–Cook FFT with sparsity aware error tuning in a shared memory architecture	14
A 6.4-Gbps 0.41-pJ/b fully-digital die-to-die interconnect PHY for silicon interposer based 2.5D integration	13
Area-efficient architectures of Midori lightweight block cipher for resource constrained devices	13
Clock mesh synthesis through dynamic programming with physical parameters consideration	13
MT-PUF: A reconfigurable intrinsic PUF for MRAM TCAM achieving 0.07%/10 ℃ and 0.44%/0.1 V sensitivity	13
A Quad-XOR cross-coupled FPGA TRNG with multimodal metastability and application-level validation	13
Low-	13
Neurochaos feature transformation for Machine Learning	13
Secure access microcontroller system based on fingerprint template with hyperchaotic encryption	13
Matching constraint extraction for analog integrated circuits layout via edge classify	13
Simple memristive chaotic systems with complex dynamics	13
Fine-grained data integration for high throughput and bandwidth-efficient computation on FPGAs	13
A Consistent Conditional Probability Estimator based Fixed-Width Booth Multiplier	13
Efficient hardware mapping of Boolean substitution boxes based on functional decomposition for RFID and ISM band IoT applications	13
Nonlinear analysis, circuit implementation, and application in image encryption of a four-dimensional multi-scroll hyper-chaotic system	13
Power Gated-SRAM and novel header–footer multiplexer based ultra low power Look-Up Table design	12
A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications	12

ExpanderGraph-128: A novel graph-theoretic block cipher with formal security analysis and hardware implementation	12
Editorial Board	12
A parametric, scalable and efficient architecture for schoolbook polynomial multiplier for lattice-based cryptography	12
Spherical chaotic trajectory tracking and formation of unmanned aerial vehicles in master–slave configuration with intermediary system	12
Analysis of hazards in hardware implementations of cryptographic substitution boxes (S-boxes) with hazard location and mitigation	12
Non-equilibrium oscillator with a diode: Dynamics and application	12
Built-in Self-prevention (BISP) for runtime ageing effects of TSVs in 3D ICs	12
LBDR: A load-balanced deadlock-free routing strategy for chiplet systems	12
FPGA routing congestion prediction combining DAGNN and GCN	12
Optimization and FPGA implementation of Echo State Networks to predict the chaotic Lorenz system	12
Concurrent Steiner Tree Selection for Global routing with EUVL Flare Reduction	12
High performance mixed-radix NTT design for post quantum cryptography	11
The effect of ECG data variability on side-channel attack success rate in wearable devices	11
Integrating error correction and detection techniques in RISC-V processor microarchitecture for enhanced reliability	11
A 0.2-V 1.2 nW 1-KS/s SAR ADC with a novel comparator structure for biomedical applications	11
Design of a dynamic obfuscation-based strong PUF resistant to modeling attacks and mutual authentication protocol	11
FPGA-enhanced system-on-chip for finger vein-based biometric system using novel DL model	11
Universal Triangular Matrices for Representation of any Radix-Rx FFT Algorithms	11
A simulation optimization method for Verilog-AMS IBIS model under overclocking	11
Hot-spot aware thermoelectric array based cooling for multicore processors	11
A tunable hardware-optimized unsigned hybrid square rooter for error-tolerant computing system applications	11
Double-node-upset-hardened full-subtractor applying MTJ for the high energy physics experiments	10
Unified chip hardware architecture of KD-tree mean-based trainer and speeding-up classifier with repeat-point searching for various applications	10
Approximate digital-in analog-out multiplier with asymmetric nonvolatility and low energy consumption	10
A self-control leakage-suppression block for low-power high-efficient static logic circuit design in 22 nm CMOS process	10
Third-order resonance networks and their application to chaos generation	10
Symmetric synchronization behavior of multistable chaotic systems and circuits in attractive and repulsive couplings	10
Robust optimization algorithm of RF MEMS switches considering uncertainties	10
Fixed-point implementations for feed-forward artificial neural networks	10
AND-Logic embedded 7T SRAM-based backplane circuit for low-power micro-displays	10
Genetic algorithm-optimized fuzzy controller for the calibration of pipelined ADCs	10
High speed and high performance approximate multipliers for error resilient applications	10
Intelligent and kernelized placement: A survey	10
An improved reconfigurable logic in resistive random access memory	10
An efficient open-source design and implementation framework for non-quantized CNNs on FPGAs	10
CAPUF: Design of a configurable circular arbiter PUF with enhanced security and hardware efficiency	10
Approximate subtractors designed for image processing applications	10
Preferential fault-tolerance multiplier design to mitigate soft errors in FPGAs	10
An area-efficient and low-latency GF(2m) multiplier for FPGA applications	9
Gated logic controlled 10T-SRAM for low-power bidirectional ring oscillators	9
MORL-IC: Multi-objective reinforcement learning approaches for analog integrated circuit optimization	9
Innovative nonlinear component generator inspired by squirrel search algorithm	9
A novel grounded and electronically tunable resistorless capacitance multiplier based on a voltage conveyor transconductance amplifier	9
EOHEAA: Error-Optimized Hardware-Efficient Approximate Adder for energy-aware error-resilient applications	9
AI/ML algorithms and applications in VLSI design and technology	9
A lossless floating capacitance multiplier based on the single DDCC−	9
ANAS: Software–hardware co-design of approximate neural network accelerators via neural architecture search	9
Picowatt 0.3-V MOS-only voltage reference based on a picoamp cascode current generator	9
Alternative method to reveal encoded images via Gaussian distribution functions	9
Fast electromigration stress analysis using Low-Rank Balanced Truncation for general interconnect and power grid structures	9
Incremental/decremental memristor utilizing solely a voltage controlled second-generation current conveyor	9
Hardware efficient design and implementation of multiplierless FIR filters using Sparse PSO on FPGA and ASIC	9
Optimizing code allocation for hybrid on-chip memory in IoT systems	9
Analytic estimation of jitter and eye diagram based on transmission line time domain response considering skin effect and stochastic crosstalk	8
An effective routability-driven packing algorithm for large-scale heterogeneous FPGAs	8
A low-jitter and low-phase noise switched-loop filter PLL using fast phase-error correction and dual-edge phase comparison technique	8
Editorial Board	8
A hybrid entropy source scheme for true random number generator	8
The study of TSV-induced and strained silicon-enhanced stress in 3D-ICs	8
Design and analysis of a frequency division and duty cycle control circuit for on-chip signal synthesis	8
Energy efficient multiply-accumulate unit using novel recursive multiplication for error-tolerant applications	8
A real-time integrated eye tracker with in-pixel image processing in 0.18-μm CMOS technology	8
High-performance unified modular multiplication algorithm and hardware architecture over G(2m)	8
JoBiS: Joint capacitance and inductance bit stuffing CAC for interposer based multi-chip Deep Learning Accelerator	8
An optimised hardware architecture of the angular-domain cyclostationary detector for cognitive radio communications	8
Comments on “New low power and fast SEC-DAEC and SEC-DAEC-TAEC codes for memories in space application”	8
Editorial Board	8
Resource-efficient and ultra-high throughput LDPC decoder for CCSDS near-earth standard	8
Machine learning based fast and accurate High Level Synthesis design space exploration: From graph to synthesis	8
MVSym: Efficient symbiotic exploitation of HLS-kernel multi-versioning for collaborative CPU-FPGA cloud systems	8
A 15.13 mW 3.2 GHz 8-bit carry look-ahead adder using single-phase all-N-transistor logic	8
Editorial Board	8
An efficient architecture of truncated booth multiplier for AI application	8
Electronic equivalent of a pump-modulated erbium-doped fiber laser	8
CompreCity: Accelerating the Traveling Salesman Problem on GPU with data compression	8
An efficient XOR-free implementation of polar encoder for reconfigurable hardware	8
Digital background calibration algorithm for pipelined ADC based on time-delay neural network with genetic algorithm feature selection	7
Optimal design of mixed dielectric coaxial-annular TSV using GWO algorithm based on artificial neural network	7
High-resolution calibrated successive-approximation-register analog-to-digital converter	7
Lorenz system as a filter	7

Language semantics to support secure computation and communication in embedded systems via hardware monitors	7
Approximate squaring circuits exploiting recursive architectures	7
A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow	7
A secure scan architecture using parallel latch-based lock	7
VLFF — A very low-power flip-flop with only two clock transistors	7
A progressive self-training semi-supervised model to enhance discontinuous change detection	7
AI-enabled image processing approach for efficient clustering and identification of hardware Trojans	7
An area and power efficient VLSI architecture for epileptic seizure detection using Transpose Form Retimed Delayed LMS filter and spiking neural networks	7
Hardware architecture design for complementary ensemble empirical mode decomposition algorithm	7
Design of a soft error resilient 13T SRAM architecture for radiation-prone environments in FinFET 18 nm technology	7
An efficient algorithm for disparity map compression based on spatial correlations and its low-cost hardware architecture	7
Comparison of integer-order chaotic attractors as randomness source in collision-free robotic exploration methods	7
Electronically tunable floating DXCCDITA-based universal memelement emulator and its applications	7
A novel low-resource consumption and high-speed hardware implementation of HOG feature extraction on FPGA for human detection	7
Design and analysis of faithful parallel mean filter using approximate adders and 4:2 compressors for low-power VLSI architectures	7
A non-degenerate n-dimensional integer domain chaotic map model with application to PRNG	6
A hybrid memory polynomial digital predistortion model for RF transmitters	6
A wide-input-range boost converter with three-phase self-start and adaptive zero current detector for photovoltaic energy harvesting	6
True canonical third-order resonance-based oscillators and application to chaos generation	6
Design of joint reconfigurable hybrid adder and subtractor using FinFET and GnrFET technologies	6
A frequency boosting technique for cold-start charge pump units	6
A 158 nw, 2.877 ppm/°C resistorless bandgap reference circuit	6
Low-cost compression architecture based on extended DCT algorithm	6
Design of A prototype 128 × 128 ROIC array for 2.6 μm-wavelength SWIR image sensor applications	6
Automatic correction of RTL designs using a lightweight partial high level synthesis	6
Enhanced debugging and fault identification in digital VLSI circuits using Automated Multi Distance Spatial Temporal Graph Neural Networks	6
An energy-efficient image filtering interpolation algorithm using domain-specific dynamic reconfigurable array processor	6
A fast and high-performance global router with enhanced congestion control	6
Study of the dynamical behavior of an Ikeda-based map with a discrete memristor	6
Content-addressable memory using selective-charging and adaptive-discharging scheme for low-power hardware search engine	6
Design of CMOS fully differential multipath two-stage OTA with boosted slew rate and power efficiency	6
A novel class-E class-D doherty power amplifier based on past matching network with linearity region extension and flat output power	6
Review: Application and development of machine learning in semiconductor manufacturing for automated wafer map pattern recognition and classification	6
Ultra-low power linearized FVF based BD double diffusor double differential pair transconductor	6
Editorial: 5th meeting for the dissemination and research in the study of complex systems and their applications	6
Accurate closed-form delay formulas for interconnected CMOS gates based on first-order thresholded hybrid systems	6
A high-performance convolution block oriented accelerator for MBConv-Based CNNs	6
An ultra-wideband low noise amplifier with cascaded flipped-active inductor for cognitive radio applications	6
A systematic review of machine learning-driven design space exploration in high-level synthesis	6
Low-temperature-drift voltage reference design using magnetic tunnel junctions	6
A fine-grained mixed precision DNN accelerator using a two-stage big–little core RISC-V MCU	6
RapidPnR: Accelerating the physical design for FPGAs via design-level parallelism	5
Online detection of hardware Trojan enabled packet tampering attack on network-on-chip: A Bayesian approach	5
Integrated DC - DC converter design methodology for design cycle speed up	5
BonnLogic: Delay optimization by And-Or Path restructuring	5
A precision programmable multilevel voltage output and low-temperature-variation CMOS bandgap reference with area-efficient transistor-array layout	5
156 dB low-voltage low-power CMOS exponential function generator circuit	5
MICSim: A modular pre-circuit simulator for mixed-signal compute-in-memory accelerators in CNNs and transformers	5
An area-efficient 1st order noise shaping SAR using C-2C ladder DAC for biomedical applications	5
Nested chopper instrument amplifier with noise modulation for physiological signal sensing	5
Integration mixer: An efficient mixed neural network for memory dynamic stability analysis in high dimensional variation space	5
A low power offset voltage calibration method for flash ADCs	5
Lorenz system manufacturing with a Butterworth filter	5
A high-efficiency feedforward compensation method for capacitor-less LDO	5
Adaptive-precision SIMD architecture for high-throughput and resource-efficient DNN acceleration	5
Editorial Board	5
Circuit implementation of on-chip trainable spiking neural network using CMOS based memristive STDP synapses and LIF neurons	5
Novel hybrid TFET-FinFET 12T SRAM cells with enhanced write margin and read performance	5
A novel RISC-V core for the networking processing processor with bit-level custom instructions and thread-aware fetching architecture	5
Novel fault tolerance topology using corvus seek algorithm for application specific NoC	5
Compact MAX and MIN Stochastic Computing architectures	5
Chosen ciphertext correlation power analysis on Kyber	5
Ring-oscillator-assisted CTR_DRBG on FPGA with improved statistical properties	5
High-throughput and area-efficient architectures for image encryption using PRINCE cipher	5
An on-chip temperature sensor with 0.5 °C resolution and 0.34% linearity error using 180-nm CMOS process	5
Resource-efficient hardware architecture for low-light image enhancement	5
Reinforcement learning-driven net order selection for efficient analog IC routing	5
Hardware implementation of a robust image cryptosystem using reversible cellular-automata rules and 3-D chaotic systems	5
Highly robust power efficient Full Adder and Full Subtractor CiM architecture using 10T SRAM cell	5
Cost-aware test pattern ordering for VLSI using an enhanced LSTNet architecture	5
Novel logic and memory synthesis algorithm for Memristive Hardware Description Language (HDL)	5
A logic device based on memristor-diode crossbar and CMOS periphery as spike router for hardware neural network	5
rel-SLIFMEM: Design and analysis of a reliability-aware neuromorphic system	5
Advanced fault diagnosis in analog and digital VLSI circuits utilizing multi-anchor space-aware temporal convolutional neural network for efficient circuit reliability assessment	5
Design of CMOS VCO with XNOR and transmission gate based delay stages	5
Reviewing the interrelationship between FPGA-based dynamic partial reconfiguration technology and vulnerabilities of side-channel analysis attacks	5
Optimizing value prediction for ILP processors: A design space exploration approach	4
Implementation of imprecise multipliers using 2-bit adder for image processing	4
Fractional-Order PI/PD and PID Controllers in Power Electronics: The step-down converter case	4
A Parity-based Multi-bit Fault-Tolerant Instruction Decoder for RISC-V pipelined soft processor	4
VLSI implementation of low-power and area efficient parallel memory allocation with EC-TCAM	4
Comparative study of planar stacked integrated transformers for MMICs	4
Multi-harvesting smart solution for self-powered wearable objects: System-level model and transistor-level design	4
Design and implementation of deep learning-based object detection and tracking system	4
Dynamics analysis, FPGA implementation, and application in image encryption of a quadruple-wing chaotic system based on hyperbolic sine functions	4
A PSRR enhanced capacitorless LDO with gate capacitance cancellation technique	4
Design of an adaptive winner takes all circuit explaining features of binocular rivalry in visual brain	4
Radiation-aware analog circuit design via fully-automated simulation environment	4
Design, manufacturing, and testing of a flash mass memory unit for Earth observation small satellites	4
CCTA based four different pairs of mutually coupled circuit using single topology	4
Design of synthesizable period-jitter sensor IP with high power reduction and variation resiliency	4
Thermal optimization of analog ICs via transistor-array placement	4
WF-SPR: A weighted single fanout approach for signal probability-based reliability estimation	4
Universal gates as a cornerstone for next-generation configurable ring oscillator PUFs	4
Design of high performance energy efficient CMOS voltage level shifter for mixed signal circuits applications	4