Integration-The VLSI Journal

Papers
(The H4-Index of Integration-The VLSI Journal is 23. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-11-01 to 2025-11-01.)
ArticleCitations
Editorial Board108
A high reliability under-voltage lock out circuit for power driver IC106
Deep reinforcement learning assisted reticle floorplanning with rectilinear polygon modules for multiple-project wafer67
Design-for-reliability and on-the-fly fault tolerance procedure for paper-based digital microfluidic biochips with multiple faults58
Exploring BTI aging effects on spatial power density and temperature profiles of VLSI chips56
Edge computing design space exploration for heart rate monitoring56
Low-power hardware architecture of optimized logarithmic square rooter with enhanced error compensation for error-tolerant systems43
Model of a switched-capacitor programmable voltage reference for ultra low-power applications41
Generating pseudo-random numbers with a Brownian system40
A new three-dimensional conservative system with non - Hamiltonian energy and its synchronization application39
Chaos based speech encryption using microcontroller37
A novel filter-bank architecture of 2D-FIR symmetry filters using LUT based multipliers37
Design and application of multiscroll chaotic attractors based on memristors36
Accelerating large-scale multi-scalar multiplication in Zk-SNARK through exploiting its multilevel parallelism34
A general and accurate pattern search method for various scenarios30
Efficient processor verification by tautologies-derived universal properties model checking29
Emerging monolithic 3D integration: Opportunities and challenges from the computer system perspective27
High-robustness CMOS voltage reference for automotive applications with PVT variation tolerance27
mMIG: Inversion optimization in majority inverter graph with minority operations27
HDLBC: A lightweight block cipher with high diffusion25
Design and implementation of virtual-single-length turbo decoder for multi-user parallel decoding25
A transparent virtual channel power gating method for on-chip network routers25
3-D coarse-grained reconfigurable array using multi-pole NEM relays for programmable routing23
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