Microelectronics Journal

Papers
(The TQCC of Microelectronics Journal is 6. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2020-11-01 to 2024-11-01.)
ArticleCitations
Nanosheet field effect transistors-A next generation device to keep Moore's law alive: An intensive study62
Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes49
A review on emerging negative capacitance field effect transistor for low power electronics42
Comparing bulk-Si FinFET and gate-all-around FETs for the 5 ​nm technology node41
Design of photonic crystal based compact all-optical 2 × 1 multiplexer for optical processing devices40
New electronically adjustable memelement emulator for realizing the behaviour of fully-floating meminductor and memristor32
Performance analysis of silicon nanotube dielectric pocket Tunnel FET for reduced ambipolar conduction28
Ultra-low-power and stable 10-nm FinFET 10T sub-threshold SRAM27
FinFET based SRAMs in Sub-10nm domain27
RF & linearity distortion sensitivity analysis of DMG-DG-Ge pocket TFET with hetero dielectric26
A robust and write bit-line free sub-threshold 12T-SRAM for ultra low power applications in 14 nm FinFET technology25
Ge/Si interfaced label free nanowire BIOFET for biomolecules detection - analytical analysis25
Modeling the threshold voltage of core-and-outer gates of ultra-thin nanotube Junctionless-double gate-all-around (NJL-DGAA) MOSFETs24
Gaussian Mixture Model classifier analog integrated low-power implementation with applications in fault management detection23
Numerical assessment of dielectrically-modulated short- double-gate PNPN TFET-based label-free biosensor22
A review of III-V Tunnel Field Effect Transistors for future ultra low power digital/analog applications22
Negative drain-induced barrier lowering and negative differential resistance effects in negative-capacitance transistors22
Design and simulation of triple metal double-gate germanium on insulator vertical tunnel field effect transistor21
Spin field effect transistors and their applications: A survey21
A novel ultra-low-power CNTFET and 45 nm CMOS based ternary SRAM20
Noise behavior of vertical tunnel FETs under the influence of interface trap states19
Design and implementation of 20-T hybrid full adder for high-performance arithmetic applications19
Improved optical performance in near visible light detection photosensor based on TFET18
Design of efficient approximate 1-bit Full Adder cells using CNFET technology applicable in motion detector systems17
An efficient EEGNet processor design for portable EEG-Based BCIs16
Accurate Dynamic Voltage and Frequency Scaling Measurement for Low-Power Microcontrollors in Wireless Sensor Networks16
Integrated multi-band RF transceiver design for multi-standard applications using 130 ​nm CMOS technology16
Computing-in-memory using voltage-controlled spin-orbit torque based MRAM array16
Analysis on electrical parameters including temperature and interface trap charges in gate overlap Ge source step shape double gate TFET15
Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications15
An ultra-low-power neural signal acquisition analog front-end IC15
Negative capacitance FETs for energy efficient and hardware secure logic designs14
An energy-efficient crypto-extension design for RISC-V14
Performance Optimization of Analog Circuits in Negative Capacitance Transistor Technology14
Disconnected N-doped zigzag ZnO nanoribbon for potential Negative Differential Resistance (NDR) applications14
CNFET-based design of efficient ternary half adder and 1-trit multiplier circuits using dynamic logic14
Voltage differencing buffered amplifier based low power, high frequency and universal filters using 32 nm CNTFET technology14
An intensive approach to optimize capacitive type RF MEMS shunt switch14
Efficient ternary comparator on CMOS technology13
Impact of band gap and gate dielectric engineering on novel Si0.1Ge0.9-GaAs lateral N-type charge plasma based JLTFET13
Enabling on-device classification of ECG with compressed learning for health IoT13
Research progress and applications of memristor emulator circuits13
Implementation of highly optimized optical all logic gates on a single chip using Ti-diffused lithium-niobate for high-speed processing in combinational circuits13
Analytical model of subthreshold drain current for nanoscale negative capacitance junctionless FinFET13
Design and implementation of true random number generators based on semiconductor superlattice chaos13
Impact of temperature and interface trapped charges variation on the Analog/RF and linearity of vertically extended drain double gate Si0.5Ge0.5 source tunnel FET13
Structure design and optimization of SOI high-temperature pressure sensor chip12
Capacitance response of concave well substrate touch-mode capacitive pressure sensor: Mathematical analysis and simulation12
M-RO PUF: A portable pure digital RO PUF based on MUX unit12
Low power CMOS differential ring VCO designs using dual delay stages in 0.13 ​μm technology for wireless applications12
Total ionizing dose hardness analysis of transistors in commercial 180 nm CMOS technology12
Newly energy-efficient SRAM bit-cell using GAA CNT-GDI method with asymmetrical write and built-in read-assist schemes for QR code-based multimedia applications12
Analysis of I–V-T characteristics of Be-doped AlGaAs Schottky diodes grown on (100) GaAs substrates by molecular beam epitaxy12
Triple bands Class-C voltage-controlled power oscillator based on high-quality factor asymmetry inductor12
RF/Analog performance of GaAs Multi-Fin FinFET with stress effect12
A low-power asynchronous hardware implementation of a novel SVM classifier, with an application in a speech recognition system12
Half-select disturb-free single-ended 9-transistor SRAM cell with bit-interleaving scheme in TMDFET technology12
Fractional-order inverse filters revisited: Equivalence with fractional-order controllers12
Electronically tunable higher-order quadrature oscillator employing CDBA12
Impact of temperature variation on noise parameters and HCI degradation of Recessed Source/Drain Junctionless Gate All Around MOSFETs11
Computationally efficient memristor model based on Hann window function11
Mechanical strain and bias-stress compensated, 6T-1C pixel circuit for flexible AMOLED displays11
A 1-V 2.69-ppm/°C 0.8-μW bandgap reference with piecewise exponential curvature compensation11
Low to high-frequency noise behavior investigation of steeper sub-threshold swing NC-GeFinFET11
Design and analysis of a dual gate tunnel FET with InGaAs source pockets for improved performance11
A push-pull FVF based LDO voltage regulator with slew rate enhancement at the gate of power transistor11
Next generation QCA technology based true random number generator for cryptographic applications11
A chaos-based true random number generator based on OTA sharing and non-flipped folded Bernoulli mapping for high-precision ADC calibration11
An FPGA-based memristor emulator for artificial neural network11
An ultra-low-power CNFET based dual V ternary dynamic Half Adder11
Efficient hardware design of a deep U-net model for pixel-level ECG classification in healthcare device11
A negative capacitance FET based energy efficient 6T SRAM computing-in-memory (CiM) cell design for deep neural networks11
Experimental demonstration of 62.5 Mbps VLC link for healthcare infrastructures by incorporating limiting amplifier as an amplification scheme11
Advances in neuromorphic devices for the hardware implementation of neuromorphic computing systems for future artificial intelligence applications: A critical review11
Orthogonal study and analysis of variance on a thermal management system for high-power LED package10
A hardware-efficient computing engine for FPGA-based deep convolutional neural network accelerator10
An ultra-low-power bulk-driven subthreshold super class-AB rail-to-rail CMOS OTA with enhanced small and large signal performance suitable for large capacitive loads10
Naive Bayes classifier based on memristor nonlinear conductance10
A process variation resilient spintronic true random number generator for highly reliable hardware security applications10
Investigation of negative DIBL effect for ferroelectric-based FETs to improve MOSFETs and CMOS circuits10
PFD with improved average gain and minimal blind zone combined with lock-in detection for fast settling PLLs10
A 5 MHz-BW 71.7-dB SNDR two-step hybrid-domain ADC in 65-nm CMOS10
Analysis of nanoscale digital circuits using novel drain-gate underlap DMG hetero-dielectric TFET10
Impact of doping concentration and recess depth to achieve enhancement mode operation in β-Ga2O3 MOSFET10
A 26-ppm/oC, 13.2-ppm/V, 0.11%-inaccuracy picowatt voltage reference with PVT compensation and fast startup10
Steep-subthreshold slope dual gate negative capacitance junction less FET with dead channel: TCAD approach for digital/ RF applications9
All-optical diode for terahertz optical power rectification based on two-dimensional photonic crystals9
CPW-fed elliptical shaped patch antenna with RF switches for wireless applications9
Analytical drain current model development of twin gate TFET in subthreshold and super threshold regions9
Thermal layout optimization for 3D stacked multichip modules9
A high reliability physically unclonable function based on multiple tunable ring oscillator9
A C4.5 decision tree classifier based floorplanning algorithm for System-on-Chip design9
Fabrication and high-frequency characterization of low-cost fan-in/out WLP technology with RDL for 2.5D/3D heterogeneous integration9
Advanced implementation of Montgomery Modular Multiplier9
Electromagnetic modelling and analysis of RF MEMS capacitive shunt switch for 5G applications9
Impact on performance of dual stack hetero- gated dielectric modulated TFET biosensor due to Si1-xGex pocket variation9
Design, implementation, and estimation of MFCV for 4-different position of human body using FPGA9
A critical evaluation based on Lattice Boltzmann method of nanoscale thermal behavior inside MOSFET and SOI-MOSFET9
Performance analysis of dielectrically modulated InSb/Si TFET based label free biosensor9
Self-compliance and high-performance GeTe-based CBRAM with Cu electrode9
A novel read decoupled 8T1M nvSRAM cell for near threshold operation9
Dielectric surface roughness scattering induced crosstalk performance of coupled MCB interconnects9
A digital background calibration scheme for non-linearity of SAR ADC using back-propagation algorithm9
A 32 Gb/s PAM-16 TX and ADC-Based RX AFE with 2-tap embedded analog FFE in 28 nm FDSOI8
Design and simulation of junctionless nanowire tunnel field effect transistor for highly sensitive biosensor8
Radio frequency analog-to-digital converters: Systems and circuits review8
All-digital successive approximation TDC in time-mode signal processing8
Column amplification stages in CMOS image sensors based on incremental sigma-delta ADCs8
Hybrid small-signal modeling of GaN HEMTs based on improved genetic algorithm8
Design and analysis of high-performance double-gate ZnO nano-structured thin-film ISFET for pH sensing applications8
Comprehensive characterization of vertical GaN-on-GaN Schottky barrier diodes8
DDCC-based meminductor circuit with hard and smooth switching behaviors and its circuit implementation8
Wide-band compact floating memristor emulator configuration with electronic/resistive adjustability8
Design of a high linear and ultra-wideband LNA using post distortion star feedback method8
Pair-Wise Urdhava-Tiryagbhyam (UT) Vedic Ternary multiplier8
Negative capacitance FET based energy efficient and DPA attack resilient ultra-light weight block cipher design8
A 15 mV-input and 71%-efficiency boost converter with 22 mV output ripple for thermoelectric energy harvesting application8
An FPGA-based online reconfigurable CNN edge computing device for object detection8
A robust architecture of physical unclonable function based on Memristor crossbar array8
An energy harvesting system for time-varying energy transducers with FOCV based dynamic and adaptive MPPT for 30 nW to 4 mW of input power range8
Current collapse degradation in GaN High Electron Mobility Transistor by virtual gate8
Design of radiation-hardened memory cell by polar design for space applications8
Threshold voltage modeling of Gaussian-doped Dual work function Material Cylindrical Gate-all-around (CGAA) MOSFET considering the effect of temperature and fixed interface trapped charges8
Low mismatch high-speed charge pump for high bandwidth phase locked loops8
2μs row time 12-bit column-parallel single slope ADC for high-speed CMOS image sensor8
A reconfigurable and compact hardware architecture of CLEFIA block cipher with multi-configuration7
Design and performance assessment of a vertical feedback FET7
Gate electrode work function engineered JAM-GS-GAA FinFET for analog/RF applications: Performance estimation and optimization7
A 12-bit SAR ADC with a reversible VCM-based capacitor switching scheme7
Distribution optimization of thermal through-silicon via for 3D chip based on thermal-mechanic coupling7
UWB down-conversion mixer using an IM3 cancellation modified technique for zero and low IF applications7
A 5T1C pixel circuit compensating mobility and threshold voltage variation7
Improved modeling of flicker noise including velocity saturation effect in FinFETs and experimental validation7
Investigation on effect of AlN barrier thickness and lateral scalability of Fe-doped recessed T-gate AlN/GaN/SiC HEMT with polarization-graded back barrier for future RF electronic applications7
CNTFET design of a multiple-port ternary register file7
Lifetime prediction and analysis of AlGaN/GaN HEMT devices under temperature stress7
A multiple-sensitivity Hall sensor featuring a low-cost temperature compensation circuit7
An augmented small-signal model of InP HBT with its analytical-based parameter extraction technique7
A curvature-compensated bandgap voltage reference with a temperature coefficient trimming circuit7
Impact of self-heating on RF/analog and linearity parameters of DMG FinFETs in underlap and overlap configurations7
Impact of biomolecules position and filling area on the sensitivity of hetero stack gate MOSFET7
Template attacks on ECC implementations using performance counters in CPU7
Impact of interface trap charge and temperature on the performance of epitaxial layer tunnel field effect transistor7
A 128 Kb DAC-less 6T SRAM computing-in-memory macro with prioritized subranging ADC for AI edge applications7
Low walk error multi-stage cascade comparator for TOF LiDAR application7
A 4H–SiC double trench MOSFET with split gate and integrated MPS diode7
A high-sensitivity, low-noise dual-band RF energy harvesting and managing system for wireless bio-potential acquisition7
A nano-watt power-on reset circuit with Brown-Out detection capability7
Back-gate bias effect on the linearity of pocket doped FDSOI MOSFET7
Exact and approximate multiplications for signal processing applications6
A 2.4 GHz receiver with a current-reused inductor-less noise-canceling balun LNA in 40 nm CMOS6
Junctionless-accumulation-mode stacked gate GAA FinFET with dual-k spacer for reliable RFIC design6
A 2.6 GΩ, 1.4 μVrms current-reuse instrumentation amplifier for wearable electrocardiogram monitoring6
Unified floating immittance emulator based on CCTA6
Shunt resistance spatial variations in amorphous silicon solar cells6
A comparative study of SiC MOSFETs with and without integrated SBD6
A 9-bit 8.3 MS/s column SAR ADC with hybrid RC DAC for CMOS image sensors6
A high-speed and triple-node-upset recovery latch with heterogeneous interconnection6
Electronic microstructure and thermal conductivity modeling of semiconductor nanomaterials6
CMOS image sensor fixed pattern noise calibration scheme based on digital filtering method6
A comparative study on performance of junctionless Bulk SiGe and Si FinFET6
A self-compensated approach for ramp kickback noise in CMOS image sensor column parallel single slope ADC6
A robust architecture of ring oscillator PUF: Enhancing cryptographic security with configurability6
A 2.44μs row conversion time 12-bit high-speed differential single-slope ADC with TDC applied to CMOS image sensor6
Low voltage high performance super class AB OTA design using SCCM and DTMOS with enhanced slew rate and DC gain6
A 1T2M memristor-based logic circuit and its applications6
A novel control circuit for piezoelectric energy harvesting6
Stability and reliability of LTCC-based 5/12 ​V dual output DC-DC converter with high efficiency and small size6
Investigation of proton irradiated dual field plate AlGaN/GaN HEMTs: TCAD based assessment6
A 1 GS/s 10bit SAR ADC with background calibration in 28 nm CMOS6
A 2.4 GHz sub 1-mW highly linear differential LNA using balun transformer gm-boosting technique6
New pull-in voltage modelling of step structure RF MEMS switch6
Ultra low power current mirror design with enhanced bandwidth6
Optimization design of high-speed data acquisition system based on DMA double cache mechanism6
Measurement method of the IGBT chip temperature fluctuation based on electrothermal model derivation6
Design of a V-band low noise amplifier for passive millimeter wave imaging application6
Enhanced analog/RF performance of hybrid charge plasma based junctionless C-FinFET amplifiers at 10 nm technology node6
Study of multi-domain switching dynamics in negative capacitance FET using SPICE model6
Substrate BOX engineering to mitigate the self-heating induced degradation in nanosheet transistor6
Effect of curie temperature on electrical parameters of NC-FinFET and digital switching application of NC-FinFET6
In-situ characterization up to 100 ​GHz of insulators used in new 3D “System in Package on board” (SiPoB) technologies6
A reconfigurable PUF structure with dual working modes based on entropy separation model6
Negative capacitance based phase-transition FET for low power applications: Device-circuit co-design6
A link adaptation scheme for reliable downlink communications in narrowband IoT6
Behavioral-level modeling of GaN HEMT small-signal intrinsic noise based on DE-SVR algorithm6
A communication-aware and predictive list scheduling algorithm for network-on-chip based heterogeneous muti-processor system-on-chip6
Implementation of TRNG with SHA-3 for hardware security6
Investigation and optimization of electro-thermal performance of Double Gate-All-Around MOSFET6
Electronic transport in doped and dielectric inserted MLGNR interconnects: Crosstalk induced delay and stability analyses at sub-threshold regime6
MESO-ADC: The ADC design using MESO device6
A novel dual-reference sensing scheme for computing in memory within STT-MRAM6
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