IEEE Journal of Solid-State Circuits

Article	Citations
Message From the Incoming Editor-in-Chief	140
IEEE JOURNAL OF SOLID-STATE CIRCUITS	126
Table of Contents	115
Table of Contents	111
IEEE JOURNAL OF SOLID-STATE CIRCUITS	108
Table of Contents	106
A Time-Domain Accuracy-Boosted Temperature Compensated Crystal Oscillator	105
Table of Contents	100
Drift-Compensated Magnetic Biosensors Using Concurrent Dual-Frequency Oscillators	98
A 3-nm FinFET 563-kbit 35.5-Mbit/mm 2 Dual-Rail SRAM With 3.89-pJ/Access High Energy Efficient and 27.5-μW/Mbit One-Cycle Latency Low-Leakage Mode	87
A Nonuniform Sampling Lifetime Estimation Technique for Luminescent Oxygen Measurements for Biomedical Applications	84
A Microscaling Multi-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Device	82
A 14 nm SRAM Using NMOS Header Assist Cell for Improved Write Ability and Reduced Cell Retention Leakage With Minimal Power Overhead	75
An Isolated DC–DC Converter Using a Cross-Coupled Shoot-Through-Free Class-D Oscillator With Low EMI Emissions	73
A 0.13- μ m HV CMOS Fully-Integrated Galvanic Isolator for Gate Drivers With Asynchronous Full-Duplex Communication	72
A 30.2-µ Vrms Horizontal Streak Noise 8.3-Mpixel 60-Frames/s CMOS Image Sensor With Skew-Relaxation ADC and On-Chip Testable Ramp Generator for Surveillance Camera	71
STAR-SRAM: 16-bit Floating-Point SRAM-Based Digital Computing-in-Memory Macro in a 28 nm	70
Dual-Mode Operations of Self-Rectifying Ferroelectric Tunnel Junction Crosspoint Array for High-Density Integration of IoT Devices	69
A 16-kB 65-nm GC-eDRAM Macro With Internal Bias Voltage Generation Providing Over 100-μs Retention Time	67
A PNP-Based Temperature Sensor With Continuous-Time Readout and ±0.1 ∘C (3σ) Inaccuracy From -55 ∘C to 125 ∘C	66
A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta–Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS	66
A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68	63
An 86.71875-GHz RF Transceiver for 57.8125-Gb/s Plastic Waveguide Links With a CDR-Assisted Carrier Synchronization Technique in 28-nm CMOS	62
A 1.1-/0.9-nA Temperature-Independent 213-/565-ppm/°C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI	61
A Compact 10-MHz RC Frequency Reference With a Versatile Temperature Compensation Scheme	61

A Hybrid Voltage-Time Domain Pipelined ADC With Reference-Embedded Time-Domain Residues	61
A 1.19-pJ/b 32-Gb/s Baud-Rate Receiver Employing 2UI Integrated Pattern-Based CDR and DFE Adaptation Without Data-Level Reference	57
Analysis and Comparison of Logic Architectures for Digital Circuits in a-IGZO Thin-Film Transistor Technologies	57
A 60-V High-Side / In-Line Instrumentation Amplifier With 54-V/ μ s CM Transient Tolerance and 115-dB Dynamic Range	56
A CMOS 49–63-GHz Phase-Locked Stepped-Chirp FMCW Radar Transceiver	56
A 14-b BW /Power Scalable Sensor Interface With a Dynamic Bandgap Reference	56
NeuroFlare: An mm3-Scale Wireless Neural Interface Device With Simultaneous Neural Recording and Optical Stimulation	55
A Compact 19.7- to 43.8-GHz Power Amplifier With 20.3-dBm Psat and 35.5% PAE in 28-nm Bulk CMOS	53
A 1.8-V GPIO With Design-Technology-Reliability Co-Optimization in Sub-3-nm GAA-NS Technology	52
A Charge-Domain Fractional-N ADPLL Based on Charge-Steering Sampling	50
A 23-GHz TX/LNA Front-End Module for Inter-Satellite Links With 27.8% Peak Efficiency in the TX Path and 3.1-dB NF in the RX Path	50
A 300-GHz 2-D Scalable 4 × 4 Phased-Array Receiver With Half-Wavelength Element Spacing in 65-nm CMOS	49
A 6.78-MHz Wireless Power and Data Transfer System Achieving Simultaneous 48.6% End-to-End Efficiency and 4.0-Mb/s Forward Data Delivery With Interference-Free Rectifier	49
Building Minimum-Power Digital Circuits With Sub-Femtowatt Dynamic Leakage-Suppression Logic Standard Cells	49
W-band Scalable 2×2 Phased-Array Transmitter and Receiver Chipsets in SiGe BiCMOS for High Data-Rate Communication	49
Xiling: Cryo-CMOS Manipulator Using Dual 18-bit R-2R DACs for Single-Electron Transistor at 60 mK	48
A Programmable Filtering and Frequency Translation by Aliasing IF Receiver With Alias and Harmonic Rejection	47
Picowatt-Power Super-Cutoff Analog Building Blocks and 78-pW Battery-Less Wake-Up Receiver for Light-Harvested Near-Always-On Operation	47
A 119-dBA Dynamic Range, 3.3-mW Audio CTDSM With a Class-B Resistor DAC and Continuous-Time Quantizer	47
RFIC 2023 Call for Papers	46
An Intrinsically Linear Multi-Rate Continuous-Time Zoom ADC Achieving 97.4-dB DR and 105.7-dB SFDR in 50-kHz Signal Bandwidth	46
A Runtime Reconfigurable Array (RTRA) for Multiprogram ML and DSP Acceleration With Hierarchical Partitioning and On-Chip Multilevel Scheduling	46
TechRxiv: Share Your Preprint Research With the World!	45
A Bidirectional USB Power Delivery Voltage-Regulating Cable	44
A Passive Wideband Noise-Canceling Mixer-First Architecture With Shared Antenna Interface for Interferer-Tolerant Wake-Up Receivers and Low-Noise Primary Receivers	44
A Filter-Embedded Pipe-SAR ADC With Progressive Conversion and Floating Charge Transfer Amplifier	44
Table of Contents	44
A Dual-Path Topology for Single-Inductor Dual-Output DC–DC Converters	44
Table of Contents	44
Table of Contents	43
Information For Authors	43
IEEE Journal of Solid-State Circuits Publication Information	43
Erratum to “A 7-bit 1.15-GS/s 2.6-bit/Cycle Asynchronous SAR ADC Using Comparator Decision Skip Technique With Background Offset Calibration”	43
New Associate Editor	42
Guest Editorial Introduction to the Special Section on the 2025 RFIC Symposium	42
Onyx: A 12-nm Programmable Accelerator for Dense and Sparse Applications	42
A 3.47 NEF 175.2-dB FoMs Direct Digitization Front-End Featuring Delta Amplification Noise-Shaping SAR ADC for Biosignal Acquisition	42
Guest Editorial 2022 Radio Frequency Integrated Circuits Symposium	42
New Associate Editor	42
A Multiply-and-Accumulate SAR-ADC-Based Hybrid Slepian Beamformer	41
A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-Voltage Multivoltage/ Frequency-Domain Network-on-Chip	41
Concurrent Body-Coupled Powering and Communication ICs With a Single Electrode	41
On-Chip Condition-Adaptive Δ f 3 EMI Control for Switching Power ICs	40
A 92%-Efficiency Inductor-Charging Switched-Capacitor Stimulation System With Level-Adaptive Duty Modulation and Offset Charge Balancing	40
A +43.3-dBm IIP 3 , Low-Power Transimpedance Amplifier Employing a Switched-Capacitor Amplifier-Based Transition-Band Pole-Zero Doublets Compensation	40
A Fully Integrated 4:1 DC–DC Converter With Series Transmission and Parallel Reception Through Electromagnetically Coupled Class-D LC Oscillators	40
A Cycle-Slip Compensated FMCW Digital PLL With Background Back-Tracking DPD	40
A 2.16-pJ/b 112-Gb/s PAM-4 Transceiver With Time-Interleaved 2-b/3-b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28-nm CMOS	40
A LiDAR–PNN Pipelined Processor With Cylindrical Bin Partitioning and Halo Indexing for 3-D Perception in Outdoor Autonomous Driving Applications	40
A Continuous-Time Zoom ADC With Coarse Noise-Shaping ADC and Interstage Low-Pass Filter	40

TensorCIM: Digital Computing-in-Memory Tensor Processor With Multichip-Module-Based Architecture for Beyond-NN Acceleration	40
An Isolated DC-DC Converter With Full-Duplex Communication Using a Single Pair of Transformers	39
A 1920 × 1080 Array 2-D/3-D Image Sensor With 3-μ s Row-Time Single-Slope ADC and 100-MHz Demodulated PPD Locked-In Pixel	39
MetaVRain: A Mobile Neural 3-D Rendering Processor With Bundle-Frame-Familiarity-Based NeRF Acceleration and Hybrid DNN Computing	39
Design and Analysis of Ka-Band Variable-Gain Phase Shifter With Impedance-Invariant Vector Modulation	38
A 4×112 Gb/s PAM-4 Silicon-Photonic Transmitter and Receiver Chipsets for Linear-Drive Co-Packaged Optics	38
A 128-Gb/s D-Band Receiver With Integrated PLL and ADC Achieving 1.95-pJ/b Efficiency in 22-nm FinFET	38
HUNBN, a 16-nm Digital In-Memory-Compute SoC for Edge CNN Application Achieving 24 TOPs/W (4b) at System Level	38
A Complementary Positive Feedback-Assisted Current Mirror-Based Level Shifter for Energy-Efficient Level Conversion for Wide Voltage Ranges	38
A 1.6-GHz DPLL Using Feedforward Phase-Error Cancellation	38
A 116-Gb/s PAM4 0.9-pJ/b Transmitter With Eight-Tap FFE in 5-nm FinFET	38
A 22-nm Delta-Sigma Computing-In-Memory SRAM Macro With Near-Zero-Mean Outputs and LSB-First ADCs for Edge AI Processing	38
A 77-GHz Hybrid TDM-MIMO Phased-Array Radar With 186-m Detection Range and 3-cm Range Resolution	38
Analysis and Design of a 10.4-ENOB 0.92–5.38-μW Event-Driven Level-Crossing ADC With Adaptive Clocking for Time-Sparse Edge Applications	38
A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application	38
A 4.96-μW 15-bit Self-Timed Dynamic-Amplifier-Based Incremental Zoom ADC	37
A mm-Wave Frequency Modulated Transmitter Array for Superior Resolution in Angular Localization Supporting Low-Latency Joint Communication and Sensing	37
A Benchmark of Cryo-CMOS Embedded SRAM/DRAMs in 40-nm CMOS	37
A Millimeter-Wave Three-Way Doherty Power Amplifier for 5G NR OFDM	37
A Single Li-Ion Battery Powered Buck Converter With >90% Efficiency Over 10-μA to 500-mA Loading Range by Utilizing Compensator-Based Built-In Mode Tracking Technology	36
A 12-bit 1-GS/s Current-Steering DAC With Paired Current Source Switching Background Mismatch Calibration	36
A Four-Channel Bidirectional D-Band Phased-Array Transceiver for 200 Gb/s 6G Wireless Communications in a 130-nm BiCMOS Technology	36
Dual-Mode Inverter-Based Write Termination Scheme for Energy- and Area-Efficient Write Operation in 28-nm 1T1MTJ STT-MRAM	36
Design and Analysis of a 13.7--41 GHz Ultra-Wideband Frequency Doubler With Cross-Coupled Push-Push Structure	36
A K / Ka -Band Transmit/Receive Front-End With Triple-Coupled Transformer Technique in 65-nm Bulk CMOS	36
A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference	35
A 30-μW 94.7-dB SNDR Noise-Shaping Current-Mode Direct-to-Digital Converter Using Triple-Slope Quantizer for PPG/NIRS Readout	35
Table of Contents	35
A Sub-Threshold Oscillator-Based High-Accuracy Temperature Sensor With Tolerance to Supply Fluctuation and Device Aging	35
Introducing IEEE Collabratec	35
New Associate Editor	35
A Scalable 1024-Channel VCO-Based CTDSM MEA Readout IC Achieving High Yield and Reliability Through Slot-Partitioned Channel Redundancy	34
A Reflection-Mode N-Path Filter Tunable From 6 to 31 GHz	34
An Efficient Inductive Rectifier Based Piezo-Energy Harvesting Using Recursive Pre-Charge and Accumulation Operation	34
A 6.5-pJ/Step Reconfigurable Readout IC With Duty-Cycled Resistor and Switched Capacitor for High Linearity RC-to-Digital Converter	34
A Display Source-Driver IC Featuring Multistage-Cascaded 10-Bit DAC and True-DC-Interpolative Super-OTA Buffer	34
An EMG Interface Comprising a Flexible a-IGZO Active Electrode Matrix and a 65-nm CMOS IC	34
A 65-nm RRAM Compute-in-Memory Macro for Genome Processing	34
A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking	34
A 0.8-V BJT-Based Temperature Sensor With an Inaccuracy of ±0.4 °C (3σ) From −40 °C to 125 °C in 22-nm CMOS	33
A 1.01-V 8.5-Gb/s/pin 16-Gb LPDDR5x SDRAM With Advanced I/O Circuitry for High-Speed and Low-Power Applications	33
A 128-Gb/s PAM-4 Transmitter With Edge-Boosting Pulse Generator and Pre-Emphasis Asymmetric Fractional-Spaced FFE in 28-nm CMOS	33
A 2.5–20 kS/s In-Pixel Direct Digitization ECoG Front End With Submillisecond Stimulation Artifact Recovery	33
New Associate Editor	33
A 2.4-GHz Full-Duplex Transceiver With Broadband, Linearity-Enhanced, and Long-Delay Spread Self-Interference Cancellation	33
A Fully Bit-Flexible Computation in Memory Macro Using Multi-Functional Computing Bit Cell and Embedded Input Sparsity Sensing	33
TechRxiv: Share Your Preprint Research With the World!	32
A Fast Back-to-Lock DPLL-Based 192–210-GHz Chirp Generator With +5.9-dBm Peak Output Power for Sub-THz Imaging and Sensing	32
A 4.6-GHz 54.5-fs rms PLL-XO Co-Design Featuring a Pulse-Injection XO Driver	32
Denim: Heterogeneous Compute-in-Memory Accelerator Exploiting Denoising--Similarity for Diffusion Models	32
A 6-GHz Continuous-Time Bandpass ΔΣ ADC With Background Filter Calibration and −100 dBc IM3 for a Mixer-Less DAB Band III Receiver	32
IEEE Journal of Solid-State Circuits Publication Information	32
An 11.95-ENOB 560-MS/s Amplifier-Switching Subranging Analog-to-Digital Converter With Multi-Threshold Comparators	31
A 15-Gb/s PAM-3 Transceiver With Hybrid Equalization and Time-Domain Decoder for High-Bandwidth-Memory Interfaces	31
A 56-GHz Fractional-N PLL With 110-fs Jitter	31
A Low-Voltage-CMOS AC–DC Converter With Series-Capacitor Pre-Regulation and Fine-Grained Capacitance Reallocation for Mains-Powered IoT	31
A 1.5–23.5-GHz 150.5-Gb/s Distributed PA Using High-Power-Density Cells and Broadband Power Combining Techniques in 40-nm CMOS	31
A 96.1% Efficiency Single-Inductor Multiple-Output (SIMO) Buck Converter With 2.1-A/ns Transient Speed and 2.2-A Maximum Current Capacity	31
Introducing IEEE Collabratec	31
A Miniaturized 3-D-MRI Scanner Featuring an HV-SOI ASIC and Achieving a 10 × 8 × 8 mm3 Field of View	31
A High-Resolution Solid-State LiDAR Sensor With Reconfigurable Histogramming Time-to-Digital Converter and Filter for Depth Refinement	31
A 120.9-dB DR Digital-Input Capacitively Coupled Chopper Class-D Audio Amplifier	30
A Capacitor-Free Hybrid-Process Low Dropout Regulator With Ultrahigh-Gain Amplifier and Super Source Follower for 0.297 mV/A Load Regulation and 0.024 mV/V Line Regulation	30
A Portable CMOS-Based Spin Resonance System for High-Resolution Spectroscopy and Imaging	30
A 37–43.5-GHz Phase and Amplitude Detection Circuit With 0.049° and 0.036-dB Accuracy for 5G Phased-Array Calibration Using Transformer-Based Injection-Enhanced ILFD	30
Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology	30
Space-Mate: A 303.5-mW Real-Time Sparse Mixture-of-Experts-Based NeRF-SLAM Processor for Mobile Spatial Computing	30
A Ten-Level Series-Capacitor 24-to-1-V DC–DC Converter With Fast In Situ Efficiency Tracking, Power-FET Code Roaming, and Switch Node Power Rail	30
An Energy-Efficient POSIT Compute-in-Memory Macro for High-Accuracy AI Applications	30
An 18.3- μ W 108.3-dB DR Discrete-Time Delta-Sigma Modulator Using a Loop Filter Auto-Shift Technique	29
Design Considerations for a Low-Power Fully Integrated MMIC Parametric Upconverter in SiGe BiCMOS	29
A 0.186-pJ per Bit Latch-Based True Random Number Generator Featuring Mismatch Compensation and Random Noise Enhancement	29
A 96 × 64 SPAD LiDAR Sensor With 6× Imaging FoM Promotion by AI-Assisted Fusion of 2-D and Edge-Guided Sparse 3-D Detection	29
An Intrinsically PVT Robust 10-bit 2.6-GS/s Dynamic Pipelined ADC With Dual-Path Time-Assisted Residue Generation Scheme	29
A 29.12-TOPS/W Vector Systolic Accelerator With NAS-Optimized DNNs in 28-nm CMOS	29
A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features	29
An Energy-Efficient and High-Accuracy Dual-Mode ECG AI Processor via Deep-Fold and Zero-Free Fine-Grained Quantization	29
A 65-nm Energy-Efficient Interframe Data Reuse Neural Network Accelerator for Video Applications	29
A 7-Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS	29
An Edge 3-D Gaussian Splatting Processor Based on Shape-Aware Computation Architecture and Spatio-Temporal Gaussian Cache	28

Guest Editorial Introduction to the Special Section on the 2025 IEEE International Solid-State Circuits Conference (ISSCC)	28
A Compact Millimeter-Wave Reconfigurable Dual-Band LNA With Image-Rejection in 28-nm Bulk CMOS for 5G Applications	28
A 12.8-GS/s Time-Interleaved Sub-Sampling ADC Front End With 38-GHz Input Bandwidth and >39-dB SNDR for 1–32 GHz in 22-nm FDSOI	28
Guest Editorial IEEE 2022 BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium	28
A 4.13-GHz UHS Pseudo Two-Port SRAM With BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4-nm FinFET Technology	28
A −91 dB THD+N, Class-D Piezoelectric Speaker Driver Using Dual Voltage/Current Feedback for Resistor-Less LC Resonance Damping	28
New Associate Editor	28
A 4.9–7.1-GHz High-Efficiency Post-Matching GaN Front-End Module for Wi-Fi 7 Application	27
A 0.00175 mm 2 and 9.62 μ W per Channel Direct-Digitization Front End With EDO Compensation for Neural	27
Cryo-CMOS Dual-Qubit Homodyne Reflectometer Array With Degenerate Parametric Amplification	27
RF-to-Millimeter-Wave Receivers Employing Frequency-Translated Feedback	27
A Low-Complexity FM-UWB Transmitter With Digital Reuse and Analog Stacking	27
Energy Efficient Monolithically Integrated 256 Gb/s Optical Transmitter With Autonomous Wavelength Stabilization in 45 nm CMOS SOI	27
A Sub-μW Energy Harvester Architecture With Reduced Top/Bottom Plate Switching Loss Achieving 80.66% Peak Efficiency in 180-nm CMOS	27
A Fully Integrated 490-GHz CMOS Receiver Adopting Dual-Locking Receiver-Based FLL	27
A Recursive N-Path Switched-Capacitor Rectifier for Piezoelectric Energy Harvesting	27
A 28-nm RRAM/SRAM Collaborative CIM Accelerator Supporting RRAM-Endurance-Latency Awareness for Edge Fine-Tuning	27
A 103 fJ/b/dB, 10–26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement	26
A Constant Bandwidth Oversampling PLL Enabled by a Constant-Gain Oversampler Composed of Double-Edge and Sampling Single-Edge Capacitive Charging and Discharging Phase Interpolators	26
A High-Efficiency Wireless Power Transfer System Under Wide Coupling Coefficient Range Based on Phase Shift and Near-Zero-Time Detection	26
A Single-Trim Frequency Reference System With 0.7 ppm/°C From −63 °C to 165 °C Consuming 210 μW at 70 MHz	26
Hybrid SRAM/ROM Compute-in-Memory Architecture for High Task-Level Energy Efficiency in Transformer Models With 8928-kb/mm² Density in 28nm CMOS	26
A Single-Ended NRZ Receiver With Gain-Enhanced Active-Inductive CTLE and Reference-Selection DFE for Memory Interfaces	26
A Scalable BEV Perception Processor for Image/Point Cloud Fusion Applications Using CAM-Based Universal Mapping Unit	26
48-to-1 V Direct Conversion Using High-Voltage Storage and Low-Voltage Boost Bootstrap Technique and Early Comparison On-Time Generator for Precise Nanosecond Pulses and 90.3% Efficiency in Automotive	26
Analysis and Design of Broadband Terahertz Push–Push Frequency Doublers With Second Harmonic Source Tuning	26
EMBER: Efficient Multiple-Bits-Per-Cell Embedded RRAM Macro for High-Density Digital Storage	26
A High-Density Low-Leakage and Low-Power Fully Voltage-Stacked SRAM for IoT Application	26
A 3.1- μ W Analog-Assisted Zoom Histogramming TDC in 35- μ m Pixel Pitch for Flash LiDAR Sensor	26
A Low-Phase-Noise Wide-Tuning-Range Mode-Switching Oscillator Using Multi-Magnetic-Coupling and Active-Source-Degenerating Techniques	25
A Fully-Reflective Wi-Fi-Compatible Backscatter Communication System With Retro-Reflective MIMO Gain for Improved Range	25
Ultra-Low-Power Dynamic-Bias Comparators With Self-Clocked Latch in 65-nm CMOS	25
A Rail-to-Rail Input NS-Pipelined-SAR ADC With Self-Boosted Input Impedance and Reused Residue Amplifier for Biosignal Acquisition	25
A Dual-Band Simultaneous RF Energy Harvesting System With Globally Optimized 3-D MPPT and Efficiency Enhancement	25
A 2 MHz Bandwidth TMR-Based Contactless Current Sensor With Ping-Pong Auto-Zeroing and SAR-Assisted Offset Calibration	25
A 124–161 GHz Active Vector Modulator for 6G Applications Utilizing a Dual Current Steering With Low RMS Phase and Gain Errors	25
An NMOS LDO With TM-MOS and Dynamic Clamp Technique Handling Up To Sub-10-μs Short-Period Load Transient	25
Design and Analysis of a 22.6-to-73.9 GHz Low-Noise Amplifier for 5G NR FR2 and NR-U Multiband/Multistandard Communications	25
IEEE JOURNAL OF SOLID-STATE CIRCUITS	25
A Single-Input RF Energy-Harvesting Interface With Compensated-CEPE Control and 3-D Hill-Climbing MPPT Achieving −28.5-dBm Sensitivity	25
A Multi-Mode 8k-MAC HW-Utilization-Aware Neural Processing Unit With a Unified Multi-Precision Datapath in 4-nm Flagship Mobile SoC	25
IEEE Journal of Solid-State Circuits Information for Authors	25
PAICORE: A 1.9-Million-Neuron 5.181-TSOPS/W Digital Neuromorphic Processor With Unified SNN-ANN and On-Chip Learning Paradigm	25
Compute SNDR-Boosted 22-nm MRAM-Based In-Memory Computing Macro Using Statistical Error Compensation	25
TechRxiv: Share Your Preprint Research With the World!	25
Efficient Wideband mmW Transceiver Front End for 5G Base Stations in 22-nm FD-SOI CMOS	25
New Associate Editor	24
Table of Contents	24
IEEE Journal of Solid-State Circuits Publication Information	24
Guest Editorial Introduction to the Special Section on the 2023 RFIC Symposium	24
Table of Contents	24
An Indirect ToF Sensor With In-Pixel Adaptive ΔΣ -Scheme for Background Light Rejection and Floating Diffusion Mismatch Cancellation	24
Table of Contents	24
TechRxiv: Share Your Preprint Research With the World!	24
Introducing IEEE Collabratec	24
New Associate Editor	24
NeRF-Navi: An Energy-Efficient NeRF 3-D Path Planning Processor With Reconfigurable Approximate/Accurate Bit Offloading Core	24
A Ka-Band Eight-Stream Phased-Array MIMO Receiver With Time-Hopping Blocker Rejection for 6G	24
Wideband High-Gain Amplifiers in 45-nm CMOS SOI Operating at 0.56f max: An Analytical Approach on Reversed Feedback Amplifiers	24
Table of Contents	24
IEEE Journal of Solid-State Circuits Information for Authors	24
New Associate Editor	24
Table of Contents	24
TechRxiv: Share Your Preprint Research With the World!	24
Corrections to “Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation”	24
A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS	23
ED-MPIM: An Energy-Efficient Event-Driven Smart Vision SoC With High-Linearity and Reconfigurable MRAM PIM	23
Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration	23
A 95.3% Efficiency APT/AET/SPT Multimode Multiband CMOS/GaN Envelope Tracking for 6G-Oriented Systems	23
A 2.2-ps Time-of-Flight Resolution Frequency-Domain fNIRS Readout IC With a Dynamic Architecture and Cross-Coupling-Free Intensity and Phase-to-Digital Converter	23
A 0.033-mm2 21.5-aF to 114.9-aF Resolution Continuous-Time Δ Σ Capacitance-to-Digital Converter Achieving Parasitic Capacitance Immunity Up to 480 pF	23
An Efficient Power Management Unit With Continuous MPPT and Energy Recycling for Wireless Millimetric Biomedical Implants	23
A 0.5-V 6.14- μW Trimming-Free Single-XO Dual-Output Frequency Reference With [5.1-nJ, 120- μs] XO Start-Up and [8.1-nJ, 200- μs] Successive-Approximation-Based RTC Calibration	23
QVGA CMOS LiDAR Sensor With nMOS-Only SPAD Analog Front-End and Area-Efficient Priority Histogramming TDC	23
A 20-Gb/s/Line Single-Ended Transceiver With Coupling-Balanced Crosstalk-Cancellation for Shield-Less 1.5- μ m-Pitch Interconnect	23
A 0.29 pJ/b 5.27 Tb/s/mm UCIe Advanced Package Link With 2.5-D CoWoS Interposer and a 0.52 pJ/b 0.448 Tb/s/mm UCIe Standard Package Link With Organic Substrate in 3 nm FinFET	23
An Area-Efficient 10-Bit Source-Driver IC With LSB-Stacked LV-to-HV-Amplify DAC for Mobile OLED Displays	23
A Four-Channel BiCMOS Transmitter for a Quantum Magnetometer Based on Nitrogen-Vacancy Centers in Diamond	23
Planar 200-GHz Transceiver Modules	22
A Six-Phase Harmonic-Rejection Digital Transmitter	22
A 48–56 GHz >1 dBm-HB1dB Sub-Sampling Eight-Path-Filter Receiver With Fully-Integrated LO Generation and On-Chip Antenna	22
CMOS SPAD Line Sensor With Fine-Tunable Parallel Connected Time-to-Digital Converters for Raman Spectroscopy	22
A 23-μW Keyword Spotting IC With Ring-Oscillator-Based Time-Domain Feature Extraction	22
Full-Duplex Receiver With Wideband, High-Power RF Self-Interference Cancellation Based on Capacitor Stacking in Switched-Capacitor Delay Lines	22
A 2.46-mm2 Miniaturized Brain-Machine Interface (MiBMI) Enabling 31-Class Brain-to-Text Decoding	22
Digital In-Memory Compute for Machine Learning Applications With Input and Model Security	22
A 2-mW 70.7-dB SNDR 200-MS/s Pipelined-SAR ADC Using Continuous-Time SAR-Assisted Detect-and-Skip and Open-Then-Close Correlated Level Shifting	22
A Harmonic-Mixing PLL Architecture for Millimeter-Wave Application	22
A 71.5-dB SNDR 475-MS/s Ringamp-Based Pipelined SAR ADC With On-Chip Bit-Weight Calibration	22
An Ultralow-Power Triaxial MEMS Accelerometer With High-Voltage Biasing and Electrostatic Mismatch Compensation	22
A 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks	22
A Power-Efficient CMOS Multi-Band Phased-Array Receiver Covering 24–71-GHz Utilizing Harmonic-Selection Technique With 36-dB Inter-Band Blocker Tolerance for 5G NR	22
A Digital-Sampling PLL With a Second-Order Noise Shaping SAR ADC Phase Detector	22
A 200-GHz Power Amplifier With 18.7-dBm P sat in 45-nm CMOS SOI: A Model-Based Large-Signal Approach on Cascaded Series-Connected Power Amplification	22
A Battery-Free Neural-Recording Chip Achieving 5.5 cm Fully-Implanted Depth by Galvanically-Switching Passive Body Channel Communication	22