IEEE Journal of Solid-State Circuits

(The median citation count of IEEE Journal of Solid-State Circuits is 3. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 500 papers]. The publications cover those that have been published in the past four years, i.e., from 2019-11-01 to 2023-11-01.)
XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks168
An 80-Gb/s 300-GHz-Band Single-Chip CMOS Transceiver133
C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism121
A 39-GHz 64-Element Phased-Array Transceiver With Built-In Phase and Amplitude Calibrations for Large-Array 5G NR in 65-nm CMOS107
A Reconfigurable 3-D-Stacked SPAD Imager With In-Pixel Histogramming for Flash LIDAR or High-Speed Time-of-Flight Imaging98
A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors91
An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier90
A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing88
A Single-Chip Optical Phased Array in a Wafer-Scale Silicon Photonics/CMOS 3D-Integration Platform86
Design and Characterization of a 28-nm Bulk-CMOS Cryogenic Quantum Controller Dissipating Less Than 2 mW at 3 K84
A Programmable Heterogeneous Microprocessor Based on Bit-Scalable In-Memory Computing78
A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR76
300-GHz-Band 120-Gb/s Wireless Front-End Based on InP-HEMT PAs and Mixers76
A Sub-mm3 Ultrasonic Free-Floating Implant for Multi-Mote Neural Recording73
A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS63
Tianjic: A Unified and Scalable Chip Bridging Spike-Based and Continuous Neural Computation61
A Scalable Cryo-CMOS Controller for the Wideband Frequency-Multiplexed Control of Spin Qubits and Transmons59
Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors56
A 12-b 18-GS/s RF Sampling ADC With an Integrated Wideband Track-and-Hold Amplifier and Background Calibration53
Vocell: A 65-nm Speech-Triggered Wake-Up SoC for 10-$\mu$ W Keyword Spotting and Speaker Verification52
Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks51
A Modular, Direct Time-of-Flight Depth Sensor in 45/65-nm 3-D-Stacked CMOS Technology51
A CMOS 76–81-GHz 2-TX 3-RX FMCW Radar Transceiver Based on Mixed-Mode PLL Chirp Generator50
A 0.32–128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm47
A 24.5–43.5-GHz Ultra-Compact CMOS Receiver Front End With Calibration-Free Instantaneous Full-Band Image Rejection for Multiband 5G Massive MIMO46
A 20-GHz 1.9-mW LNA Using g m-Boost and Current-Reuse Techniques in 65-nm CMOS for Satellite Communications46
A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects45
High-Value Tunable Pseudo-Resistors Design45
A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier44
Design and Analysis of Enhanced Mixer-First Receivers Achieving 40-dB/decade RF Selectivity43
An mm-Wave Synthesizer With Robust Locking Reference-Sampling PLL and Wide-Range Injection-Locked VCO43
A 3-D-Integrated Silicon Photonic Microring-Based 112-Gb/s PAM-4 Transmitter With Nonlinear Equalization and Thermal Control42
A Coupler-Based Differential mm-Wave Doherty Power Amplifier With Impedance Inverting and Scaling Baluns42
MANA: A Monolithic Adiabatic iNtegration Architecture Microprocessor Using 1.4-zJ/op Unshunted Superconductor Josephson Junction Devices42
A 192-pW Voltage Reference Generating Bandgap–$V_{\text{th}}$ With Process and Temperature Dependence Compensation41
STICKER: An Energy-Efficient Multi-Sparsity Compatible Accelerator for Convolutional Neural Networks in 65-nm CMOS41
A 220-to-320-GHz FMCW Radar in 65-nm CMOS Using a Frequency-Comb Architecture41
A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET41
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management40
A Super-Resolution Mixed-Signal Doherty Power Amplifier for Simultaneous Linearity and Efficiency Enhancement40
A 1.7-dB Minimum NF, 22–32-GHz Low-Noise Feedback Amplifier With Multistage Noise Matching in 22-nm FD-SOI CMOS40
A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors40
A 10-mA LDO With 16-nA IQ and Operating From 800-mV Supply39
A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips39
A 0.46-THz 25-Element Scalable and Wideband Radiator Array With Optimized Lens Integration in 65-nm CMOS38
A 373-F² 0.21%-Native-BER EE SRAM Physically Unclonable Function With 2-D Power-Gated Bit Cells and VSS Bias-Based Dark-Bit Detection38
A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration37
STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin–Spin Interactions37
A 13.9-nA ECG Amplifier Achieving 0.86/0.99 NEF/PEF Using AC-Coupled OTA-Stacking37
CAP-RAM: A Charge-Domain In-Memory Computing 6T-SRAM for Accurate and Precision-Programmable CNN Inference36
Design of a 50-Gb/s Hybrid Integrated Si-Photonic Optical Link in 16-nm FinFET36
Analysis and Design of a 260-MHz RF Bandwidth +22-dBm OOB-IIP3 Mixer-First Receiver With Third-Order Current-Mode Filtering TIA36
Track-and-Zoom Neural Analog-to-Digital Converter With Blind Stimulation Artifact Rejection36
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking36
112-Gb/s PAM4 ADC-Based SERDES Receiver With Resonant AFE for Long-Reach Channels36
A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC With Dynamic Gm-R-Based Amplifier36
A 47.14-$\mu\text{W}$ 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications36
A 6.5-μW 10-kHz BW 80.4-dB SNDR Gm-C-Based CT ∆∑ Modulator With a Feedback-Assisted Gm Linearization for Artifact-Tolerant Neural Recording36
A 510-nW Wake-Up Keyword-Spotting Chip Using Serial-FFT-Based MFCC and Binarized Depthwise Separable CNN in 28-nm CMOS35
A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS35
A 12.08-TOPS/W All-Digital Time-Domain CNN Engine Using Bi-Directional Memory Delay Lines for Energy Efficient Edge Computing35
A 1.9-mW SVM Processor With On-Chip Active Learning for Epileptic Seizure Control35
A Single-Chip Bidirectional Neural Interface With High-Voltage Stimulation and Adaptive Artifact Cancellation in Standard CMOS35
A 0.02–4.5-GHz LN(T)A in 28-nm CMOS for 5G Exploiting Noise Reduction and Current Reuse35
A 32 × 128 SPAD-257 TDC Receiver IC for Pulsed TOF Solid-State 3-D Imaging34
A VGA Indirect Time-of-Flight CMOS Image Sensor With 4-Tap 7-$\mu$ m Global-Shutter Pixel and Fixed-Pattern Phase Noise Self-Compensation34
A DC-to-108-GHz CMOS SOI Distributed Power Amplifier and Modulator Driver Leveraging Multi-Drive Complementary Stacked Cells33
A 1.16-V 5.8-to-13.5-ppm/°C Curvature-Compensated CMOS Bandgap Reference Circuit With a Shared Offset-Cancellation Method for Internal Amplifiers33
A CMOS Two-Element 170-GHz Fundamental-Frequency Transmitter With Direct RF-8PSK Modulation33
A Process and Temperature Insensitive CMOS Linear TIA for 100 Gb/s/$\lambda$ PAM-4 Optical Links33
A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH With DAC Non-Linearity Tolerance33
Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode33
Evolver: A Deep Learning Processor With On-Device Quantization–Voltage–Frequency Tuning33
A Reconfigurable Hybrid Series/Parallel Doherty Power Amplifier With Antenna VSWR Resilient Performance for MIMO Arrays33
Analysis and Design of High-Order QAM Direct-Modulation Transmitter for High-Speed Point-to-Point mm-Wave Wireless Links33
An 8.93 TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity for On-Device Speech Recognition33
A Probabilistic Compute Fabric Based on Coupled Ring Oscillators for Solving Combinatorial Optimization Problems32
A 0.65-V 12-16-GHz Sub-Sampling PLL With 56.4-fsrms Integrated Jitter and -256.4-dB FoM32
A 243-mW 1.25–56-Gb/s Continuous Range PAM-4 42.5-dB IL ADC/DAC-Based Transceiver in 7-nm FinFET32
A CMOS Dual-Polarized Phased-Array Beamformer Utilizing Cross-Polarization Leakage Cancellation for 5G MIMO Systems32
A Sub-6-GHz 5G New Radio RF Transceiver Supporting EN-DC With 3.15-Gb/s DL and 1.27-Gb/s UL in 14-nm FinFET CMOS31
11-bit Column-Parallel Single-Slope ADC With First-Step Half-Reference Ramping Scheme for High-Speed CMOS Image Sensors31
A Bipolar-Input Thermoelectric Energy-Harvesting Interface With Boost/Flyback Hybrid Converter and On-Chip Cold Starter31
A Self-Tuning IoT Processor Using Leakage-Ratio Measurement for Energy-Optimal Operation31
A Multi-Loop Slew-Rate-Enhanced NMOS LDO Handling 1-A-Load-Current Step With Fast Transient for 5G Applications31
An Acoustic Signal Processing Chip With 142-nW Voice Activity Detection Using Mixer-Based Sequential Frequency Scanning and Neural Network Classification31
HERMES-Core—A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs31
A Self-Regulated and Reconfigurable CMOS Physically Unclonable Function Featuring Zero-Overhead Stabilization30
A 0.025-mm2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-$\Delta\Sigma$ M Structure30
Direct TOF Scanning LiDAR Sensor With Two-Step Multievent Histogramming TDC and Embedded Interference Filter30
A Continuous-Time Zoom ADC for Low-Power Audio Applications30
A Fully Passive RF Front End With 13-dB Gain Exploiting Implicit Capacitive Stacking in a Bottom-Plate N-Path Filter/Mixer30
A 3.5-mV Input Single-Inductor Self-Starting Boost Converter With Loss-Aware MPPT for Efficient Autonomous Body-Heat Energy Harvesting30
A 28-nm-CMOS Based 145-GHz FMCW Radar: System, Circuits, and Characterization30
An Energy-Efficient Deep Convolutional Neural Network Training Accelerator for In Situ Personalization on Smart Devices30
A 128 × 128 SPAD Motion-Triggered Time-of-Flight Image Sensor With In-Pixel Histogram and Column-Parallel Vision Processor30
Sub-nW Wake-Up Receivers With Gate-Biased Self-Mixers and Time-Encoded Signal Processing29
A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing29
Algebraic Series-Parallel-Based Switched-Capacitor DC–DC Boost Converter With Wide Input Voltage Range and Enhanced Power Density29
Direct 48-/1-V GaN-Based DC–DC Power Converter With Double Step-Down Architecture and Master–Slave AO2T Control29
A 2-in-1 Temperature and Humidity Sensor With a Single FLL Wheatstone-Bridge Front-End29
A 77-GHz 8RX3TX Transceiver for 250-m Long-Range Automotive Radar in 40-nm CMOS Technology29
A 0.6-V 13-bit 20-MS/s Two-Step TDC-Assisted SAR ADC With PVT Tracking and Speed-Enhanced Techniques29
A Smart Contact Lens Controller IC Supporting Dual-Mode Telemetry With Wireless-Powered Backscattering LSK and EM-Radiated RF Transmission Using a Single-Loop Antenna29
An 802.11ba-Based Wake-Up Radio Receiver With Wi-Fi Transceiver Integration28
A 640 $\times$ 640 Fully Dynamic CMOS Image Sensor for Always-On Operation28
HNPU: An Adaptive DNN Training Processor Utilizing Stochastic Dynamic Fixed-Point and Active Bit-Precision Searching28
Monostatic and Bistatic G-Band BiCMOS Radar Transceivers With On-Chip Antennas and Tunable TX-to-RX Leakage Cancellation28
A Highly Reliable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source28
A Beyond-1-Tb/s Coherent Optical Transmitter Front-End Based on 110-GHz-Bandwidth 2:1 Analog Multiplexer in 250-nm InP DHBT27
A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference27
A Cryogenic Broadband Sub-1-dB NF CMOS Low Noise Amplifier for Quantum Applications27
Enhanced Power and Electromagnetic SCA Resistance of Encryption Engines via a Security-Aware Integrated All-Digital LDO27
A Batteryless Motion-Adaptive Heartbeat Detection System-on-Chip Powered by Human Body Heat27
A 65-nm Neuromorphic Image Classification Processor With Energy-Efficient Training Through Direct Spike-Only Feedback27
A Broadband Switched-Transformer Digital Power Amplifier for Deep Back-Off Efficiency Enhancement27
A Bio-Impedance Readout IC With Digital-Assisted Baseline Cancellation for Two-Electrode Measurement27
A Variation-Adaptive Integrated Computational Digital LDO in 22-nm CMOS With Fast Transient Response26
A 1.6-to-3.0-GHz Fractional-${N}$ MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power26
Power-Efficient Design Techniques for mm-Wave Hybrid/Digital FDD/Full-Duplex MIMO Transceivers26
A 0.5-V Hybrid SRAM Physically Unclonable Function Using Hot Carrier Injection Burn-In for Stability Reinforcement26
A 0.5-V Real-Time Computational CMOS Image Sensor With Programmable Kernel for Feature Extraction26
ULPAC: A Miniaturized Ultralow-Power Atomic Clock26
A 10-mW 16-b 15-MS/s Two-Step SAR ADC With 95-dB DR Using Dual-Deadzone Ring Amplifier26
A Broadband Linear Ultra-Compact mm-Wave Power Amplifier With Distributed-Balun Output Network: Analysis and Design26
Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports26
A 2 $\times$ 30k-Spin Multi-Chip Scalable CMOS Annealing Processor Based on a Processing-in-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems25
An 8-Bit 10-GS/s 16× Interpolation-Based Time-Domain ADC With <1.5-ps Uncalibrated Quantization Steps25
An Ultra-Low-Noise Swing-Boosted Differential Relaxation Oscillator in 0.18-μm CMOS25
An Efficient Piezoelectric Energy Harvesting Interface Circuit Using a Sense-and-Set Rectifier25
A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO25
An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators25
SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference24
A 5-GS/s 7.2-ENOB Time-Interleaved VCO-Based ADC Achieving 30.5 fJ/cs24
A Cascaded Noise-Shaping SAR Architecture for Robust Order Extension24
A 22.3-nW, 4.55 cm2 Temperature-Robust Wake-Up Receiver Achieving a Sensitivity of −69.5 dBm at 9 GHz24
A 13-bit 0.005-mm2 40-MS/s SAR ADC With kT/C Noise Cancellation24
A High-Voltage Dual-Input Buck Converter Achieving 52.9% Maximum End-to-End Efficiency for Triboelectric Energy-Harvesting Applications24
A Dual-Polarization Silicon-Photonic Coherent Transmitter Supporting 552 Gb/s/wavelength24
A 30-GHz CMOS SOI Outphasing Power Amplifier With Current Mode Combining for High Backoff Efficiency and Constant Envelope Operation24
A High-Power Broadband Multi-Primary DAT-Based Doherty Power Amplifier for mm-Wave 5G Applications24
A 1770-$\mu$ m2 Leakage-Based Digital Temperature Sensor With Supply Sensitivity Suppression in 55-nm CMOS24
High-Scalability CMOS Quantum Magnetometer With Spin-State Excitation and Detection of Diamond Color Centers24
Hybrid Dickson Switched-Capacitor Converter With Wide Conversion Ratio in 65-nm CMOS24
A 1.02-pJ/b 20.83-Gb/s/Wire USR Transceiver Using CNRZ-5 in 16-nm FinFET23
A Flying-Inductor Hybrid DC–DC Converter for 1-Cell and 2-Cell Smart-Cable Battery Chargers23
A Physical Unclonable Function With Bit Error Rate < 2.3 $\times$ 10−8 Based on Contact Formation Probability Without Error Correction Code23
A Fully Integrated 0.27-THz Injection-Locked Frequency Synthesizer With Frequency-Tracking Loop in 65-nm CMOS23
A 5.6 μ A Wide Bandwidth, High Power Supply Rejection Linear Low-Dropout Regulator With 68 dB of PSR Up To 2 MHz23
A Wireless Power and Data Transfer Receiver Achieving 75.4% Effective Power Conversion Efficiency and Supporting 0.1% Modulation Depth for ASK Demodulation23
A 42.2-Gb/s 4.3-pJ/b 60-GHz Digital Transmitter With 12-b/Symbol Polarization MIMO23
A Sub-10-pJ/bit 5-Mb/s Magnetic Human Body Communication Transceiver23
A 12-Level Series-Capacitor 48-1V DC–DC Converter With On-Chip Switch and GaN Hybrid Power Conversion23
The Design of a CMOS Nanoelectrode Array With 4096 Current-Clamp/Voltage-Clamp Amplifiers for Intracellular Recording/Stimulation of Mammalian Neurons22
Piezoelectric Energy-Harvesting Interface Using Split-Phase Flipping-Capacitor Rectifier With Capacitor Reuse for Input Power Adaptation22
A High-Voltage Compliance, 32-Channel Digitally Interfaced Neuromodulation System on Chip22
A 6.5–12.5-Gb/s Half-Rate Single-Loop All-Digital Referenceless CDR in 28-nm CMOS22
A Calibration-Free Time-Interleaved Fourth-Order Noise-Shaping SAR ADC22
Trimming-Less Voltage Reference for Highly Uncertain Harvesting Down to 0.25 V, 5.4 pW22
Energy-Efficient Motion-Triggered IoT CMOS Image Sensor With Capacitor Array-Assisted Charge-Injection SAR ADC22
Indirect Time-of-Flight CMOS Image Sensor With On-Chip Background Light Cancelling and Pseudo-Four-Tap/Two-Tap Hybrid Imaging for Motion Artifact Suppression22
Z-PIM: A Sparsity-Aware Processing-in-Memory Architecture With Fully Variable Weight Bit-Precision for Energy-Efficient Deep Neural Networks22
A 31-$\mu$ W, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS22
A Dynamically High-Impedance Charge-Pump-Based LDO With Digital-LDO-Like Properties Achieving a Sub-4-fs FoM21
A Wideband Low-Power Cryogenic CMOS Circulator for Quantum Applications21
A 64-Channel Transmit Beamformer With ±30-V Bipolar High-Voltage Pulsers for Catheter-Based Ultrasound Probes21
2.4-GHz Highly Selective IoT Receiver Front End With Power Optimized LNTA, Frequency Divider, and Baseband Analog FIR Filter21
A 22.9–38.2-GHz Dual-Path Noise-Canceling LNA With 2.65–4.62-dB NF in 28-nm CMOS21
A 112-dB SFDR 89-dB SNDR VCO-Based Sensor Front-End Enabled by Background-Calibrated Differential Pulse Code Modulation21
A 4–20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS21
A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme21
A 90.2% Peak Efficiency Multi-Input Single-Inductor Multi-Output Energy Harvesting Interface With Double-Conversion Rejection Technique and Buck-Based Dual-Conversion Mode21
A 64-Pixel 0.42-THz Source SoC With Spatial Modulation Diversity for Computational Imaging21
Cascade Current Mirror to Improve Linearity and Consistency in SRAM In-Memory Computing21
THz Prism: One-Shot Simultaneous Localization of Multiple Wireless Nodes With Leaky-Wave THz Antennas and Transceivers in CMOS21
EM and Power SCA-Resilient AES-256 Through >350× Current-Domain Signature Attenuation and Local Lower Metal Routing21
Highly Linear High-Power 802.11ac/ax WLAN SiGe HBT Power Amplifiers With a Compact 2nd-Harmonic-Shorted Four-Way Transformer and a Thermally Compensating Dynamic Bias Circuit21
A Monolithic GaN-IC With Integrated Control Loop for 400-V Offline Buck Operation Achieving 95.6% Peak Efficiency21
Dynamic Focusing of Large Arrays for Wireless Power Transfer and Beyond21
A 265-$\mu$ W Fractional-${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS21
A 4-GS/s 39.9-dB SNDR 11.7-mW Hybrid Voltage-Time Two-Step ADC With Feedforward Ring Oscillator-Based TDCs20
A 1–10-MHz Frequency-Aware CMOS Active Rectifier With Dual-Loop Adaptive Delay Compensation and >230-mW Output Power for Capacitively Powered Biomedical Implants20
A 30-GHz Digital Sub-Sampling Fractional-$N$ PLL With −238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS20
Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication20
A CMOS 1.2-V Hybrid Current- and Voltage-Mode Three-Way Digital Doherty PA With Built-In Phase Nonlinearity Compensation20
First Demonstration of Distributed Amplifier MMICs With More Than 300-GHz Bandwidth20
TG-SPP: A One-Transmission-Gate Short-Path Padding for Wide-Voltage-Range Resilient Circuits in 28-nm CMOS20
A Fully Dynamic Low-Power Wideband Time-Interleaved Noise-Shaping SAR ADC20
Analysis and Design of a Full-Duplex Two-Element MIMO Circulator-Receiver With High TX Power Handling Exploiting MIMO RF and Shared-Delay Baseband Self-Interference Cancellation20
Extracellular Recording of Entire Neural Networks Using a Dual-Mode Microelectrode Array With 19 584 Electrodes and High SNR20
A CMOS Electrochemical Biochip With 32$\times$ 32 Three-Electrode Voltammetry Pixels20
Bandwidth-Enhanced Oversampling Successive Approximation Readout Technique for Low-Noise Power-Efficient MEMS Capacitive Accelerometer20
A Mm-Wave Wideband MIMO RX With Instinctual Array-Based Blocker/Signal Management for Ultralow-Latency Communication20
A 32 × 32-Pixel CMOS Imager for Quantum Optics With Per-SPAD TDC, 19.48% Fill-Factor in a 44.64-μm Pitch Reaching 1-MHz Observation Rate19
A 2.92-Gb/s/W and 0.43-Gb/s/MG Flexible and Scalable CGRA-Based Baseband Processor for Massive MIMO Detection19
A BJT-Based Temperature-to-Digital Converter With a ±0.25 °C 3$\sigma$ -Inaccuracy From −40 °C to +180 °C Using Heater-Assisted Voltage Calibration19
A 7-bit 900-MS/s 2-Then-3-bit/cycle SAR ADC With Background Offset Calibration19
A Two-Step ADC With a Continuous-Time SAR-Based First Stage19
A 16-Element Fully Integrated 28-GHz Digital RX Beamforming Receiver19
A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection19
A 1.33-Tb 4-Bit/Cell 3-D Flash Memory on a 96-Word-Line-Layer Technology19
A Variable-Gain Low-Noise Transimpedance Amplifier for Miniature Ultrasound Probes19
Structure-Reconfigurable Power Amplifier (SR-PA) and 0X/1X Regulating Rectifier for Adaptive Power Control in Wireless Power Transfer System18
Low-Power Organic Light Sensor Array Based on Active-Matrix Common-Gate Transimpedance Amplifier on Foil for Imaging Applications18
An Energy-Efficient 10-Gb/s CMOS Millimeter-Wave Transceiver With Direct-Modulation Digital Transmitter and I/Q Phase-Coupled Frequency Synthesizer18
A 0.5-V Sub-10-μW 15.28-mΩ/√Hz Bio-Impedance Sensor IC With Sub-1° Phase Error18
An Auto-Calibrated Resistive Measurement System With Low Noise Instrumentation ASIC18
A Fully Dynamic Multi-Mode CMOS Vision Sensor With Mixed-Signal Cooperative Motion Sensing and Object Segmentation for Adaptive Edge Computing18
A Data-Compressive 1.5/2.75-bit Log-Gradient QVGA Image Sensor With Multi-Scale Readout for Always-On Object Detection18
An AMOLED Pixel Circuit With a Compensating Scheme for Variations in Subthreshold Slope and Threshold Voltage of Driving TFTs18
A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR18
Multi-Mode 60-GHz Radar Transmitter SoC in 45-nm SOI CMOS18
Opamp-Less Sub-μW/Channel Δ-Modulated Neural-ADC With Super-GΩ Input Impedance18
Large-Area, Fast-Gated Digital SiPM With Integrated TDC for Portable and Wearable Time-Domain NIRS18
Wideband Hybrid Envelope Tracking Modulator With Hysteretic-Controlled Three-Level Switching Converter and Slew-Rate Enhanced Linear Amplifier18
An Eight-Element 140-GHz Wafer-Scale IF Beamforming Phased-Array Receiver With 64-QAM Operation in CMOS RFSOI18
A 20–32-GHz Quadrature Digital Transmitter Using Synthesized Impedance Variation Compensation17
A Self-Calibrated 16-GHz Subsampling-PLL-Based Fast-Chirp FMCW Modulator With 1.5-GHz Bandwidth17
A Fractional-$N$ PLL With Space–Time Averaging for Quantization Noise Reduction17
A 4TX/4RX Pulsed Chirping Phased-Array Radar Transceiver in 65-nm CMOS for X-Band Synthetic Aperture Radar Application17
Integrated Power Management for Battery-Indifferent Systems With Ultra-Wide Adaptation Down to nW17
Octave-Tuning Dual-Core Folded VCO Leveraging a Triple-Mode Switch-Less Tertiary Magnetic Loop17
A Biofuel-Cell-Based Energy Harvester With 86% Peak Efficiency and 0.25-V Minimum Input Voltage Using Source-Adaptive MPPT17
A Highly Linear OTA-Less 1-1 MASH VCO-Based $\Delta\Sigma$ ADC With an Efficient Phase Quantization Noise Extraction Technique17
A Sub-nW/kHz Relaxation Oscillator With Ratioed Reference and Sub-Clock Power Gated Comparator17
A 440-μW, 109.8-dB DR, 106.5-dB SNDR Discrete-Time Zoom ADC With a 20-kHz BW17
A 2-D Mode-Switching Quad-Core Oscillator Using E-M Mixed-Coupling Resonance Boosting17
A 9.6-mW/Ch 10-MHz Wide-Bandwidth Electrical Impedance Tomography IC With Accurate Phase Compensation for Early Breast Cancer Detection17
A 22-ng/$\surd$ Hz 17-mW Capacitive MEMS Accelerometer With Electrically Separated Mass Structure and Digital Noise- Reduction Techniques17
A 50–112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS17
Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition17
A 0.35-V 5,200-μm2 2.1-MHz Temperature-Resilient Relaxation Oscillator With 667 fJ/Cycle Energy Efficiency Using an Asymmetric Swing-Boosted RC Network and a Dual-Path Comparator17
Fully Integrated Switched-Inductor-Capacitor Voltage Regulator With 0.82-A/mm2 Peak Current Density and 78% Peak Power Efficiency17
A 60-Gb/s PAM4 Wireline Receiver With 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS17
An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter17
A 10 fJ·K2 Wheatstone Bridge Temperature Sensor With a Tail-Resistor-Linearized OTA16
A High-Voltage Dual-Input Buck Converter With Bidirectional Inductor Current for Triboelectric Energy-Harvesting Applications16
A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET16
A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding16
A 43–97-GHz Mixer-First Front-End With Quadrature Input Matching and On-Chip Image Rejection16
A 3-to-40-V Automotive-Use GaN Driver With Active Bootstrap Balancing and V SW Dual-Edge Dead-Time Modulation Techniques16
A 1-nA 4.5-nW 289-ppm/°C Current Reference Using Automatic Calibration16
±CIM SRAM for Signed In-Memory Broad-Purpose Computing From DSP to Neural Processing16
Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices16
A 1.8-nW, −73.5-dB PSRR, 0.2-ms Startup Time, CMOS Voltage Reference With Self-Biased Feedback and Capacitively Coupled Schemes16
A Self-Calibrated 2-bit Time-Period Comparator-Based Synthesized Fractional-N MDLL in 22-nm FinFET CMOS16
High Efficiency D-Band Multiway Power Combined Amplifiers With 17.5–19-dBm Psat and 14.2–12.1% Peak PAE in 45-nm CMOS RFSOI16
A 16.1-bit Resolution 0.064-mm2 Compact Highly Digital Closed-Loop Single-VCO-Based 1-1 Sturdy-MASH Resistance-to-Digital Converter With High Robustness in 180-nm CMOS16
A 512-Pixel, 51-kHz-Frame-Rate, Dual-Shank, Lens-Less, Filter-Less Single-Photon Avalanche Diode CMOS Neural Imaging Probe16
Combined In-Pixel Linear and Single-Photon Avalanche Diode Operation With Integrated Biasing for Wide-Dynamic-Range Optical Sensing16
A 245-mA Digitally Assisted Dual-Loop Low-Dropout Regulator16
A 4-GS/s 11.3-mW 7-bit Time-Based ADC With Folding Voltage-to-Time Converter and Pipelined TDC in 65-nm CMOS16
A CMOS Dual-Mode Brain-Computer Interface Chipset With 2-mV Precision Time-Based Charge Balancing and Stimulation-Side Artifact Suppression16
High-Voltage CMOS Active Pixel Sensor16
A Fully Integrated Multilevel Synchronized-Switch-Harvesting-on-Capacitors Interface for Generic PEHs16
An Analog-Proportional Digital-Integral Multiloop Digital LDO With PSR Improvement and LCO Reduction15
A Hybrid Boost Converter With Cross-Connected Flying Capacitors15
A Wide-Range Variation-Resilient Physically Unclonable Function in 28 nm15
An Interference-Resilient BLE-Compatible Wake-Up Receiver Employing Single-Die Multi-Channel FBAR-Based Filtering and a 4-D Wake-Up Signature15
A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion15
A 6.78-MHz Single-Stage Wireless Charger With Constant-Current Constant-Voltage Charging Technique15
SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6–3.6-μW/DMIPS 40–80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode15
Broadband GaN MMIC Doherty Power Amplifier Using Continuous-Mode Combining for 5G Sub-6 GHz Applications15
A 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks15
Direct 12V/24V-to-1V Tri-State Double Step-Down Power Converter With Online V CF Rebalancing and In-Situ Precharge Rate Regulation15
A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4× Passive Gain and Second-Order DAC Mismatch Error Shaping15
An Event-Driven Quasi-Level-Crossing Delta Modulator Based on Residue Quantization15
A Three-Level Boost Converter With Full-Range Auto-Capacitor-Compensation Pulse Frequency Modulation15
A 24.8-μW Biopotential Amplifier Tolerant to 15-VPP Common-Mode Interference for Two-Electrode ECG Recording in 180-nm CMOS15
A Low-Power 70–100-GHz Mixer-First RX Leveraging Frequency-Translational Feedback15
A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References15
Unbalanced Power Amplifier: An Architecture for Broadband Back-Off Efficiency Enhancement15
A 760-nW, 180-nm CMOS Fully Analog Voice Activity Detection System for Domestic Environment15
A 100-Gb/s PAM-4 Optical Receiver With 2-Tap FFE and 2-Tap Direct-Feedback DFE in 28-nm CMOS15
NB-IoT and GNSS All-In-One System-On-Chip Integrating RF Transceiver, 23-dBm CMOS Power Amplifier, Power Management Unit, and Clock Management System for Low Cost Solution15
A Watt-Level Phase-Interleaved Multi-Subharmonic Switching Digital Power Amplifier15
A High-Efficiency 142–182-GHz SiGe BiCMOS Power Amplifier With Broadband Slotline-Based Power Combining Technique15
A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx15
A VHF Wide-Input Range CMOS Passive Rectifier With Active Bias Tuning14
A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique14
A Full-Duplex Receiver With True-Time-Delay Cancelers Based on Switched-Capacitor-Networks Operating Beyond the Delay–Bandwidth Limit14
A 24–29.5-GHz Highly Linear Phased-Array Transceiver Front-End in 65-nm CMOS Supporting 800-MHz 64-QAM and 400-MHz 256-QAM for 5G New Radio14
A 14-GHz Bang-Bang Digital PLL With Sub-150-fs Integrated Jitter for Wireline Applications in 7-nm FinFET CMOS14
Nanowatt Acoustic Inference Sensing Exploiting Nonlinear Analog Feature Extraction14
A Bidirectional Neural Interface SoC With Adaptive IIR Stimulation Artifact Cancelers14
3.2-mW Ultra-Low-Power 173-207-GHz Amplifier With 130-nm SiGe HBTs Operating in Saturation14
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter14
50nW Opamp-Less ΔΣ-Modulated Bioimpedance Spectrum Analyzer for Electrochemical Brain Interfacing14
A 36-Channel Auto-Calibrated Front-End ASIC for a pMUT-Based Miniaturized 3-D Ultrasound System14
Design Techniques for High-Resolution Continuous-Time Delta–Sigma Converters With Low In-Band Noise Spectral Density14
30-Gb/s 1.11-pJ/bit Single-Ended PAM-3 Transceiver for High-Speed Memory Links14
A Light-Load Efficient Fully Integrated Voltage Regulator in 14-nm CMOS With 2.5-nH Package-Embedded Air-Core Inductors14
A Dual-Mode Wi-Fi/BLE Wake-Up Receiver14
Fast & Energy Efficient Start-Up of Crystal Oscillators by Self-Timed Energy Injection14
Design and Analysis of a Sample-and-Hold CMOS Electrochemical Sensor for Aptamer-Based Therapeutic Drug Monitoring14
Analysis and Design of an Audio Continuous-Time 1-X FIR-MASH Delta–Sigma Modulator14
Breaking the Performance Tradeoffs in N-Path Mixer-First Receivers Using a Second-Order Baseband Noise-Canceling TIA14
A Fully Integrated Cryo-CMOS SoC for State Manipulation, Readout, and High-Speed Gate Pulsing of Spin Qubits14
A Second-Order Purely VCO-Based CT $\Delta\Sigma$ ADC Using a Modified DPLL Structure in 40-nm CMOS14
A 13.8-ENOB Fully Dynamic Third-Order Noise-Shaping SAR ADC in a Single-Amplifier EF-CIFF Structure With Hardware-Reusing kT/C Noise Cancellation14
A 28 GHz Single-Input Linear Chireix (SILC) Power Amplifier in 130 nm SiGe Technology14
A 22-bit Read-Out IC With 7-ppm INL and Sub-100-$\mu$ Hz 1/$f$ Corner for DC Measurement Systems14
GANPU: An Energy-Efficient Multi-DNN Training Processor for GANs With Speculative Dual-Sparsity Exploitation14
A Time Domain Artificial Intelligence Radar System Using 33-GHz Direct Sampling for Hand Gesture Recognition14
A 12.3-μW 0.72-mm² Fully Integrated Front-End IC for Arterial Pulse Waveform and ExG Recording14
A 12.5-MHz Bandwidth 77-dB SNDR SAR-Assisted Noise Shaping Pipeline ADC14
A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface14
A Multi-Band 16–52-GHz Transmit Phased Array Employing 4 × 1 Beamforming IC With 14–15.4-dBm P sat for 5G NR FR2 Operation14
Low-Loss Heterogeneous Integrations With High Output Power Radar Applications at W-Band13
A Fast Startup CMOS Crystal Oscillator Using Two-Step Injection13
A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET13
Analysis and Design of a 20-MHz Bandwidth Continuous-Time Delta-Sigma Modulator With Time-Interleaved Virtual-Ground-Switched FIR Feedback13
High-Throughput Dynamic Time Warping Accelerator for Time-Series Classification With Pipelined Mixed-Signal Time-Domain Computing13
A 51-pJ/Pixel 33.7-dB PSNR 4× Compressive CMOS Image Sensor With Column-Parallel Single-Shot Compressive Sensing13
Liquid Silicon: A Nonvolatile Fully Programmable Processing-in-Memory Processor With Monolithically Integrated ReRAM13
In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware Security13
A Low-Power Backscatter Modulation System Communicating Across Tens of Meters With Standards-Compliant Wi-Fi Transceivers13
A Bi-Directional, Zero-Latency Adaptive Clocking Circuit in a 28-nm Wide AVFS System13
DF-LNPU: A Pipelined Direct Feedback Alignment-Based Deep Neural Network Learning Processor for Fast Online Learning13
A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS13
A 13-Bit ENOB Third-Order Noise-Shaping SAR ADC Employing Hybrid Error Control Structure and LMS-Based Foreground Digital Calibration13
Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier13
An 8-Gb GDDR6X DRAM Achieving 22 Gb/s/pin With Single-Ended PAM-4 Signaling13
A MM-Wave Current-Mode Inverse Outphasing Transmitter Front-End: A Circuit Duality of Conventional Voltage-Mode Outphasing13
A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS13
An Eight-Element 136–147 GHz Wafer-Scale Phased-Array Transmitter With 32 dBm Peak EIRP and >16 Gbps 16QAM and 64QAM Operation13
A 0.6V 785-nW Multimodal Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring13
A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based Multiphase Clock Generator13
A Monolithic GaN Power IC With On-Chip Gate Driving, Level Shifting, and Temperature Sensing, Achieving Direct 48-V/1-V DC–DC Conversion13
A Cascaded Hybrid Switched-Capacitor DC–DC Converter Capable of Fast Self Startup for USB Power Delivery13
Analog I/Q FIR Filter in 55-nm SiGe BiCMOS for 16-QAM Optical Communications at 112 Gb/s13
A Reconfigurable and Extendable Single-Inductor Single-Path Three-Switch Converter for Indoor Photovoltaic Energy Harvesting13
A High Dynamic Range 128 × 120 3-D Stacked CMOS SPAD Image Sensor SoC for Fluorescence Microendoscopy13
A Configurable Successive-Cancellation List Polar Decoder Using Split-Tree Architecture13
A 77-dB-DR 0.65-mW 20-MHz 5th-Order Coupled Source Followers Based Low-Pass Filter13
A Fully Integrated 27-dBm Dual-Band All-Digital Polar Transmitter Supporting 160 MHz for Wi-Fi 6 Applications13
A Symmetric Modified Multilevel Ladder PMIC for Battery-Connected Applications13
Clockless, Continuous-Time Analog Correlator Using Time-Encoded Signal Processing Demonstrating Asynchronous CDMA for Wake-Up Receivers13
A 0.07-mm2 162-mW DAC Achieving >65 dBc SFDR and < −70 dBc IM3 at 10 GS/s With Output Impedance Compensation and Concentric Parallelogram Routing13
RRAM-DNN: An RRAM and Model-Compression Empowered All-Weights-On-Chip DNN Accelerator13
Antenna Preprocessing and Element-Pattern Shaping for Multi-Band mmWave Arrays: Multi-Port Transmitters and Antennas12
Dual-Band, Two-Layer Millimeter-Wave Transceiver for Hybrid MIMO Systems12
Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips12
Broadband Active Load-Modulation Power Amplification Using Coupled-Line Baluns: A Multifrequency Role-Exchange Coupler Doherty Amplifier Architecture12
EMI-Regulated GaN-Based Switching Power Converter With Markov Continuous Random Spread-Spectrum Modulation and One-Cycle on-Time Rebalancing12
A 50-Gb/s PAM4 Si-Photonic Transmitter With Digital-Assisted Distributed Driver and Integrated CDR in 40-nm CMOS12
A Fast-Transient 500-mA Digitally Assisted Analog LDO With 30-μ V/mA Load Regulation and 0.0073-ps FoM in 65-nm CMOS12
A 230-GHz High-Power and Wideband Coupled Standing Wave VCO in 65-nm CMOS12
A 9.7-nTᵣₘₛ, 704-ms Magnetic Biosensor Front-End for Detecting Magneto-Relaxation12
A Laser-Forwarded Coherent Transceiver in 45-nm SOI CMOS Using Monolithic Microring Resonators12
A 134-μW 99.4-dB SNDR Audio Continuous-Time Delta-Sigma Modulator With Chopped Negative-R and Tri-Level FIR-DAC12
A Digitally Assisted Multiplexed Neural Recording System With Dynamic Electrode Offset Cancellation via an LMS Interference-Canceling Filter12
A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator12
An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Amplifiers in 28-nm CMOS12
ADC-DSP-Based 10-to-112-Gb/s Multi-Standard Receiver in 7-nm FinFET12
Sub-μWRComm: 415-nW 1–10-kb/s Physically and Mathematically Secure Electro-Quasi-Static HBC Node for Authentication and Medical Applications12
A Wideband Four-Way Doherty Bits-In RF-Out CMOS Transmitter12
Bidirectional Peripheral Nerve Interface With 64 Second-Order Opamp-Less ΔΣ ADCs and Fully Integrated Wireless Power/Data Transmission12
Low-Power High-Linearity Mixer-First Receiver Using Implicit Capacitive Stacking With 3× Voltage Gain12
A 128 Gb/s, 11.2 mW Single-Ended PAM4 Linear TIA With 2.7 μArms Input Noise in 22 nm FinFET CMOS12
Retinal Stimulator ASIC Architecture Based on a Joint Power and Data Optical Link12
A Wearable Real-Time CMOS Dosimeter With Integrated Zero-Bias Floating Gate Sensor and an 861-nW 18-Bit Energy-Resolution Scalable Time-Based Radiation to Digital Converter12
Multi-Watt, 1-GHz CMOS Circulator Based on Switched-Capacitor Clock Boosting11
Machine Learning Assisted Side-Channel-Attack Countermeasure and Its Application on a 28-nm AES Circuit11
Multi-Feed Antenna and Electronics Co-Design: An E-Band Antenna-LNA Front End With On-Antenna Noise-Canceling and Gₘ-Boosting11
A 91.15% Efficient 2.3–5-V Input 10–35-V Output Hybrid Boost Converter for LED-Driver Applications11
Low-Power Highly Selective Channel Filtering Using a Transconductor–Capacitor Analog FIR11
A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3σ Inaccuracy of +0.02%, −0.12% for Battery-Monitoring Applications11
A Variation-Resilient Microprocessor With a Two-Level Timing Error Detection and Correction System in 28-nm CMOS11
A Monolithically Integrated Single-Input Load-Modulated Balanced Amplifier With Enhanced Efficiency at Power Back-Off11
A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS11
A Time-Domain Computing Accelerated Image Recognition Processor With Efficient Time Encoding and Non-Linear Logic Operation11
A Code-Domain RF Signal Processing Front End With High Self-Interference Rejection and Power Handling for Simultaneous Transmit and Receive11
High-Density 3-D Stackable Crossbar 2D2R nvTCAM With Low-Power Intelligent Search for Fast Packet Forwarding in 5G Applications11
A 5.2-Mpixel 88.4-dB DR 12-in CMOS X-Ray Detector With 16-bit Column-Parallel Continuous-Time Incremental ΔΣ ADCs11
A Neural Network Training Processor With 8-Bit Shared Exponent Bias Floating Point and Multiple-Way Fused Multiply-Add Trees11
A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-V MIN11
Millimeter-Scale Node-to-Node Radio Using a Carrier Frequency-Interlocking IF Receiver for a Fully Integrated 4$\times$ 4$\times$ 4 mm3 Wireless Sensor Node11
A 15.1-mW 6-GS/s 6-bit Single-Channel Flash ADC With Selectively Activated 8× Time-Domain Latch Interpolation11
A 4900-$\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition11
A 4-Element Digital Modulated Polar Phased-Array Transmitter With Phase Modulation Phase-Shifting11
An Automotive LiDAR SoC for 240 × 192-Pixel 225-m-Range Imaging With a 40-Channel 0.0036-mm2 Voltage/Time Dual-Data-Converter-Based AFE11
A High-Efficiency Dual-Polarity Thermoelectric Energy-Harvesting Interface Circuit With Cold Startup and Fast-Searching ZCD11
A Ka-Band Doherty-Like LMBA for High-Speed Wireless Communication in 28-nm CMOS11
A 65-nm 8-to-3-b 1.0–0.36-V 9.1–1.1-TOPS/W Hybrid-Digital-Mixed-Signal Computing Platform for Accelerating Swarm Robotics11
Design of Sub-10-μW Sub-0.1% THD Sinusoidal Current Generator IC for Bio-Impedance Sensing11
A 354F2 Leakage-Based Physically Unclonable Function With Lossless Stabilization Through Remapping for Low-Cost IoT Security11
A Broadband 300 GHz Power Amplifier in a 130 nm SiGe BiCMOS Technology for Communication Applications11
Silicon Photonic Microring-Based 4 × 112 Gb/s WDM Transmitter With Photocurrent-Based Thermal Control in 28-nm CMOS11
A Low-Jitter and Low-Spur Charge-Sampling PLL11
NeuroSLAM: A 65-nm 7.25-to-8.79-TOPS/W Mixed-Signal Oscillator-Based SLAM Accelerator for Edge Robotics11
A Discrete-Time Audio $\Delta\Sigma$ Modulator Using Dynamic Amplifier With Speed Enhancement and Flicker Noise Reduction Techniques11
A Time-Interleaved Resonant Voltage Mode Wireless Power Receiver With Delay-Based Tracking Loops for Implantable Medical Devices11
A 32-MHz, 34-μW Temperature-Compensated RC Oscillator Using Pulse Density Modulated Resistors10
A 4-GHz Sub-Harmonically Injection-Locked Phase-Locked Loop With Self-Calibrated Injection Timing and Pulsewidth10
Sub-Sampling Direct RF-to-Digital Converter With 1024-APSK Modulation for High Throughput Polar Receiver10
An All-Digital Fused PLL-Buck Architecture for 82% Average V dd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor10
A Baseband-Matching-Resistor Noise-Canceling Receiver With a Three-Stage Inverter-Only OpAmp for High In-Band IIP3 and Wide IF Applications10
Quadrature Switched/Floated Capacitor Power Amplifier With Reconfigurable Self-Coupling Canceling Transformer for Deep Back-Off Efficiency Enhancement10
Wireless Body-Area-Network Transceiver and Low-Power Receiver With High Application Expandability10
A 15-Channel Orthogonal Code Chopping Instrumentation Amplifier for Area-Efficient, Low-Mismatch Bio-Signal Acquisition10
A Dual-Mode Continuously Scalable-Conversion-Ratio SC Energy Harvesting Interface With SC-Based PFM MPPT and Flying Capacitor Sharing Scheme10
A 148-nW Reconfigurable Event-Driven Intelligent Wake-Up System for AIoT Nodes Using an Asynchronous Pulse-Based Feature Extractor and a Convolutional Neural Network10
A W-Band Single-Antenna FMCW Radar Transceiver With Adaptive Leakage Cancellation10
A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET10
A Hybrid Single-Inductor Bipolar-Output DC–DC Converter With Floating Negative Output for AMOLED Displays10
A 77.1-dB-SNDR 6.25-MHz-BW Pipeline SAR ADC With Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping10
A 0.7–5.7 GHz Reconfigurable MIMO Receiver Architecture for Analog Spatial Notch Filtering Using Orthogonal Beamforming10
Scalable and Programmable Neural Network Inference Accelerator Based on In-Memory Computing10
A 10-Gb/s 180-GHz Phase-Locked-Loop Minimum Shift Keying Receiver10
A 7-nm FinFET CMOS PLL With 388-fs Jitter and −80-dBc Reference Spur Featuring a Track-and-Hold Charge Pump and Automatic Loop Gain Control10
A 0.31-THz Orbital-Angular-Momentum (OAM) Wave Transceiver in CMOS With Bits-to-OAM Mode Mapping10
Sub-nW Microcontroller With Dual-Mode Logic and Self-Startup for Battery-Indifferent Sensor Nodes10
A 56-Gb/s 50-mW NRZ Receiver in 28-nm CMOS10
A Light-Tolerant Wireless Neural Recording IC for Motor Prediction With Near-Infrared-Based Power and Data Telemetry10
A Fractional-N Reference Sampling PLL With Linear Sampler and CDAC Based Fractional Spur Cancellation10
A Deep-Subthreshold Variation-Aware 0.2-V Open-Loop VCO-Based ADC10
A Multimode Multi-Efficiency-Peak Digital Power Amplifier10
STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse10
A Reconfigurable Capacitive Power Converter With Capacitance Redistribution for Indoor Light-Powered Batteryless Internet-of-Things Devices10
A Wirelessly Powered Reconfigurable FDD Radio With On-Chip Antennas for Multi-Site Neural Interfaces10
COMPAC: Compressed Time-Domain, Pooling-Aware Convolution CNN Engine With Reduced Data Movement for Energy-Efficient AI Computing10
A Quadrature Class-G Complex-Domain Doherty Digital Power Amplifier10
A 112-Gb/s PAM-4 Voltage-Mode Transmitter With Four-Tap Two-Step FFE and Automatic Phase Alignment Techniques in 40-nm CMOS10
A 1.87-mm2 56.9-GOPS Accelerator for Solving Partial Differential Equations10
A Self-Gating RF Energy Harvester for Wireless Power Transfer With High-PAPR Incident Waveform10
A 28-GHz Beam-Space MIMO RX With Spatial Filtering and Frequency-Division Multiplexing-Based Single-Wire IF Interface10
Highly Integrated Guidewire Ultrasound Imaging System-on-a-Chip10
Code-Domain Multiplexing for Shared IF/LO Interfaces in Millimeter-Wave MIMO Arrays10
A 2.5-nW Radio Platform With an Internal Wake-Up Receiver for Smart Contact Lens Using a Single Loop Antenna10
A Type-II Phase-Tracking Receiver10
A 0.6-mW 16-FSK Receiver Achieving a Sensitivity of −103 dBm at 100 kb/s10
A Single BJT Bandgap Reference With Frequency Compensation Exploiting Mirror Pole10
Robust, Efficient Distributed Power Amplifier Achieving 96 Gbit/s With 10 dBm Average Output Power and 3.7% PAE in 22-nm FD-SOI9
An Implantable Neuromorphic Sensing System Featuring Near-Sensor Computation and Send-on-Delta Transmission for Wireless Neural Sensing of Peripheral Nerves9
CMOS THz-ID: A 1.6-mm² Package-Less Identification Tag Using Asymmetric Cryptography and 260-GHz Far-Field Backscatter Communication9
Integrated Self-Adaptive and Power-Scalable Wideband Interference Cancellation for Full-Duplex MIMO Wireless9
A 24–30-GHz 256-Element Dual-Polarized 5G Phased Array Using Fast On-Chip Beam Calculators and Magnetoelectric Dipole Antennas9
PUF Architecture with Run-Time Adaptation for Resilient and Energy-Efficient Key Generation via Sensor Fusion9
Periodically Time-Varying Noise Cancellation for Filtering-by-Aliasing Receiver Front Ends9
A Software-Defined Always-On System With 57–75-nW Wake-Up Function Using Asynchronous Clock-Free Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC9
A Pipeline SAR ADC With Second-Order Interstage Gain Error Shaping9
A CMOS 21 952-Pixel Multi-Modal Cell-Based Biosensor With Four-Point Impedance Sensing for Holistic Cellular Characterization9
Fully Integrated GaN-on-Silicon Gate Driver and GaN Switch With Temperature-Compensated Fast Turn-on Technique for Achieving Switching Frequency of 50 MHz and Slew Rate of 118.3 V/Ns9
A Scalable CMOS Ising Computer Featuring Sparse and Reconfigurable Spin Interconnects for Solving Combinatorial Optimization Problems9
Catena: A Near-Threshold, Sub-0.4-mW, 16-Core Programmable Spatial Array Accelerator for the Ultralow-Power Mobile and Embedded Internet of Things9
An Automotive-Use Battery-to-Load GaN-Based Switching Power Converter With Anti-Aliasing MR-SSM and In-Cycle Adaptive ZVS Techniques9
Fully Synthesizable Unified True Random Number Generator and Cryptographic Core9
A 32-Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver With Adaptive Echo Cancellation Techniques9
A Monolithic Resonant Switched-Capacitor Voltage Regulator With Dual-Phase Merged-LC Resonator9
A 32-A, 5-V-Input, 94.2% Peak Efficiency High-Frequency Power Converter Module Featuring Package-Integrated Low-Voltage GaN nMOS Power Transistors9
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix–Matrix Multiplication Accelerator9
A 124-dB Dynamic-Range SPAD Photon-Counting Image Sensor Using Subframe Sampling and Extrapolating Photon Count9
A 390-GHz Outphasing Transmitter in 28-nm CMOS9
A Patient-Specific Closed-Loop Epilepsy Management SoC With One-Shot Learning and Online Tuning9
A 1.2-Mpixel Indirect Time-of-Flight Image Sensor With 4-Tap 3.5-μm Pixels for Peak Current Mitigation and Multi-User Interference Cancellation9
A 28-nm 10-b 2.2-GS/s 18.2-mW Relative-Prime Time-Interleaved Sub-Ranging SAR ADC With On-Chip Background Skew Calibration9
Design of a Bone-Guided Cochlear Implant Microsystem With Monopolar Biphasic Multiple Stimulations and Evoked Compound Action Potential Acquisition and Its In Vivo Verification9
S2ADC: A 12-bit, 1.25-MS/s Secure SAR ADC With Power Side-Channel Attack Resistance9
Design of High-Gain Sub-THz Regenerative Amplifiers Based on Double-G max Gain Boosting Technique9
An Embedded nand Flash-Based Compute-In-Memory Array Demonstrated in a Standard Logic Process9
A Fill-In Technique for Robust IMD Suppression in Chopper Amplifiers9
A Quadrature Digital Power Amplifier With Hybrid Doherty and Impedance Boosting for Complex Domain Power Back-Off Efficiency Enhancement9
A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling9
An Energy-Efficient Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access9
A 1.3–4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line9
A Four-Way Series Doherty Digital Polar Transmitter at mm-Wave Frequencies9
A Single-Pin Antenna Interface RF Front End Using a Single-MOS DCO-PA and a Push–Pull LNA9
mm-Wave Mixer-First Receiver With Selective Passive Wideband Low-Pass Filtering9
An OTA-Less Second-Order VCO-Based CT $\Delta\Sigma$ Modulator Using an Inherent Passive Integrator and Capacitive Feedback9
A 0-dB STF-Peaking 85-MHz BW 74.4-dB SNDR CT ΔΣ ADC With Unary-Approximating DAC Calibration in 28-nm CMOS9
A 420-GHz Sub-5-μm Range Resolution TX–RX Phase Imaging System in 40-nm CMOS Technology9
A Low-Noise Low-Power Chopper Instrumentation Amplifier With Robust Technique for Mitigating Chopping Ripples9
A 103-dB SFDR Calibration-Free Oversampled SAR ADC With Mismatch Error Shaping and Pre-Comparison Techniques9
Terahertz Even-Order Subharmonic Mixer Using Symmetric MOS Varactors9
A Single-Stage Dual-Output Regulating Rectifier With Hysteretic Current-Wave Modulation9
An 11-b 100-MS/s Fully Dynamic Pipelined ADC Using a High-Linearity Dynamic Amplifier9
A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV, and SRAM PUF for Authentication and Secret Key Generation9
A Power-Efficient Fractional-N DPLL With Phase Error Quantized in Fully Differential-Voltage Domain9
A 10-MHz Current-Mode AOT Boost Converter With Dual-Ramp Modulation Scheme and Translinear Loop-Based Current Sensor for WiFi IoT Applications8
Single Transformer-Based Compact Doherty Power Amplifiers for 5G RF Phased-Array ICs8
Antenna Preprocessing and Element-Pattern Shaping for Multi-Band mmWave Arrays: Multi-Port Receivers and Antennas8
A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta–Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS8
An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch8
A 52% Peak Efficiency > 1-W Isolated Power Transfer System Using Fully Integrated Transformer With Magnetic Core8
A mm-Wave Switched-Capacitor RFDAC8
A 0.8 V Multimode Vision Sensor for Motion and Saliency Detection With Ping-Pong PWM Pixel8
A 4-GS/s 80-dB DR Current-Domain Analog Frontend for Phase-Coded Pulse-Compression Direct Time-of-Flight Automotive Lidar8
A 0.5-V BLE Transceiver With a 1.9-mW RX Achieving −96.4-dBm Sensitivity and −27-dBm Tolerance for Intermodulation From Interferers at 6- and 12-MHz Offsets8
A 0.65-mW-to-1-W Photovoltaic Energy Harvester With Irradiance-Aware Auto-Configurable Hybrid MPPT Achieving >95% MPPT Efficiency and 2.9-ms FOCV Transient Time8
Reference Oversampling PLL Achieving −256-dB FoM and −78-dBc Reference Spur8
A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking8
A 28-W, −102.2-dB THD+N Class-D Amplifier Using a Hybrid ΔΣM-PWM Scheme8
A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS8
A 10-MHz Closed-Loop EMI-Regulated GaN Switching Power Converter Using Emulated Miller Plateau Tracking and Adaptive Strength Gate Driving8
A 368 × 184 Optical Under-Display Fingerprint Sensor Comprising Hybrid Arrays of Global and Rolling Shutter Pixels With Shared Pixel-Level ADCs8
Static CMOS Physically Unclonable Function Based on 4T Voltage Divider With 0.6%–1.5% Bit Instability at 0.4–1.8 V Operation in 180 nm8
A 3-nm Gate-All-Around SRAM Featuring an Adaptive Dual-Bitline and an Adaptive Cell-Power Assist Circuit8
A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth8
A 2.4 GHz-91.5 dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver8