OOIR: Observatory of International Research

Papers

(The median citation count of IEEE Journal of Solid-State Circuits is 2. The table below lists those papers that are above that threshold based on CrossRef citation counts [max. 250 papers]. The publications cover those that have been published in the past four years, i.e., from 2021-03-01 to 2025-03-01.)

Article	Citations
Information For Authors	102
IEEE JOURNAL OF SOLID-STATE CIRCUITS	83
Table of Contents	83
Table of Contents	77
Table of Contents	71
Introducing IEEE Collabratec	68
Table of Contents	68
IEEE Journal of Solid-State Circuits Publication Information	66
Together, we are advancing technology	60
Together, we are advancing technology	59
Table of Contents	58
Information For Authors	58
Table of Contents	55
Introducing IEEE Collabratec	55
Introducing IEEE Collabratec	54
TechRxiv: Share Your Preprint Research with the World!	53
TechRxiv: Share Your Preprint Research with the World!	53
TechRxiv: Share Your Preprint Research with the World!	52
Introducing IEEE Collabratec	52
Guest Editorial 2022 Custom Integrated Circuits Conference	51
Introducing IEEE Collabratec	51
Information For Authors	50
NeuroFlare: An mm³-Scale Wireless Neural Interface Device With Simultaneous Neural Recording and Optical Stimulation	49
A 49.8-mm² IR-UWB Transmitter With Co-Designed Power Amplifier and Antenna for Neural Implants With Extended Transmission Range	49
A Polar Phase-Tracking Receiver With Two-Point Injection Technique	46

A 128-kbit Approximate Search-Capable Content-Addressable Memory (CAM) With Tunable Hamming Distance	46
Compact PNP BJT-Based Temperature Sensor and Sub-1-V Bandgap Reference for SoC Applications in 4-nm FinFET	44
An E-Band FMCW Radar Receiver With Arbitrary-Path Spillover Cancellation	44
Introducing IEEE Collabratec	43
Table of Contents	43
Information For Authors	43
Table of Contents	43
Information For Authors	43
New Associate Editor	43
TechRxiv: Share Your Preprint Research with the World!	43
Table of Contents	43
Table of Contents	42
Table of Contents	42
IEEE Access	42
BioCas 2022	42
Together, we are advancing technology	41
Together, we are advancing technology	41
Table of Contents	41
Table of contents	40
New Associate Editor	40
IEEE JOURNAL OF SOLID-STATE CIRCUITS	40
IEEE JOURNAL OF SOLID-STATE CIRCUITS	39
TechRxiv: Share Your Preprint Research with the World!	39
Introducing IEEE Collabratec	39
Table of Contents	38
Table of Contents	36
TechRxiv: Share Your Preprint Research with the World!	36
A Programmable Filtering and Frequency Translation by Aliasing IF Receiver With Alias and Harmonic Rejection	36
A Fully Integrated Electrostatic Charge Boosting Rectifier for Triboelectric Energy Harvesting	36
Message From the Incoming Editor-in-Chief	36
IEEE JOURNAL OF SOLID-STATE CIRCUITS	35
A 2.5–5-V Input 100-V Output 86.2% Peak Efficiency Fibonacci–Dickson Hybrid Converter for Acoustic Surface Audio Driver	35
A 0.38-mW 200-kHz-BW Digital-Intensive Single-Opamp Fourth-Order Continuous-Time Delta-Sigma Modulator With Third-Order Digital Noise Coupling in 28-nm CMOS	35
Information For Authors	35
Table of Contents	35
IEEE Journal of Solid-State Circuits Publication Information	35
IEEE JOURNAL OF SOLID-STATE CIRCUITS	35
Table of Contents	35
A 3-nm Gate-All-Around SRAM Featuring an Adaptive Dual-Bitline and an Adaptive Cell-Power Assist Circuit	34
A Compact 19.7- to 43.8-GHz Power Amplifier With 20.3-dBm Psat and 35.5% PAE in 28-nm Bulk CMOS	34
Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology	34
A Simultaneous Bidirectional Single-Ended Coaxial Link With 24-Gb/s Forward and 312.5-Mb/s Back Channels	34
A Multi-Band 16–52-GHz Transmit Phased Array Employing 4 × 1 Beamforming IC With 14–15.4-dBm P _sat for 5G NR FR2 Operation	34
Dual-Mode Operations of Self-Rectifying Ferroelectric Tunnel Junction Crosspoint Array for High-Density Integration of IoT Devices	33
A 1 mm ×1 mm CGM System on Die Achieving 1.65-nA/mM In Vivo Resolution and 0–40-mM/L Detection Range With ΔΣ Backscatter Technique	33
A 33-Gb/s/Pin 1.09-pJ/Bit Single-Ended PAM-3 Transceiver With Ground-Referenced Signaling and Time-Domain Decision Technique for Multi-Chip Module Memory Interfaces	32
High-Scalability CMOS Quantum Magnetometer With Spin-State Excitation and Detection of Diamond Color Centers	32
A 112-Gb/s PAM-4 Voltage-Mode Transmitter With Four-Tap Two-Step FFE and Automatic Phase Alignment Techniques in 40-nm CMOS	32
Chip-to-Chip Interfaces for Large-Scale Highly Configurable mmWave Phased Arrays	32
A 334 μW 0.158 mm² ASIC for Post-Quantum Key-Encapsulation Mechanism Saber With Low-Latency Striding Toom–Cook Multiplication	32

39 000-Subexposures/s Dual-ADC CMOS Image Sensor With Dual-Tap Coded-Exposure Pixels for Single-Shot HDR and 3-D Computational Imaging	32
An Automotive-Use Battery-to-Load GaN-Based Switching Power Converter With Anti-Aliasing MR-SSM and In-Cycle Adaptive ZVS Techniques	32
A 10-Gb/s 180-GHz Phase-Locked-Loop Minimum Shift Keying Receiver	32
A Compact and Low Phase Noise Square-Geometry Quad-Core Class-F VCO Using Parallel Inductor-Sharing Technique	32
A 1.8-nW, −73.5-dB PSRR, 0.2-ms Startup Time, CMOS Voltage Reference With Self-Biased Feedback and Capacitively Coupled Schemes	32
IMPACT: A 1-to-4b 813-TOPS/W 22-nm FD-SOI Compute-in-Memory CNN Accelerator Featuring a 4.2-POPS/W 146-TOPS/mm² CIM-SRAM With Multi-Bit Analog Batch-Normalization	32
Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs	31
A 95% Peak Efficiency Modified KY Converter With Improved Flying Capacitor Charging in DCM for IoT Applications	31
Dynamic Focusing of Large Arrays for Wireless Power Transfer and Beyond	31
Monostatic and Bistatic G-Band BiCMOS Radar Transceivers With On-Chip Antennas and Tunable TX-to-RX Leakage Cancellation	31
A 3.5-mV Input Single-Inductor Self-Starting Boost Converter With Loss-Aware MPPT for Efficient Autonomous Body-Heat Energy Harvesting	31
Analysis and Design of Wideband Filtering ADCs Using Continuous-Time Pipelining	31
A Baseband-Matching-Resistor Noise-Canceling Receiver With a Three-Stage Inverter-Only OpAmp for High In-Band IIP3 and Wide IF Applications	31
A 12-to-1 V Quad-Output Switched-Capacitor Buck Converter With Shared DC Capacitors	30
DF-LNPU: A Pipelined Direct Feedback Alignment-Based Deep Neural Network Learning Processor for Fast Online Learning	30
A 9.6-mW/Ch 10-MHz Wide-Bandwidth Electrical Impedance Tomography IC With Accurate Phase Compensation for Early Breast Cancer Detection	30
A 65-nm 0.6-fJ/Bit/Search Ternary Content Addressable Memory Using an Adaptive Match-Line Discharge	30
A 0.05-mm² 2.91-nJ/Decision Keyword-Spotting (KWS) Chip Featuring an Always-Retention 5T-SRAM in 28-nm CMOS	30
A Charge Recycling Logic Data Links for Single- and Multiple-Channel I/Os	30
A 0.65-mW-to-1-W Photovoltaic Energy Harvester With Irradiance-Aware Auto-Configurable Hybrid MPPT Achieving >95% MPPT Efficiency and 2.9-ms FOCV Transient Time	30
A Process-Scalable Ultra-Low-Voltage Sleep Timer With a Time-Domain Amplifier and a Switch-Less Resistance Multiplier	30
A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface	30
Direct TOF Scanning LiDAR Sensor With Two-Step Multievent Histogramming TDC and Embedded Interference Filter	29
ADC-DSP-Based 10-to-112-Gb/s Multi-Standard Receiver in 7-nm FinFET	29
RRAM-DNN: An RRAM and Model-Compression Empowered All-Weights-On-Chip DNN Accelerator	29
A Time Amplifier Assisted Frequency-to-Digital Converter Based Digital Fractional-N PLL	29
A Transformer-Based Quadrature Doherty Digital Power Amplifier With 4.1 W Peak Power in 28 nm Bulk CMOS	29
A Three-Level Boost Converter With Fully State-Based Phase Selection Technique for High-Speed V_CF Calibration and Smooth Mode Transition	29
A 368 × 184 Optical Under-Display Fingerprint Sensor Comprising Hybrid Arrays of Global and Rolling Shutter Pixels With Shared Pixel-Level ADCs	29
Voltage Level Detection for Near-V _TH Computing	29
A Thin Elastic NFC Forum Type 1 Compatible RFID Tag	28
A Reconfigurable Single-Inductor Multi-Stage Hybrid Converter for 1-Cell Battery Chargers	28
A Low-Stimulus-Scattering Pixel-Sharing Sub-Retinal Prosthesis SoC With Time-Based Photodiode Sensing and Per-Pixel Dynamic Voltage Scaling	28
A Bidirectional Neural Interface SoC With Adaptive IIR Stimulation Artifact Cancelers	28
Retinal Stimulator ASIC Architecture Based on a Joint Power and Data Optical Link	28
DIMCA: An Area-Efficient Digital In-Memory Computing Macro Featuring Approximate Arithmetic Hardware in 28 nm	27
Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports	27
An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch	27
A Sub-5mW Monolithic CMOS-MEMS Thermal Flow Sensing SoC With ±6 m/s Linear Range	27
A 65-nm CMOS Fluorescence Sensor for Dynamic Monitoring of Living Cells	27
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering	27
SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6–3.6-μW/DMIPS 40–80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode	27
Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC)	26
Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2–8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing	26
A Highly Integrated Distributed Mixer Receiver for Low-Power Wireless Radios	26
A Fully Integrated IEEE 802.15.4/4z-Compliant UWB System-on-Chip RF Transceiver Supporting Precision Positioning in a CMOS 28-nm Process	26
A 10-GS/s NRZ/Mixing DAC With Switching-Glitch Compensation Achieving SFDR >64/50 dBc Over the First/Second Nyquist Zone	26
A Reconfigurable Non-Uniform Power-Combining V-Band PA With +17.9 dBm P_sat and 26.5% PAE in 16-nm FinFET CMOS	26
A Nonvolatile AI-Edge Processor With SLC–MLC Hybrid ReRAM Compute-in-Memory Macro Using Current–Voltage-Hybrid Readout Scheme	26
eDRAM-CIM: Reconfigurable Charge Domain Compute-In-Memory Design With Embedded Dynamic Random Access Memory Array Realizing Adaptive Data Converters	25
Analysis and Comparison of Logic Architectures for Digital Circuits in a-IGZO Thin-Film Transistor Technologies	25
A 22.9–38.2-GHz Dual-Path Noise-Canceling LNA With 2.65–4.62-dB NF in 28-nm CMOS	25
A Compact 0.2–0.3-V Inverse-Class-F₂₃ Oscillator for Low 1/f ³ Noise Over Wide Tuning Range	25
0.5–1-V, 90–400-mA, Modular, Distributed, 3 × 3 Digital LDOs Based on Event-Driven Control and Domino Sampling and Regulation	25
Reference Oversampling PLL Achieving −256-dB FoM and −78-dBc Reference Spur	25
A Compact 10-MHz RC Frequency Reference With a Versatile Temperature Compensation Scheme	25
A 50.7-dB-DR Finger-Resistance Extracting Multi-Touch Sensor IC for Soft Classification of Fingers Contacted on 6.7-in Capacitive Touch Screen Panel	25
A Wideband Full-Duplex Receiver With Multi-Domain Self-Interference Cancellation Based on Capacitor Stacking Delay and Delay Compensation in Cancellers	25
A Wideband Sliding Digital-IF Quadrature Digital Transmitter for Multimode NB-IoT/BLE Applications	25
A 27 W Wireless Power Transceiver With Compact Single-Stage Regulated Class-E Architecture and Adaptive ZVS Control	25
An Area-Efficient Smart Temperature Sensor Based on a Fully Current Processing Error-Feedback Noise-Shaping SAR ADC in 180-nm CMOS	24
A 0.58-mm² 2.76-Gb/s 79.8-pJ/b 256-QAM Message-Passing Detector for a 128 × 32 Massive MIMO Uplink System	24
Analog Front End of 50-Gb/s SiGe BiCMOS Opto-Electrical Receiver in 3-D-Integrated Silicon Photonics Technology	24
Guest Editorial Introduction to the Special Section on the 2020 IEEE BCICTS Conference	24
A 2.4 GHz-91.5 dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver	24
A 52–73-GHz LNA With Tri-Coupled Transformer for G _m Boosting and Enhanced Noise Canceling	24
A 12-Level Series-Capacitor 48-1V DC–DC Converter With On-Chip Switch and GaN Hybrid Power Conversion	24
An Energy-Efficient GAN Accelerator With On-Chip Training for Domain-Specific Optimization	24
A 0.61-μW Fully Integrated Keyword-Spotting ASIC With Real-Point Serial FFT-Based MFCC and Temporal Depthwise Separable CNN	24
A High-Efficiency 142–182-GHz SiGe BiCMOS Power Amplifier With Broadband Slotline-Based Power Combining Technique	24
Fixed-Switching-Frequency Background Capacitor-Current-Sensor Calibration for DC–DC Converters	24
Syn-STELLAR: An EM/Power SCA-Resilient AES-256 With Synthesis-Friendly Signature Attenuation	23
A Fill-In Technique for Robust IMD Suppression in Chopper Amplifiers	23
A Chip-PCB Hybrid SC PUF Used for Anti-Desoldering and Depackaging-Attack Protection	23
A 511-μW 89-dB-SNDR Asynchronous SAR-ISDM ADC With Noise Shaping Dynamic Amplifier and Time-Domain Noise-Slicing Technique	23
A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking	23
Introduction to the Special Section on the 2020 Asian Solid-State Circuits Conference (A-SSCC)	23
An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips	23
Picowatt-Power Super-Cutoff Analog Building Blocks and 78-pW Battery-Less Wake-Up Receiver for Light-Harvested Near-Always-On Operation	23
A 10-Gb/s True Random Number Generator Using ML-Resistant Middle Square Method	23

An Anti-Aliasing-Filter-Assisted 3rd-Order VCO-Based CTDSM With NS-SAR Quantizer	22
Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode	22
A High Conversion Ratio and 97.4% High Efficiency Three-Switch Boost Converter With Duty-Dependent Charge Topology for 1.2-A High Driving Current and 20% Reduction of Inductor DC Current in MiniLED Ap	22
Erratum to “High-Power Radiation at 1 THz in Silicon: A Fully Scalable Array Using a Multi-Functional Radiating Mesh Structure”	22
Design of a Noncoherent 100-Gb/s 3-m Dual-Band PAM-4 Dielectric Waveguide Link in 28-nm CMOS	22
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter	22
A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth	22
New Associate Editor	22
A High-Efficiency 40.68-MHz Single-Stage Dual-Output Regulating Rectifier With ZVS and Synchronous PFM Control for Wireless Powering	22
A Through-Power-Link Hysteretic-Controlled Capacitive Isolated DC–DC Converter With Enhanced Efficiency and Common-Mode Transient Immunity	22
Introduction to the Special Section on the 2021 IEEE International Solid-State Circuits Conference (ISSCC)	21
A Scalable CMOS Ising Computer Featuring Sparse and Reconfigurable Spin Interconnects for Solving Combinatorial Optimization Problems	21
A Fully Integrated Cryo-CMOS SoC for State Manipulation, Readout, and High-Speed Gate Pulsing of Spin Qubits	21
A 3.2-GHz 405 fs_rms Jitter –237.2 dB FoM_JIT Ring-Based Fractional-N Synthesizer	21
Guest Editorial Introduction to the Special Issue on the 2021 IEEE International Solid-State Circuits Conference (ISSCC)	21
A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling	21
A Partially Feedback NSSAR Embedded Third-Order Delta–Sigma Modulator With Gain-Boosted Two-Stage FIAs	21
A −121.5-dB THD Class-D Audio Amplifier With 49-dB LC Filter Nonlinearity Suppression	21
A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC With Gain and Offset Calibrations	21
A 43 nW, 32 kHz, ±4.2 ppm Piecewise Linear Temperature-Compensated Crystal Oscillator With ΔΣ-Modulated Load Capacitance	21
A 0.45-THz 2-D Scalable Radiator Array With 28.2-dBm EIRP Using an Elliptical Teflon Lens	21
OTA-Free 1–1 MASH ADC Using Fully Passive Noise-Shaping SAR & VCO ADC	21
A 13.56-MHz Single-Input Dual-Output Wireless Power and Data Transfer System for Bio-Implants	21
A 48–80-V Input 2-MHz Adaptive ZVT-Assisted Bus Converter With Light-Load Efficiency Improvement	21
A Wireless Somatosensory Feedback System Using Human Body Communication	21
CIM-Spin: A Scalable CMOS Annealing Processor With Digital In-Memory Spin Operators and Register Spins for Combinatorial Optimization Problems	21
A 3.36-μm-Pitch SPAD Photon-Counting Image Sensor Using a Clustered Multi-Cycle Clocked Recharging Technique With an Intermediate Most-Significant-Bit Readout	21
Magnetoelectric Bio-Implants Powered and Programmed by a Single Transmitter for Coordinated Multisite Stimulation	21
A Low-Power, Compact, 0.1–5.5-GHz, 40-dBm IB OIP3 LNTA-First Receiver for SDR	20
HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs	20
A 5 Gb/s Time-Interleaved Voltage-Mode Duobinary Encoding Scheme for 3-D-Stacked IC	20
A 16 MHz CMOS RC Frequency Reference With ±90 ppm Inaccuracy From −45 °C to 85 °C	20
A 2×56 Gb/s 0.78-pJ/b PAM-4 Crosstalk Cancellation Receiver With Active Crosstalk Extraction Technique in 28-nm CMOS	20
2.45 e-RMS Low-Random-Noise, 598.5 mW Low-Power, and 1.2 kfps High-Speed 2-Mp Global Shutter CMOS Image Sensor With Pixel-Level ADC and Memory	20
FLEX-CIM: A Flexible Kernel Size 1-GHz 181.6-TOPS/W 25.63-TOPS/mm² Analog Compute-in-Memory Macro	20
Design and Analysis of a 140-GHz T/R Front-End Module in 22-nm FD-SOI CMOS	20
A 0.31-THz Orbital-Angular-Momentum (OAM) Wave Transceiver in CMOS With Bits-to-OAM Mode Mapping	20
Highly Efficient Terahertz Beam-Steerable Integrated Radiator Based on Tunable Boundary Conditions	20
A mm-Wave Switched-Capacitor RFDAC	20
A 23-GHz TX/LNA Front-End Module for Inter-Satellite Links With 27.8% Peak Efficiency in the TX Path and 3.1-dB NF in the RX Path	19
A 0.67-to-5.4 TSOPs/W Spiking Neural Network Accelerator With 128/256 Reconfigurable Neurons and Asynchronous Fully Connected Synapses	19
VOTA: A Heterogeneous Multicore Visual Object Tracking Accelerator Using Correlation Filters	19
eCIMC: A 603.1-TOPS/W eDRAM-Based Cryogenic In-Memory Computing Accelerator Supporting Boolean/Convolutional Operations	19
Physical Layer Security Through Directional Modulation With Spatio-Temporal Millimeter-Wave Transmitter Arrays	19
A Compact E-Band Load-Modulation Balanced Power Amplifier in 65-nm CMOS	19
A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta–Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS	19
A Jitter Programmable Digital Bang-Bang PLL Using PVT-Invariant Stochastic Jitter Monitor	19
A Fully Integrated Nine-Ratio Switched-Capacitor Converter With Overlapped-Conversion-Ratio Modulation for IoT Applications	19
A 26/28/39-GHz Reconfigurable Phased-Array Receiver Front-End With Built-In Calibration Technique for 5G New Radio	19
EQZ-LDO: A Secure Digital Low Dropout Regulator Armed With Detection-Driven Protection Against Correlation Power Analysis	19
A Current Re-Use Quadrature RF Receiver Front-End for Low Power Applications: Blixator Circuit	19
A 56-Gb/s 8-mW PAM4 CDR/DMUX With High Jitter Tolerance	19
A 7.3-μ W 13-ENOB 98-dB SFDR Noise-Shaping SAR ADC With Duty-Cycled Amplifier and Mismatch Error Shaping	19
A Packaged 54-to-69-GHz Wideband 2T2R FMCW Radar Transceiver Employing Cascaded-PLL Topology and PTAT-Enhanced Temperature Compensation in 40-nm CMOS	19
A High-Resolution Pipelined-SAR ADC Using Cyclically Charged Floating Inverter Amplifier	19
Design and Analysis of 55–63-GHz Fundamental Quad-Core VCO With NMOS-Only Stacked Oscillator in 28-nm CMOS	19
Static CMOS Physically Unclonable Function Based on 4T Voltage Divider With 0.6%–1.5% Bit Instability at 0.4–1.8 V Operation in 180 nm	19
An Intrinsically Linear Multi-Rate Continuous-Time Zoom ADC Achieving 97.4-dB DR and 105.7-dB SFDR in 50-kHz Signal Bandwidth	19
Efficient RF-PA Two-Chip Supply Modulator Architecture for 4G LTE and 5G NR Dual-Connectivity RF Front End	19
A Chopper Class-D Amplifier for PSRR Improvement Over the Entire Audio Band	19
A 30.2-µ Vrms Horizontal Streak Noise 8.3-Mpixel 60-Frames/s CMOS Image Sensor With Skew-Relaxation ADC and On-Chip Testable Ramp Generator for Surveillance Camera	18
An Isolated DC–DC Converter Using a Cross-Coupled Shoot-Through-Free Class-D Oscillator With Low EMI Emissions	18
Multi-Watt-Level 4.9-GHz Silicon Power Amplifier for Portable Thermoacoustic Imaging	18
A Double Pulse Overlapping Laser Diode Driver With Minimum 100-ps Pulse for LiDAR System	18
A 72-dB SNDR 130-MS/s 0.8-mW Pipelined-SAR ADC Using a Distributed Averaging Correlated Level Shifting Ring Amplifier	18
An On-Chip Relaxation Oscillator in 5-nm FinFET Using a Frequency-Error Feedback Loop	18
A 14-b BW /Power Scalable Sensor Interface With a Dynamic Bandgap Reference	18
A 1.8-V GPIO With Design-Technology-Reliability Co-Optimization in Sub-3-nm GAA-NS Technology	18
A Multiply-Less Approximate SRAM Compute-In-Memory Macro for Neural-Network Inference	18
A Constant-Energy-Packet-Extraction-Based MPPT Technique With 98% Average Extraction Efficiency for Wide Range Generic Ambient Energy Scavenging Supporting 1000 × Source Resistance Range	18
Design of High-Resolution Continuous-Time Delta–Sigma Data Converters With Dual Return-to-Open DACs	18
A Power-Efficient Single-Mode Buck-Boost DC–DC Converter With Bilaterally Symmetrical Hybrid Topology	18
Guest Editorial: Introduction to the Special Section on the 2023 Asian Solid-State Circuits Conference (A-SSCC)	18
A Bi-Directional 300-GHz-Band Phased-Array Transceiver in 65-nm CMOS With Outphasing Transmitting Mode and LO Emission Cancellation	18
A Fully Integrated QPSK/16-QAM D-Band CMOS Transceiver With Mixed-Signal Baseband Circuitry Realizing Digital Interfaces	18
A BER-Suppressed PUF With an Amplification of Process Mismatch Effect in an Oscillator Collapse Topology	18
A PNP-Based Temperature Sensor With Continuous-Time Readout and ±0.1 ^∘C (3σ) Inaccuracy From -55 ^∘C to 125 ^∘C	18
An IR-UWB CMOS Transceiver With Extended Pulse Position Modulation	18
A Battery-to-3.4 V Hybrid Buck-Boost Converter With Always Reduced Conduction Loss	18
A Miniaturized Wireless Neural Implant With Body-Coupled Power Delivery and Data Transmission	18
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time	17
An Energy-Efficient and High-Data-Rate IR-UWB Transmitter for Intracortical Neural Sensing Interfaces	17
A 112-Gb/s —8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes	17
A Bipolar-Output Switched-Capacitor DC–DC Boost Converter With Residual-Energy-Recycling Regulation and Low Dropout Post-Filtering Techniques	17
Beyond Eliminating Timing Margin: An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator Without Accuracy Loss	17
A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68	17
A Nonuniform Sampling Lifetime Estimation Technique for Luminescent Oxygen Measurements for Biomedical Applications	17
Guest Editorial Introduction to the Special Issue on the 2022 IEEE International Solid-State Circuits Conference (ISSCC)	17
A 0.6–1.8-mW 3.4-dB NF Mixer-First Receiver With an N-Path Harmonic-Rejection Transformer-Mixer	17
A 64 Gb/s/pin Single-Ended PAM-4 Transmitter With a Merged Preemphasis Capacitive-Peaking Crosstalk Cancellation Scheme for Memory Interfaces in 28-nm CMOS	17
A Real-Time Speech Enhancement Processor for Hearing Aids in 28-nm CMOS	17
A 94.4% Peak Efficiency Coupled-Inductor Hybrid Step-Up Converter With Load-Independent Output Voltage Ripple	17
A 28-GHz Four-Channel Beamforming Front-End IC With Dual-Vector Variable Gain Phase Shifters for 64-Element Phased Array Antenna Module	17
A Monolithic GaN Power IC With On-Chip Gate Driving, Level Shifting, and Temperature Sensing, Achieving Direct 48-V/1-V DC–DC Conversion	17
Regenerative Breaking: Optimal Energy Recycling for Energy Minimization in Duty-Cycled Domains	17